2 * Copyright (c) 2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
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33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
52 #include "arch/x86/regs/apic.hh"
53 #include "arch/x86/interrupts.hh"
54 #include "arch/x86/intmessage.hh"
55 #include "cpu/base.hh"
56 #include "debug/LocalApic.hh"
57 #include "dev/x86/i82094aa.hh"
58 #include "dev/x86/pc.hh"
59 #include "dev/x86/south_bridge.hh"
60 #include "mem/packet_access.hh"
61 #include "sim/system.hh"
62 #include "sim/full_system.hh"
65 divideFromConf(uint32_t conf
)
67 // This figures out what division we want from the division configuration
68 // register in the local APIC. The encoding is a little odd but it can
69 // be deciphered fairly easily.
70 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
71 shift
= (shift
+ 1) % 8;
79 decodeAddr(Addr paddr
)
89 regNum
= APIC_VERSION
;
92 regNum
= APIC_TASK_PRIORITY
;
95 regNum
= APIC_ARBITRATION_PRIORITY
;
98 regNum
= APIC_PROCESSOR_PRIORITY
;
104 regNum
= APIC_LOGICAL_DESTINATION
;
107 regNum
= APIC_DESTINATION_FORMAT
;
110 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
128 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x8);
146 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x8);
164 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x8);
167 regNum
= APIC_ERROR_STATUS
;
170 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
173 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
176 regNum
= APIC_LVT_TIMER
;
179 regNum
= APIC_LVT_THERMAL_SENSOR
;
182 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
185 regNum
= APIC_LVT_LINT0
;
188 regNum
= APIC_LVT_LINT1
;
191 regNum
= APIC_LVT_ERROR
;
194 regNum
= APIC_INITIAL_COUNT
;
197 regNum
= APIC_CURRENT_COUNT
;
200 regNum
= APIC_DIVIDE_CONFIGURATION
;
203 // A reserved register field.
204 panic("Accessed reserved register field %#x.\n", paddr
);
212 X86ISA::Interrupts::read(PacketPtr pkt
)
214 Addr offset
= pkt
->getAddr() - pioAddr
;
215 //Make sure we're at least only accessing one register.
216 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
217 panic("Accessed more than one register at a time in the APIC!\n");
218 ApicRegIndex reg
= decodeAddr(offset
);
219 uint32_t val
= htog(readReg(reg
));
221 "Reading Local APIC register %d at offset %#x as %#x.\n",
223 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
224 pkt
->makeAtomicResponse();
229 X86ISA::Interrupts::write(PacketPtr pkt
)
231 Addr offset
= pkt
->getAddr() - pioAddr
;
232 //Make sure we're at least only accessing one register.
233 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
234 panic("Accessed more than one register at a time in the APIC!\n");
235 ApicRegIndex reg
= decodeAddr(offset
);
236 uint32_t val
= regs
[reg
];
237 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
239 "Writing Local APIC register %d at offset %#x as %#x.\n",
240 reg
, offset
, gtoh(val
));
241 setReg(reg
, gtoh(val
));
242 pkt
->makeAtomicResponse();
246 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
247 uint8_t deliveryMode
, bool level
)
250 * Fixed and lowest-priority delivery mode interrupts are handled
251 * using the IRR/ISR registers, checking against the TPR, etc.
252 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
254 if (deliveryMode
== DeliveryMode::Fixed
||
255 deliveryMode
== DeliveryMode::LowestPriority
) {
256 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
257 DeliveryMode::names
[deliveryMode
]);
258 // Queue up the interrupt in the IRR.
261 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
262 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
264 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
266 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
269 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
270 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
271 DeliveryMode::names
[deliveryMode
]);
272 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
273 pendingUnmaskableInt
= pendingSmi
= true;
275 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
276 pendingUnmaskableInt
= pendingNmi
= true;
278 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
279 pendingExtInt
= true;
280 extIntVector
= vector
;
281 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
282 pendingUnmaskableInt
= pendingInit
= true;
284 } else if (deliveryMode
== DeliveryMode::SIPI
&&
285 !pendingStartup
&& !startedUp
) {
286 pendingUnmaskableInt
= pendingStartup
= true;
287 startupVector
= vector
;
296 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
299 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
300 panic("Local APICs can't be moved between CPUs"
301 " with different IDs.\n");
304 initialApicId
= cpu
->cpuId();
305 regs
[APIC_ID
] = (initialApicId
<< 24);
310 X86ISA::Interrupts::init()
313 // The local apic must register its address ranges on both its pio port
314 // via the basicpiodevice(piodevice) init() function and its int port
315 // that it inherited from IntDev. Note IntDev is not a SimObject itself.
317 BasicPioDevice::init();
320 // the slave port has a range so inform the connected master
321 intSlavePort
.sendRangeChange();
326 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
328 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
329 assert(pkt
->cmd
== MemCmd::MessageReq
);
334 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
336 "Got Trigger Interrupt message with vector %#x.\n",
339 requestInterrupt(message
.vector
,
340 message
.deliveryMode
, message
.trigger
);
344 panic("Local apic got unknown interrupt message at offset %#x.\n",
348 pkt
->makeAtomicResponse();
354 X86ISA::Interrupts::recvResponse(PacketPtr pkt
)
356 assert(!pkt
->isError());
357 assert(pkt
->cmd
== MemCmd::MessageResp
);
358 if (--pendingIPIs
== 0) {
359 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
360 // Record that the ICR is now idle.
361 low
.deliveryStatus
= 0;
362 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
364 DPRINTF(LocalApic
, "ICR is now idle.\n");
370 X86ISA::Interrupts::getAddrRanges()
372 AddrRangeList ranges
;
373 Range
<Addr
> range
= RangeEx(x86LocalAPICAddress(initialApicId
, 0),
374 x86LocalAPICAddress(initialApicId
, 0) +
376 ranges
.push_back(range
);
377 pioAddr
= range
.start
;
383 X86ISA::Interrupts::getIntAddrRange()
385 AddrRangeList ranges
;
386 ranges
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
387 x86InterruptAddress(initialApicId
, 0) +
388 PhysAddrAPICRangeSize
));
394 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
396 if (reg
>= APIC_TRIGGER_MODE(0) &&
397 reg
<= APIC_TRIGGER_MODE(15)) {
398 panic("Local APIC Trigger Mode registers are unimplemented.\n");
401 case APIC_ARBITRATION_PRIORITY
:
402 panic("Local APIC Arbitration Priority register unimplemented.\n");
404 case APIC_PROCESSOR_PRIORITY
:
405 panic("Local APIC Processor Priority register unimplemented.\n");
407 case APIC_ERROR_STATUS
:
408 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
410 case APIC_CURRENT_COUNT
:
412 if (apicTimerEvent
.scheduled()) {
414 // Compute how many m5 ticks happen per count.
415 uint64_t ticksPerCount
= clock
*
416 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
417 // Compute how many m5 ticks are left.
418 uint64_t val
= apicTimerEvent
.when() - curTick();
419 // Turn that into a count.
420 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
433 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
435 uint32_t newVal
= val
;
436 if (reg
>= APIC_IN_SERVICE(0) &&
437 reg
<= APIC_IN_SERVICE(15)) {
438 panic("Local APIC In-Service registers are unimplemented.\n");
440 if (reg
>= APIC_TRIGGER_MODE(0) &&
441 reg
<= APIC_TRIGGER_MODE(15)) {
442 panic("Local APIC Trigger Mode registers are unimplemented.\n");
444 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
445 reg
<= APIC_INTERRUPT_REQUEST(15)) {
446 panic("Local APIC Interrupt Request registers "
447 "are unimplemented.\n");
454 // The Local APIC Version register is read only.
456 case APIC_TASK_PRIORITY
:
459 case APIC_ARBITRATION_PRIORITY
:
460 panic("Local APIC Arbitration Priority register unimplemented.\n");
462 case APIC_PROCESSOR_PRIORITY
:
463 panic("Local APIC Processor Priority register unimplemented.\n");
466 // Remove the interrupt that just completed from the local apic state.
467 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
470 case APIC_LOGICAL_DESTINATION
:
471 newVal
= val
& 0xFF000000;
473 case APIC_DESTINATION_FORMAT
:
474 newVal
= val
| 0x0FFFFFFF;
476 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
477 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
478 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
480 warn("Focus processor checking not implemented.\n");
482 case APIC_ERROR_STATUS
:
484 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
485 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
488 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
494 case APIC_INTERRUPT_COMMAND_LOW
:
496 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
497 // Check if we're already sending an IPI.
498 if (low
.deliveryStatus
) {
503 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
504 // Record that an IPI is being sent.
505 low
.deliveryStatus
= 1;
506 TriggerIntMessage message
= 0;
507 message
.destination
= high
.destination
;
508 message
.vector
= low
.vector
;
509 message
.deliveryMode
= low
.deliveryMode
;
510 message
.destMode
= low
.destMode
;
511 message
.level
= low
.level
;
512 message
.trigger
= low
.trigger
;
513 bool timing
= sys
->getMemoryMode() == Enums::timing
;
514 // Be careful no updates of the delivery status bit get lost.
515 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
517 int numContexts
= sys
->numContexts();
518 switch (low
.destShorthand
) {
520 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
521 panic("Lowest priority delivery mode "
522 "IPIs aren't implemented.\n");
524 if (message
.destMode
== 1) {
525 int dest
= message
.destination
;
526 hack_once("Assuming logical destinations are 1 << id.\n");
527 for (int i
= 0; i
< numContexts
; i
++) {
533 if (message
.destination
== 0xFF) {
534 for (int i
= 0; i
< numContexts
; i
++) {
535 if (i
== initialApicId
) {
536 requestInterrupt(message
.vector
,
537 message
.deliveryMode
, message
.trigger
);
543 if (message
.destination
== initialApicId
) {
544 requestInterrupt(message
.vector
,
545 message
.deliveryMode
, message
.trigger
);
547 apics
.push_back(message
.destination
);
554 requestInterrupt(message
.vector
,
555 message
.deliveryMode
, message
.trigger
);
558 requestInterrupt(message
.vector
,
559 message
.deliveryMode
, message
.trigger
);
563 for (int i
= 0; i
< numContexts
; i
++) {
564 if (i
!= initialApicId
) {
571 pendingIPIs
+= apics
.size();
572 intMasterPort
.sendMessage(apics
, message
, timing
);
573 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
577 case APIC_LVT_THERMAL_SENSOR
:
578 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
583 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
584 newVal
= (val
& ~readOnlyMask
) |
585 (regs
[reg
] & readOnlyMask
);
588 case APIC_INITIAL_COUNT
:
591 newVal
= bits(val
, 31, 0);
592 // Compute how many timer ticks we're being programmed for.
593 uint64_t newCount
= newVal
*
594 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
595 // Schedule on the edge of the next tick plus the new count.
596 Tick offset
= curTick() % clock
;
598 reschedule(apicTimerEvent
,
599 curTick() + (newCount
+ 1) * clock
- offset
, true);
601 reschedule(apicTimerEvent
,
602 curTick() + newCount
* clock
, true);
606 case APIC_CURRENT_COUNT
:
607 //Local APIC Current Count register is read only.
609 case APIC_DIVIDE_CONFIGURATION
:
620 X86ISA::Interrupts::Interrupts(Params
* p
) :
621 BasicPioDevice(p
), IntDev(this, p
->int_latency
), latency(p
->pio_latency
),
623 apicTimerEvent(this),
624 pendingSmi(false), smiVector(0),
625 pendingNmi(false), nmiVector(0),
626 pendingExtInt(false), extIntVector(0),
627 pendingInit(false), initVector(0),
628 pendingStartup(false), startupVector(0),
629 startedUp(false), pendingUnmaskableInt(false),
630 pendingIPIs(0), cpu(NULL
),
631 intSlavePort(name() + ".int_slave", this, this, latency
)
634 memset(regs
, 0, sizeof(regs
));
635 //Set the local apic DFR to the flat model.
636 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
643 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
645 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
646 if (pendingUnmaskableInt
) {
647 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
652 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
655 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
656 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
657 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
665 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
667 assert(checkInterrupts(tc
));
668 // These are all probably fairly uncommon, so we'll make them easier to
670 if (pendingUnmaskableInt
) {
672 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
673 return new SystemManagementInterrupt();
674 } else if (pendingNmi
) {
675 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
676 return new NonMaskableInterrupt(nmiVector
);
677 } else if (pendingInit
) {
678 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
679 return new InitInterrupt(initVector
);
680 } else if (pendingStartup
) {
681 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
682 return new StartupInterrupt(startupVector
);
684 panic("pendingUnmaskableInt set, but no unmaskable "
685 "ints were pending.\n");
688 } else if (pendingExtInt
) {
689 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
690 return new ExternalInterrupt(extIntVector
);
692 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
693 // The only thing left are fixed and lowest priority interrupts.
694 return new ExternalInterrupt(IRRV
);
699 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
701 assert(checkInterrupts(tc
));
702 if (pendingUnmaskableInt
) {
704 DPRINTF(LocalApic
, "SMI sent to core.\n");
706 } else if (pendingNmi
) {
707 DPRINTF(LocalApic
, "NMI sent to core.\n");
709 } else if (pendingInit
) {
710 DPRINTF(LocalApic
, "Init sent to core.\n");
713 } else if (pendingStartup
) {
714 DPRINTF(LocalApic
, "SIPI sent to core.\n");
715 pendingStartup
= false;
718 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
719 pendingUnmaskableInt
= false;
720 } else if (pendingExtInt
) {
721 pendingExtInt
= false;
723 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
724 // Mark the interrupt as "in service".
726 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
727 // Clear it out of the IRR.
728 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
734 X86ISA::Interrupts::serialize(std::ostream
&os
)
736 SERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
737 SERIALIZE_SCALAR(clock
);
738 SERIALIZE_SCALAR(pendingSmi
);
739 SERIALIZE_SCALAR(smiVector
);
740 SERIALIZE_SCALAR(pendingNmi
);
741 SERIALIZE_SCALAR(nmiVector
);
742 SERIALIZE_SCALAR(pendingExtInt
);
743 SERIALIZE_SCALAR(extIntVector
);
744 SERIALIZE_SCALAR(pendingInit
);
745 SERIALIZE_SCALAR(initVector
);
746 SERIALIZE_SCALAR(pendingStartup
);
747 SERIALIZE_SCALAR(startupVector
);
748 SERIALIZE_SCALAR(startedUp
);
749 SERIALIZE_SCALAR(pendingUnmaskableInt
);
750 SERIALIZE_SCALAR(pendingIPIs
);
751 SERIALIZE_SCALAR(IRRV
);
752 SERIALIZE_SCALAR(ISRV
);
753 bool apicTimerEventScheduled
= apicTimerEvent
.scheduled();
754 SERIALIZE_SCALAR(apicTimerEventScheduled
);
755 Tick apicTimerEventTick
= apicTimerEvent
.when();
756 SERIALIZE_SCALAR(apicTimerEventTick
);
760 X86ISA::Interrupts::unserialize(Checkpoint
*cp
, const std::string
§ion
)
762 UNSERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
763 UNSERIALIZE_SCALAR(clock
);
764 UNSERIALIZE_SCALAR(pendingSmi
);
765 UNSERIALIZE_SCALAR(smiVector
);
766 UNSERIALIZE_SCALAR(pendingNmi
);
767 UNSERIALIZE_SCALAR(nmiVector
);
768 UNSERIALIZE_SCALAR(pendingExtInt
);
769 UNSERIALIZE_SCALAR(extIntVector
);
770 UNSERIALIZE_SCALAR(pendingInit
);
771 UNSERIALIZE_SCALAR(initVector
);
772 UNSERIALIZE_SCALAR(pendingStartup
);
773 UNSERIALIZE_SCALAR(startupVector
);
774 UNSERIALIZE_SCALAR(startedUp
);
775 UNSERIALIZE_SCALAR(pendingUnmaskableInt
);
776 UNSERIALIZE_SCALAR(pendingIPIs
);
777 UNSERIALIZE_SCALAR(IRRV
);
778 UNSERIALIZE_SCALAR(ISRV
);
779 bool apicTimerEventScheduled
;
780 UNSERIALIZE_SCALAR(apicTimerEventScheduled
);
781 if (apicTimerEventScheduled
) {
782 Tick apicTimerEventTick
;
783 UNSERIALIZE_SCALAR(apicTimerEventTick
);
784 if (apicTimerEvent
.scheduled()) {
785 reschedule(apicTimerEvent
, apicTimerEventTick
, true);
787 schedule(apicTimerEvent
, apicTimerEventTick
);
793 X86LocalApicParams::create()
795 return new X86ISA::Interrupts(this);