2 * Copyright (c) 2012-2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
26 * Redistribution and use in source and binary forms, with or without
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52 #include "arch/x86/regs/apic.hh"
53 #include "arch/x86/interrupts.hh"
54 #include "arch/x86/intmessage.hh"
55 #include "cpu/base.hh"
56 #include "debug/LocalApic.hh"
57 #include "dev/x86/i82094aa.hh"
58 #include "dev/x86/pc.hh"
59 #include "dev/x86/south_bridge.hh"
60 #include "mem/packet_access.hh"
61 #include "sim/system.hh"
62 #include "sim/full_system.hh"
65 divideFromConf(uint32_t conf
)
67 // This figures out what division we want from the division configuration
68 // register in the local APIC. The encoding is a little odd but it can
69 // be deciphered fairly easily.
70 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
71 shift
= (shift
+ 1) % 8;
79 decodeAddr(Addr paddr
)
89 regNum
= APIC_VERSION
;
92 regNum
= APIC_TASK_PRIORITY
;
95 regNum
= APIC_ARBITRATION_PRIORITY
;
98 regNum
= APIC_PROCESSOR_PRIORITY
;
104 regNum
= APIC_LOGICAL_DESTINATION
;
107 regNum
= APIC_DESTINATION_FORMAT
;
110 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
128 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x8);
146 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x8);
164 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x8);
167 regNum
= APIC_ERROR_STATUS
;
170 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
173 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
176 regNum
= APIC_LVT_TIMER
;
179 regNum
= APIC_LVT_THERMAL_SENSOR
;
182 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
185 regNum
= APIC_LVT_LINT0
;
188 regNum
= APIC_LVT_LINT1
;
191 regNum
= APIC_LVT_ERROR
;
194 regNum
= APIC_INITIAL_COUNT
;
197 regNum
= APIC_CURRENT_COUNT
;
200 regNum
= APIC_DIVIDE_CONFIGURATION
;
203 // A reserved register field.
204 panic("Accessed reserved register field %#x.\n", paddr
);
212 X86ISA::Interrupts::read(PacketPtr pkt
)
214 Addr offset
= pkt
->getAddr() - pioAddr
;
215 //Make sure we're at least only accessing one register.
216 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
217 panic("Accessed more than one register at a time in the APIC!\n");
218 ApicRegIndex reg
= decodeAddr(offset
);
219 uint32_t val
= htog(readReg(reg
));
221 "Reading Local APIC register %d at offset %#x as %#x.\n",
223 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
224 pkt
->makeAtomicResponse();
229 X86ISA::Interrupts::write(PacketPtr pkt
)
231 Addr offset
= pkt
->getAddr() - pioAddr
;
232 //Make sure we're at least only accessing one register.
233 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
234 panic("Accessed more than one register at a time in the APIC!\n");
235 ApicRegIndex reg
= decodeAddr(offset
);
236 uint32_t val
= regs
[reg
];
237 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
239 "Writing Local APIC register %d at offset %#x as %#x.\n",
240 reg
, offset
, gtoh(val
));
241 setReg(reg
, gtoh(val
));
242 pkt
->makeAtomicResponse();
246 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
247 uint8_t deliveryMode
, bool level
)
250 * Fixed and lowest-priority delivery mode interrupts are handled
251 * using the IRR/ISR registers, checking against the TPR, etc.
252 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
254 if (deliveryMode
== DeliveryMode::Fixed
||
255 deliveryMode
== DeliveryMode::LowestPriority
) {
256 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
257 DeliveryMode::names
[deliveryMode
]);
258 // Queue up the interrupt in the IRR.
261 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
262 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
264 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
266 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
269 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
270 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
271 DeliveryMode::names
[deliveryMode
]);
272 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
273 pendingUnmaskableInt
= pendingSmi
= true;
275 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
276 pendingUnmaskableInt
= pendingNmi
= true;
278 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
279 pendingExtInt
= true;
280 extIntVector
= vector
;
281 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
282 pendingUnmaskableInt
= pendingInit
= true;
284 } else if (deliveryMode
== DeliveryMode::SIPI
&&
285 !pendingStartup
&& !startedUp
) {
286 pendingUnmaskableInt
= pendingStartup
= true;
287 startupVector
= vector
;
296 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
299 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
300 panic("Local APICs can't be moved between CPUs"
301 " with different IDs.\n");
304 initialApicId
= cpu
->cpuId();
305 regs
[APIC_ID
] = (initialApicId
<< 24);
306 pioAddr
= x86LocalAPICAddress(initialApicId
, 0);
311 X86ISA::Interrupts::init()
314 // The local apic must register its address ranges on both its pio
315 // port via the basicpiodevice(piodevice) init() function and its
316 // int port that it inherited from IntDevice. Note IntDevice is
317 // not a SimObject itself.
319 BasicPioDevice::init();
322 // the slave port has a range so inform the connected master
323 intSlavePort
.sendRangeChange();
328 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
330 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
331 assert(pkt
->cmd
== MemCmd::MessageReq
);
336 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
338 "Got Trigger Interrupt message with vector %#x.\n",
341 requestInterrupt(message
.vector
,
342 message
.deliveryMode
, message
.trigger
);
346 panic("Local apic got unknown interrupt message at offset %#x.\n",
350 pkt
->makeAtomicResponse();
356 X86ISA::Interrupts::recvResponse(PacketPtr pkt
)
358 assert(!pkt
->isError());
359 assert(pkt
->cmd
== MemCmd::MessageResp
);
360 if (--pendingIPIs
== 0) {
361 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
362 // Record that the ICR is now idle.
363 low
.deliveryStatus
= 0;
364 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
366 DPRINTF(LocalApic
, "ICR is now idle.\n");
372 X86ISA::Interrupts::getIntAddrRange() const
374 AddrRangeList ranges
;
375 ranges
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
376 x86InterruptAddress(initialApicId
, 0) +
377 PhysAddrAPICRangeSize
));
383 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
385 if (reg
>= APIC_TRIGGER_MODE(0) &&
386 reg
<= APIC_TRIGGER_MODE(15)) {
387 panic("Local APIC Trigger Mode registers are unimplemented.\n");
390 case APIC_ARBITRATION_PRIORITY
:
391 panic("Local APIC Arbitration Priority register unimplemented.\n");
393 case APIC_PROCESSOR_PRIORITY
:
394 panic("Local APIC Processor Priority register unimplemented.\n");
396 case APIC_ERROR_STATUS
:
397 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
399 case APIC_CURRENT_COUNT
:
401 if (apicTimerEvent
.scheduled()) {
402 // Compute how many m5 ticks happen per count.
403 uint64_t ticksPerCount
= clockPeriod() *
404 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
405 // Compute how many m5 ticks are left.
406 uint64_t val
= apicTimerEvent
.when() - curTick();
407 // Turn that into a count.
408 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
421 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
423 uint32_t newVal
= val
;
424 if (reg
>= APIC_IN_SERVICE(0) &&
425 reg
<= APIC_IN_SERVICE(15)) {
426 panic("Local APIC In-Service registers are unimplemented.\n");
428 if (reg
>= APIC_TRIGGER_MODE(0) &&
429 reg
<= APIC_TRIGGER_MODE(15)) {
430 panic("Local APIC Trigger Mode registers are unimplemented.\n");
432 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
433 reg
<= APIC_INTERRUPT_REQUEST(15)) {
434 panic("Local APIC Interrupt Request registers "
435 "are unimplemented.\n");
442 // The Local APIC Version register is read only.
444 case APIC_TASK_PRIORITY
:
447 case APIC_ARBITRATION_PRIORITY
:
448 panic("Local APIC Arbitration Priority register unimplemented.\n");
450 case APIC_PROCESSOR_PRIORITY
:
451 panic("Local APIC Processor Priority register unimplemented.\n");
454 // Remove the interrupt that just completed from the local apic state.
455 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
458 case APIC_LOGICAL_DESTINATION
:
459 newVal
= val
& 0xFF000000;
461 case APIC_DESTINATION_FORMAT
:
462 newVal
= val
| 0x0FFFFFFF;
464 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
465 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
466 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
468 warn("Focus processor checking not implemented.\n");
470 case APIC_ERROR_STATUS
:
472 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
473 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
476 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
482 case APIC_INTERRUPT_COMMAND_LOW
:
484 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
485 // Check if we're already sending an IPI.
486 if (low
.deliveryStatus
) {
491 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
492 // Record that an IPI is being sent.
493 low
.deliveryStatus
= 1;
494 TriggerIntMessage message
= 0;
495 message
.destination
= high
.destination
;
496 message
.vector
= low
.vector
;
497 message
.deliveryMode
= low
.deliveryMode
;
498 message
.destMode
= low
.destMode
;
499 message
.level
= low
.level
;
500 message
.trigger
= low
.trigger
;
501 bool timing(sys
->isTimingMode());
502 // Be careful no updates of the delivery status bit get lost.
503 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
505 int numContexts
= sys
->numContexts();
506 switch (low
.destShorthand
) {
508 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
509 panic("Lowest priority delivery mode "
510 "IPIs aren't implemented.\n");
512 if (message
.destMode
== 1) {
513 int dest
= message
.destination
;
514 hack_once("Assuming logical destinations are 1 << id.\n");
515 for (int i
= 0; i
< numContexts
; i
++) {
521 if (message
.destination
== 0xFF) {
522 for (int i
= 0; i
< numContexts
; i
++) {
523 if (i
== initialApicId
) {
524 requestInterrupt(message
.vector
,
525 message
.deliveryMode
, message
.trigger
);
531 if (message
.destination
== initialApicId
) {
532 requestInterrupt(message
.vector
,
533 message
.deliveryMode
, message
.trigger
);
535 apics
.push_back(message
.destination
);
542 requestInterrupt(message
.vector
,
543 message
.deliveryMode
, message
.trigger
);
546 requestInterrupt(message
.vector
,
547 message
.deliveryMode
, message
.trigger
);
551 for (int i
= 0; i
< numContexts
; i
++) {
552 if (i
!= initialApicId
) {
559 pendingIPIs
+= apics
.size();
560 intMasterPort
.sendMessage(apics
, message
, timing
);
561 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
565 case APIC_LVT_THERMAL_SENSOR
:
566 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
571 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
572 newVal
= (val
& ~readOnlyMask
) |
573 (regs
[reg
] & readOnlyMask
);
576 case APIC_INITIAL_COUNT
:
578 newVal
= bits(val
, 31, 0);
579 // Compute how many timer ticks we're being programmed for.
580 uint64_t newCount
= newVal
*
581 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
582 // Schedule on the edge of the next tick plus the new count.
583 Tick offset
= curTick() % clockPeriod();
585 reschedule(apicTimerEvent
,
586 curTick() + (newCount
+ 1) *
587 clockPeriod() - offset
, true);
590 reschedule(apicTimerEvent
,
591 curTick() + newCount
*
592 clockPeriod(), true);
596 case APIC_CURRENT_COUNT
:
597 //Local APIC Current Count register is read only.
599 case APIC_DIVIDE_CONFIGURATION
:
610 X86ISA::Interrupts::Interrupts(Params
* p
)
611 : BasicPioDevice(p
, PageBytes
), IntDevice(this, p
->int_latency
),
612 apicTimerEvent(this),
613 pendingSmi(false), smiVector(0),
614 pendingNmi(false), nmiVector(0),
615 pendingExtInt(false), extIntVector(0),
616 pendingInit(false), initVector(0),
617 pendingStartup(false), startupVector(0),
618 startedUp(false), pendingUnmaskableInt(false),
619 pendingIPIs(0), cpu(NULL
),
620 intSlavePort(name() + ".int_slave", this, this)
622 memset(regs
, 0, sizeof(regs
));
623 //Set the local apic DFR to the flat model.
624 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
631 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
633 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
634 if (pendingUnmaskableInt
) {
635 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
640 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
643 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
644 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
645 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
653 X86ISA::Interrupts::checkInterruptsRaw() const
655 return pendingUnmaskableInt
|| pendingExtInt
||
656 (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
657 bits(regs
[APIC_TASK_PRIORITY
], 7, 4));
661 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
663 assert(checkInterrupts(tc
));
664 // These are all probably fairly uncommon, so we'll make them easier to
666 if (pendingUnmaskableInt
) {
668 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
669 return new SystemManagementInterrupt();
670 } else if (pendingNmi
) {
671 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
672 return new NonMaskableInterrupt(nmiVector
);
673 } else if (pendingInit
) {
674 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
675 return new InitInterrupt(initVector
);
676 } else if (pendingStartup
) {
677 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
678 return new StartupInterrupt(startupVector
);
680 panic("pendingUnmaskableInt set, but no unmaskable "
681 "ints were pending.\n");
684 } else if (pendingExtInt
) {
685 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
686 return new ExternalInterrupt(extIntVector
);
688 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
689 // The only thing left are fixed and lowest priority interrupts.
690 return new ExternalInterrupt(IRRV
);
695 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
697 assert(checkInterrupts(tc
));
698 if (pendingUnmaskableInt
) {
700 DPRINTF(LocalApic
, "SMI sent to core.\n");
702 } else if (pendingNmi
) {
703 DPRINTF(LocalApic
, "NMI sent to core.\n");
705 } else if (pendingInit
) {
706 DPRINTF(LocalApic
, "Init sent to core.\n");
709 } else if (pendingStartup
) {
710 DPRINTF(LocalApic
, "SIPI sent to core.\n");
711 pendingStartup
= false;
714 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
715 pendingUnmaskableInt
= false;
716 } else if (pendingExtInt
) {
717 pendingExtInt
= false;
719 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
720 // Mark the interrupt as "in service".
722 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
723 // Clear it out of the IRR.
724 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
730 X86ISA::Interrupts::serialize(std::ostream
&os
)
732 SERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
733 SERIALIZE_SCALAR(pendingSmi
);
734 SERIALIZE_SCALAR(smiVector
);
735 SERIALIZE_SCALAR(pendingNmi
);
736 SERIALIZE_SCALAR(nmiVector
);
737 SERIALIZE_SCALAR(pendingExtInt
);
738 SERIALIZE_SCALAR(extIntVector
);
739 SERIALIZE_SCALAR(pendingInit
);
740 SERIALIZE_SCALAR(initVector
);
741 SERIALIZE_SCALAR(pendingStartup
);
742 SERIALIZE_SCALAR(startupVector
);
743 SERIALIZE_SCALAR(startedUp
);
744 SERIALIZE_SCALAR(pendingUnmaskableInt
);
745 SERIALIZE_SCALAR(pendingIPIs
);
746 SERIALIZE_SCALAR(IRRV
);
747 SERIALIZE_SCALAR(ISRV
);
748 bool apicTimerEventScheduled
= apicTimerEvent
.scheduled();
749 SERIALIZE_SCALAR(apicTimerEventScheduled
);
750 Tick apicTimerEventTick
= apicTimerEvent
.when();
751 SERIALIZE_SCALAR(apicTimerEventTick
);
755 X86ISA::Interrupts::unserialize(Checkpoint
*cp
, const std::string
§ion
)
757 UNSERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
758 UNSERIALIZE_SCALAR(pendingSmi
);
759 UNSERIALIZE_SCALAR(smiVector
);
760 UNSERIALIZE_SCALAR(pendingNmi
);
761 UNSERIALIZE_SCALAR(nmiVector
);
762 UNSERIALIZE_SCALAR(pendingExtInt
);
763 UNSERIALIZE_SCALAR(extIntVector
);
764 UNSERIALIZE_SCALAR(pendingInit
);
765 UNSERIALIZE_SCALAR(initVector
);
766 UNSERIALIZE_SCALAR(pendingStartup
);
767 UNSERIALIZE_SCALAR(startupVector
);
768 UNSERIALIZE_SCALAR(startedUp
);
769 UNSERIALIZE_SCALAR(pendingUnmaskableInt
);
770 UNSERIALIZE_SCALAR(pendingIPIs
);
771 UNSERIALIZE_SCALAR(IRRV
);
772 UNSERIALIZE_SCALAR(ISRV
);
773 bool apicTimerEventScheduled
;
774 UNSERIALIZE_SCALAR(apicTimerEventScheduled
);
775 if (apicTimerEventScheduled
) {
776 Tick apicTimerEventTick
;
777 UNSERIALIZE_SCALAR(apicTimerEventTick
);
778 if (apicTimerEvent
.scheduled()) {
779 reschedule(apicTimerEvent
, apicTimerEventTick
, true);
781 schedule(apicTimerEvent
, apicTimerEventTick
);
787 X86LocalApicParams::create()
789 return new X86ISA::Interrupts(this);