2 * Copyright (c) 2012-2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
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24 * modified or unmodified, in source code or in binary form.
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52 #include "arch/x86/interrupts.hh"
57 #include "arch/x86/intmessage.hh"
58 #include "arch/x86/regs/apic.hh"
59 #include "cpu/base.hh"
60 #include "debug/LocalApic.hh"
61 #include "dev/x86/i82094aa.hh"
62 #include "dev/x86/pc.hh"
63 #include "dev/x86/south_bridge.hh"
64 #include "mem/packet_access.hh"
65 #include "sim/full_system.hh"
66 #include "sim/system.hh"
69 divideFromConf(uint32_t conf
)
71 // This figures out what division we want from the division configuration
72 // register in the local APIC. The encoding is a little odd but it can
73 // be deciphered fairly easily.
74 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
75 shift
= (shift
+ 1) % 8;
83 decodeAddr(Addr paddr
)
93 regNum
= APIC_VERSION
;
96 regNum
= APIC_TASK_PRIORITY
;
99 regNum
= APIC_ARBITRATION_PRIORITY
;
102 regNum
= APIC_PROCESSOR_PRIORITY
;
108 regNum
= APIC_LOGICAL_DESTINATION
;
111 regNum
= APIC_DESTINATION_FORMAT
;
114 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
124 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x10);
134 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x10);
144 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x10);
147 regNum
= APIC_ERROR_STATUS
;
150 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
153 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
156 regNum
= APIC_LVT_TIMER
;
159 regNum
= APIC_LVT_THERMAL_SENSOR
;
162 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
165 regNum
= APIC_LVT_LINT0
;
168 regNum
= APIC_LVT_LINT1
;
171 regNum
= APIC_LVT_ERROR
;
174 regNum
= APIC_INITIAL_COUNT
;
177 regNum
= APIC_CURRENT_COUNT
;
180 regNum
= APIC_DIVIDE_CONFIGURATION
;
183 // A reserved register field.
184 panic("Accessed reserved register field %#x.\n", paddr
);
192 X86ISA::Interrupts::read(PacketPtr pkt
)
194 Addr offset
= pkt
->getAddr() - pioAddr
;
195 // Make sure we're at least only accessing one register.
196 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
197 panic("Accessed more than one register at a time in the APIC!\n");
198 ApicRegIndex reg
= decodeAddr(offset
);
199 uint32_t val
= htog(readReg(reg
));
201 "Reading Local APIC register %d at offset %#x as %#x.\n",
203 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
204 pkt
->makeAtomicResponse();
209 X86ISA::Interrupts::write(PacketPtr pkt
)
211 Addr offset
= pkt
->getAddr() - pioAddr
;
212 // Make sure we're at least only accessing one register.
213 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
214 panic("Accessed more than one register at a time in the APIC!\n");
215 ApicRegIndex reg
= decodeAddr(offset
);
216 uint32_t val
= regs
[reg
];
217 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
219 "Writing Local APIC register %d at offset %#x as %#x.\n",
220 reg
, offset
, gtoh(val
));
221 setReg(reg
, gtoh(val
));
222 pkt
->makeAtomicResponse();
226 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
227 uint8_t deliveryMode
, bool level
)
230 * Fixed and lowest-priority delivery mode interrupts are handled
231 * using the IRR/ISR registers, checking against the TPR, etc.
232 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
234 if (deliveryMode
== DeliveryMode::Fixed
||
235 deliveryMode
== DeliveryMode::LowestPriority
) {
236 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
237 DeliveryMode::names
[deliveryMode
]);
238 // Queue up the interrupt in the IRR.
241 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
242 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
244 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
246 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
249 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
250 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
251 DeliveryMode::names
[deliveryMode
]);
252 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
253 pendingUnmaskableInt
= pendingSmi
= true;
255 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
256 pendingUnmaskableInt
= pendingNmi
= true;
258 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
259 pendingExtInt
= true;
260 extIntVector
= vector
;
261 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
262 pendingUnmaskableInt
= pendingInit
= true;
264 } else if (deliveryMode
== DeliveryMode::SIPI
&&
265 !pendingStartup
&& !startedUp
) {
266 pendingUnmaskableInt
= pendingStartup
= true;
267 startupVector
= vector
;
276 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
279 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
280 panic("Local APICs can't be moved between CPUs"
281 " with different IDs.\n");
284 initialApicId
= cpu
->cpuId();
285 regs
[APIC_ID
] = (initialApicId
<< 24);
286 pioAddr
= x86LocalAPICAddress(initialApicId
, 0);
291 X86ISA::Interrupts::init()
294 // The local apic must register its address ranges on its pio
295 // port via the basicpiodevice(piodevice) init() function.
298 // The slave port has a range, so inform the connected master.
299 intSlavePort
.sendRangeChange();
300 // If the master port isn't connected, we can't send interrupts anywhere.
301 panic_if(!intMasterPort
.isConnected(),
302 "Int port not connected to anything!");
307 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
309 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
310 assert(pkt
->cmd
== MemCmd::WriteReq
);
315 TriggerIntMessage message
= pkt
->getRaw
<TriggerIntMessage
>();
317 "Got Trigger Interrupt message with vector %#x.\n",
320 requestInterrupt(message
.vector
,
321 message
.deliveryMode
, message
.trigger
);
325 panic("Local apic got unknown interrupt message at offset %#x.\n",
329 pkt
->makeAtomicResponse();
335 X86ISA::Interrupts::completeIPI(PacketPtr pkt
)
337 if (--pendingIPIs
== 0) {
338 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
339 // Record that the ICR is now idle.
340 low
.deliveryStatus
= 0;
341 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
343 DPRINTF(LocalApic
, "ICR is now idle.\n");
349 X86ISA::Interrupts::getAddrRanges() const
352 AddrRangeList ranges
;
353 ranges
.push_back(RangeSize(pioAddr
, PageBytes
));
359 X86ISA::Interrupts::getIntAddrRange() const
361 AddrRangeList ranges
;
362 ranges
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
363 x86InterruptAddress(initialApicId
, 0) +
364 PhysAddrAPICRangeSize
));
370 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
372 if (reg
>= APIC_TRIGGER_MODE(0) &&
373 reg
<= APIC_TRIGGER_MODE(15)) {
374 panic("Local APIC Trigger Mode registers are unimplemented.\n");
377 case APIC_ARBITRATION_PRIORITY
:
378 panic("Local APIC Arbitration Priority register unimplemented.\n");
380 case APIC_PROCESSOR_PRIORITY
:
381 panic("Local APIC Processor Priority register unimplemented.\n");
383 case APIC_ERROR_STATUS
:
384 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
386 case APIC_CURRENT_COUNT
:
388 if (apicTimerEvent
.scheduled()) {
389 // Compute how many m5 ticks happen per count.
390 uint64_t ticksPerCount
= clockPeriod() *
391 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
392 // Compute how many m5 ticks are left.
393 uint64_t val
= apicTimerEvent
.when() - curTick();
394 // Turn that into a count.
395 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
408 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
410 uint32_t newVal
= val
;
411 if (reg
>= APIC_IN_SERVICE(0) &&
412 reg
<= APIC_IN_SERVICE(15)) {
413 panic("Local APIC In-Service registers are unimplemented.\n");
415 if (reg
>= APIC_TRIGGER_MODE(0) &&
416 reg
<= APIC_TRIGGER_MODE(15)) {
417 panic("Local APIC Trigger Mode registers are unimplemented.\n");
419 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
420 reg
<= APIC_INTERRUPT_REQUEST(15)) {
421 panic("Local APIC Interrupt Request registers "
422 "are unimplemented.\n");
429 // The Local APIC Version register is read only.
431 case APIC_TASK_PRIORITY
:
434 case APIC_ARBITRATION_PRIORITY
:
435 panic("Local APIC Arbitration Priority register unimplemented.\n");
437 case APIC_PROCESSOR_PRIORITY
:
438 panic("Local APIC Processor Priority register unimplemented.\n");
441 // Remove the interrupt that just completed from the local apic state.
442 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
445 case APIC_LOGICAL_DESTINATION
:
446 newVal
= val
& 0xFF000000;
448 case APIC_DESTINATION_FORMAT
:
449 newVal
= val
| 0x0FFFFFFF;
451 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
452 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
453 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
455 warn("Focus processor checking not implemented.\n");
457 case APIC_ERROR_STATUS
:
459 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
460 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
463 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
469 case APIC_INTERRUPT_COMMAND_LOW
:
471 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
472 // Check if we're already sending an IPI.
473 if (low
.deliveryStatus
) {
478 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
479 TriggerIntMessage message
= 0;
480 message
.destination
= high
.destination
;
481 message
.vector
= low
.vector
;
482 message
.deliveryMode
= low
.deliveryMode
;
483 message
.destMode
= low
.destMode
;
484 message
.level
= low
.level
;
485 message
.trigger
= low
.trigger
;
486 std::list
<int> apics
;
487 int numContexts
= sys
->numContexts();
488 switch (low
.destShorthand
) {
490 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
491 panic("Lowest priority delivery mode "
492 "IPIs aren't implemented.\n");
494 if (message
.destMode
== 1) {
495 int dest
= message
.destination
;
496 hack_once("Assuming logical destinations are 1 << id.\n");
497 for (int i
= 0; i
< numContexts
; i
++) {
503 if (message
.destination
== 0xFF) {
504 for (int i
= 0; i
< numContexts
; i
++) {
505 if (i
== initialApicId
) {
506 requestInterrupt(message
.vector
,
507 message
.deliveryMode
, message
.trigger
);
513 if (message
.destination
== initialApicId
) {
514 requestInterrupt(message
.vector
,
515 message
.deliveryMode
, message
.trigger
);
517 apics
.push_back(message
.destination
);
524 requestInterrupt(message
.vector
,
525 message
.deliveryMode
, message
.trigger
);
528 requestInterrupt(message
.vector
,
529 message
.deliveryMode
, message
.trigger
);
533 for (int i
= 0; i
< numContexts
; i
++) {
534 if (i
!= initialApicId
) {
541 // Record that an IPI is being sent if one actually is.
543 low
.deliveryStatus
= 1;
544 pendingIPIs
+= apics
.size();
546 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
547 for (auto id
: apics
) {
548 PacketPtr pkt
= buildIntTriggerPacket(id
, message
);
549 intMasterPort
.sendMessage(pkt
, sys
->isTimingMode(),
550 [this](PacketPtr pkt
) { completeIPI(pkt
); });
552 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
556 case APIC_LVT_THERMAL_SENSOR
:
557 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
562 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
563 newVal
= (val
& ~readOnlyMask
) |
564 (regs
[reg
] & readOnlyMask
);
567 case APIC_INITIAL_COUNT
:
569 newVal
= bits(val
, 31, 0);
570 // Compute how many timer ticks we're being programmed for.
571 uint64_t newCount
= newVal
*
572 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
573 // Schedule on the edge of the next tick plus the new count.
574 Tick offset
= curTick() % clockPeriod();
576 reschedule(apicTimerEvent
,
577 curTick() + (newCount
+ 1) *
578 clockPeriod() - offset
, true);
581 reschedule(apicTimerEvent
,
582 curTick() + newCount
*
583 clockPeriod(), true);
587 case APIC_CURRENT_COUNT
:
588 //Local APIC Current Count register is read only.
590 case APIC_DIVIDE_CONFIGURATION
:
601 X86ISA::Interrupts::Interrupts(Params
* p
)
603 apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
604 pendingSmi(false), smiVector(0),
605 pendingNmi(false), nmiVector(0),
606 pendingExtInt(false), extIntVector(0),
607 pendingInit(false), initVector(0),
608 pendingStartup(false), startupVector(0),
609 startedUp(false), pendingUnmaskableInt(false),
610 pendingIPIs(0), cpu(NULL
),
611 intSlavePort(name() + ".int_slave", this, this),
612 intMasterPort(name() + ".int_master", this, this, p
->int_latency
),
613 pioDelay(p
->pio_latency
)
615 memset(regs
, 0, sizeof(regs
));
616 //Set the local apic DFR to the flat model.
617 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
624 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
626 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
627 if (pendingUnmaskableInt
) {
628 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
633 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
636 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
637 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
638 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
646 X86ISA::Interrupts::checkInterruptsRaw() const
648 return pendingUnmaskableInt
|| pendingExtInt
||
649 (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
650 bits(regs
[APIC_TASK_PRIORITY
], 7, 4));
654 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
656 assert(checkInterrupts(tc
));
657 // These are all probably fairly uncommon, so we'll make them easier to
659 if (pendingUnmaskableInt
) {
661 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
662 return std::make_shared
<SystemManagementInterrupt
>();
663 } else if (pendingNmi
) {
664 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
665 return std::make_shared
<NonMaskableInterrupt
>(nmiVector
);
666 } else if (pendingInit
) {
667 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
668 return std::make_shared
<InitInterrupt
>(initVector
);
669 } else if (pendingStartup
) {
670 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
671 return std::make_shared
<StartupInterrupt
>(startupVector
);
673 panic("pendingUnmaskableInt set, but no unmaskable "
674 "ints were pending.\n");
677 } else if (pendingExtInt
) {
678 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
679 return std::make_shared
<ExternalInterrupt
>(extIntVector
);
681 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
682 // The only thing left are fixed and lowest priority interrupts.
683 return std::make_shared
<ExternalInterrupt
>(IRRV
);
688 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
690 assert(checkInterrupts(tc
));
691 if (pendingUnmaskableInt
) {
693 DPRINTF(LocalApic
, "SMI sent to core.\n");
695 } else if (pendingNmi
) {
696 DPRINTF(LocalApic
, "NMI sent to core.\n");
698 } else if (pendingInit
) {
699 DPRINTF(LocalApic
, "Init sent to core.\n");
702 } else if (pendingStartup
) {
703 DPRINTF(LocalApic
, "SIPI sent to core.\n");
704 pendingStartup
= false;
707 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
708 pendingUnmaskableInt
= false;
709 } else if (pendingExtInt
) {
710 pendingExtInt
= false;
712 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
713 // Mark the interrupt as "in service".
715 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
716 // Clear it out of the IRR.
717 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
723 X86ISA::Interrupts::serialize(CheckpointOut
&cp
) const
725 SERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
726 SERIALIZE_SCALAR(pendingSmi
);
727 SERIALIZE_SCALAR(smiVector
);
728 SERIALIZE_SCALAR(pendingNmi
);
729 SERIALIZE_SCALAR(nmiVector
);
730 SERIALIZE_SCALAR(pendingExtInt
);
731 SERIALIZE_SCALAR(extIntVector
);
732 SERIALIZE_SCALAR(pendingInit
);
733 SERIALIZE_SCALAR(initVector
);
734 SERIALIZE_SCALAR(pendingStartup
);
735 SERIALIZE_SCALAR(startupVector
);
736 SERIALIZE_SCALAR(startedUp
);
737 SERIALIZE_SCALAR(pendingUnmaskableInt
);
738 SERIALIZE_SCALAR(pendingIPIs
);
739 SERIALIZE_SCALAR(IRRV
);
740 SERIALIZE_SCALAR(ISRV
);
741 bool apicTimerEventScheduled
= apicTimerEvent
.scheduled();
742 SERIALIZE_SCALAR(apicTimerEventScheduled
);
743 Tick apicTimerEventTick
= apicTimerEvent
.when();
744 SERIALIZE_SCALAR(apicTimerEventTick
);
748 X86ISA::Interrupts::unserialize(CheckpointIn
&cp
)
750 UNSERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
751 UNSERIALIZE_SCALAR(pendingSmi
);
752 UNSERIALIZE_SCALAR(smiVector
);
753 UNSERIALIZE_SCALAR(pendingNmi
);
754 UNSERIALIZE_SCALAR(nmiVector
);
755 UNSERIALIZE_SCALAR(pendingExtInt
);
756 UNSERIALIZE_SCALAR(extIntVector
);
757 UNSERIALIZE_SCALAR(pendingInit
);
758 UNSERIALIZE_SCALAR(initVector
);
759 UNSERIALIZE_SCALAR(pendingStartup
);
760 UNSERIALIZE_SCALAR(startupVector
);
761 UNSERIALIZE_SCALAR(startedUp
);
762 UNSERIALIZE_SCALAR(pendingUnmaskableInt
);
763 UNSERIALIZE_SCALAR(pendingIPIs
);
764 UNSERIALIZE_SCALAR(IRRV
);
765 UNSERIALIZE_SCALAR(ISRV
);
766 bool apicTimerEventScheduled
;
767 UNSERIALIZE_SCALAR(apicTimerEventScheduled
);
768 if (apicTimerEventScheduled
) {
769 Tick apicTimerEventTick
;
770 UNSERIALIZE_SCALAR(apicTimerEventTick
);
771 if (apicTimerEvent
.scheduled()) {
772 reschedule(apicTimerEvent
, apicTimerEventTick
, true);
774 schedule(apicTimerEvent
, apicTimerEventTick
);
780 X86LocalApicParams::create()
782 return new X86ISA::Interrupts(this);
786 X86ISA::Interrupts::processApicTimerEvent() {
787 if (triggerTimerInterrupt())
788 setReg(APIC_INITIAL_COUNT
, readReg(APIC_INITIAL_COUNT
));