2 * Copyright (c) 2008 The Hewlett-Packard Development Company
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/x86/regs/apic.hh"
41 #include "arch/x86/interrupts.hh"
42 #include "arch/x86/intmessage.hh"
43 #include "cpu/base.hh"
44 #include "dev/x86/i82094aa.hh"
45 #include "dev/x86/pc.hh"
46 #include "dev/x86/south_bridge.hh"
47 #include "mem/packet_access.hh"
48 #include "sim/system.hh"
51 divideFromConf(uint32_t conf
)
53 // This figures out what division we want from the division configuration
54 // register in the local APIC. The encoding is a little odd but it can
55 // be deciphered fairly easily.
56 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
57 shift
= (shift
+ 1) % 8;
65 decodeAddr(Addr paddr
)
75 regNum
= APIC_VERSION
;
78 regNum
= APIC_TASK_PRIORITY
;
81 regNum
= APIC_ARBITRATION_PRIORITY
;
84 regNum
= APIC_PROCESSOR_PRIORITY
;
90 regNum
= APIC_LOGICAL_DESTINATION
;
93 regNum
= APIC_DESTINATION_FORMAT
;
96 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
114 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x8);
132 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x8);
150 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x8);
153 regNum
= APIC_ERROR_STATUS
;
156 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
159 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
162 regNum
= APIC_LVT_TIMER
;
165 regNum
= APIC_LVT_THERMAL_SENSOR
;
168 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
171 regNum
= APIC_LVT_LINT0
;
174 regNum
= APIC_LVT_LINT1
;
177 regNum
= APIC_LVT_ERROR
;
180 regNum
= APIC_INITIAL_COUNT
;
183 regNum
= APIC_CURRENT_COUNT
;
186 regNum
= APIC_DIVIDE_CONFIGURATION
;
189 // A reserved register field.
190 panic("Accessed reserved register field %#x.\n", paddr
);
198 X86ISA::Interrupts::read(PacketPtr pkt
)
200 Addr offset
= pkt
->getAddr() - pioAddr
;
201 //Make sure we're at least only accessing one register.
202 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
203 panic("Accessed more than one register at a time in the APIC!\n");
204 ApicRegIndex reg
= decodeAddr(offset
);
205 uint32_t val
= htog(readReg(reg
));
207 "Reading Local APIC register %d at offset %#x as %#x.\n",
209 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
210 pkt
->makeAtomicResponse();
215 X86ISA::Interrupts::write(PacketPtr pkt
)
217 Addr offset
= pkt
->getAddr() - pioAddr
;
218 //Make sure we're at least only accessing one register.
219 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
220 panic("Accessed more than one register at a time in the APIC!\n");
221 ApicRegIndex reg
= decodeAddr(offset
);
222 uint32_t val
= regs
[reg
];
223 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
225 "Writing Local APIC register %d at offset %#x as %#x.\n",
226 reg
, offset
, gtoh(val
));
227 setReg(reg
, gtoh(val
));
228 pkt
->makeAtomicResponse();
232 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
233 uint8_t deliveryMode
, bool level
)
236 * Fixed and lowest-priority delivery mode interrupts are handled
237 * using the IRR/ISR registers, checking against the TPR, etc.
238 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
240 if (deliveryMode
== DeliveryMode::Fixed
||
241 deliveryMode
== DeliveryMode::LowestPriority
) {
242 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
243 DeliveryMode::names
[deliveryMode
]);
244 // Queue up the interrupt in the IRR.
247 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
248 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
250 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
252 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
255 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
256 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
257 DeliveryMode::names
[deliveryMode
]);
258 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
259 pendingUnmaskableInt
= pendingSmi
= true;
261 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
262 pendingUnmaskableInt
= pendingNmi
= true;
264 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
265 pendingExtInt
= true;
266 extIntVector
= vector
;
267 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
268 pendingUnmaskableInt
= pendingInit
= true;
270 } else if (deliveryMode
== DeliveryMode::SIPI
&&
271 !pendingStartup
&& !startedUp
) {
272 pendingUnmaskableInt
= pendingStartup
= true;
273 startupVector
= vector
;
281 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
284 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
285 panic("Local APICs can't be moved between CPUs"
286 " with different IDs.\n");
289 initialApicId
= cpu
->cpuId();
290 regs
[APIC_ID
] = (initialApicId
<< 24);
295 X86ISA::Interrupts::init()
298 // The local apic must register its address ranges on both its pio port
299 // via the basicpiodevice(piodevice) init() function and its int port
300 // that it inherited from IntDev. Note IntDev is not a SimObject itself.
302 BasicPioDevice::init();
305 Pc
* pc
= dynamic_cast<Pc
*>(platform
);
307 pc
->southBridge
->ioApic
->registerLocalApic(initialApicId
, this);
312 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
314 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
315 assert(pkt
->cmd
== MemCmd::MessageReq
);
320 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
322 "Got Trigger Interrupt message with vector %#x.\n",
325 requestInterrupt(message
.vector
,
326 message
.deliveryMode
, message
.trigger
);
330 panic("Local apic got unknown interrupt message at offset %#x.\n",
334 pkt
->makeAtomicResponse();
340 X86ISA::Interrupts::recvResponse(PacketPtr pkt
)
342 assert(!pkt
->isError());
343 assert(pkt
->cmd
== MemCmd::MessageResp
);
344 if (--pendingIPIs
== 0) {
345 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
346 // Record that the ICR is now idle.
347 low
.deliveryStatus
= 0;
348 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
350 DPRINTF(LocalApic
, "ICR is now idle.\n");
356 X86ISA::Interrupts::addressRanges(AddrRangeList
&range_list
)
359 Range
<Addr
> range
= RangeEx(x86LocalAPICAddress(initialApicId
, 0),
360 x86LocalAPICAddress(initialApicId
, 0) +
362 range_list
.push_back(range
);
363 pioAddr
= range
.start
;
368 X86ISA::Interrupts::getIntAddrRange(AddrRangeList
&range_list
)
371 range_list
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
372 x86InterruptAddress(initialApicId
, 0) +
373 PhysAddrAPICRangeSize
));
378 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
380 if (reg
>= APIC_TRIGGER_MODE(0) &&
381 reg
<= APIC_TRIGGER_MODE(15)) {
382 panic("Local APIC Trigger Mode registers are unimplemented.\n");
385 case APIC_ARBITRATION_PRIORITY
:
386 panic("Local APIC Arbitration Priority register unimplemented.\n");
388 case APIC_PROCESSOR_PRIORITY
:
389 panic("Local APIC Processor Priority register unimplemented.\n");
391 case APIC_ERROR_STATUS
:
392 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
394 case APIC_CURRENT_COUNT
:
396 if (apicTimerEvent
.scheduled()) {
398 // Compute how many m5 ticks happen per count.
399 uint64_t ticksPerCount
= clock
*
400 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
401 // Compute how many m5 ticks are left.
402 uint64_t val
= apicTimerEvent
.when() - curTick();
403 // Turn that into a count.
404 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
417 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
419 uint32_t newVal
= val
;
420 if (reg
>= APIC_IN_SERVICE(0) &&
421 reg
<= APIC_IN_SERVICE(15)) {
422 panic("Local APIC In-Service registers are unimplemented.\n");
424 if (reg
>= APIC_TRIGGER_MODE(0) &&
425 reg
<= APIC_TRIGGER_MODE(15)) {
426 panic("Local APIC Trigger Mode registers are unimplemented.\n");
428 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
429 reg
<= APIC_INTERRUPT_REQUEST(15)) {
430 panic("Local APIC Interrupt Request registers "
431 "are unimplemented.\n");
438 // The Local APIC Version register is read only.
440 case APIC_TASK_PRIORITY
:
443 case APIC_ARBITRATION_PRIORITY
:
444 panic("Local APIC Arbitration Priority register unimplemented.\n");
446 case APIC_PROCESSOR_PRIORITY
:
447 panic("Local APIC Processor Priority register unimplemented.\n");
450 // Remove the interrupt that just completed from the local apic state.
451 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
454 case APIC_LOGICAL_DESTINATION
:
455 newVal
= val
& 0xFF000000;
457 case APIC_DESTINATION_FORMAT
:
458 newVal
= val
| 0x0FFFFFFF;
460 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
461 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
462 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
464 warn("Focus processor checking not implemented.\n");
466 case APIC_ERROR_STATUS
:
468 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
469 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
472 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
478 case APIC_INTERRUPT_COMMAND_LOW
:
480 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
481 // Check if we're already sending an IPI.
482 if (low
.deliveryStatus
) {
487 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
488 // Record that an IPI is being sent.
489 low
.deliveryStatus
= 1;
490 TriggerIntMessage message
= 0;
491 message
.destination
= high
.destination
;
492 message
.vector
= low
.vector
;
493 message
.deliveryMode
= low
.deliveryMode
;
494 message
.destMode
= low
.destMode
;
495 message
.level
= low
.level
;
496 message
.trigger
= low
.trigger
;
497 bool timing
= sys
->getMemoryMode() == Enums::timing
;
498 // Be careful no updates of the delivery status bit get lost.
499 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
501 int numContexts
= sys
->numContexts();
502 switch (low
.destShorthand
) {
504 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
505 panic("Lowest priority delivery mode "
506 "IPIs aren't implemented.\n");
508 if (message
.destMode
== 1) {
509 int dest
= message
.destination
;
510 hack_once("Assuming logical destinations are 1 << id.\n");
511 for (int i
= 0; i
< numContexts
; i
++) {
517 if (message
.destination
== 0xFF) {
518 for (int i
= 0; i
< numContexts
; i
++) {
519 if (i
== initialApicId
) {
520 requestInterrupt(message
.vector
,
521 message
.deliveryMode
, message
.trigger
);
527 if (message
.destination
== initialApicId
) {
528 requestInterrupt(message
.vector
,
529 message
.deliveryMode
, message
.trigger
);
531 apics
.push_back(message
.destination
);
538 requestInterrupt(message
.vector
,
539 message
.deliveryMode
, message
.trigger
);
542 requestInterrupt(message
.vector
,
543 message
.deliveryMode
, message
.trigger
);
547 for (int i
= 0; i
< numContexts
; i
++) {
548 if (i
!= initialApicId
) {
555 pendingIPIs
+= apics
.size();
556 intPort
->sendMessage(apics
, message
, timing
);
557 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
561 case APIC_LVT_THERMAL_SENSOR
:
562 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
567 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
568 newVal
= (val
& ~readOnlyMask
) |
569 (regs
[reg
] & readOnlyMask
);
572 case APIC_INITIAL_COUNT
:
575 newVal
= bits(val
, 31, 0);
576 // Compute how many timer ticks we're being programmed for.
577 uint64_t newCount
= newVal
*
578 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
579 // Schedule on the edge of the next tick plus the new count.
580 Tick offset
= curTick() % clock
;
582 reschedule(apicTimerEvent
,
583 curTick() + (newCount
+ 1) * clock
- offset
, true);
585 reschedule(apicTimerEvent
,
586 curTick() + newCount
* clock
, true);
590 case APIC_CURRENT_COUNT
:
591 //Local APIC Current Count register is read only.
593 case APIC_DIVIDE_CONFIGURATION
:
604 X86ISA::Interrupts::Interrupts(Params
* p
) :
605 BasicPioDevice(p
), IntDev(this, p
->int_latency
), latency(p
->pio_latency
),
607 apicTimerEvent(this),
608 pendingSmi(false), smiVector(0),
609 pendingNmi(false), nmiVector(0),
610 pendingExtInt(false), extIntVector(0),
611 pendingInit(false), initVector(0),
612 pendingStartup(false), startupVector(0),
613 startedUp(false), pendingUnmaskableInt(false),
614 pendingIPIs(0), cpu(NULL
)
617 memset(regs
, 0, sizeof(regs
));
618 //Set the local apic DFR to the flat model.
619 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
626 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
628 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
629 if (pendingUnmaskableInt
) {
630 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
635 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
638 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
639 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
640 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
648 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
650 assert(checkInterrupts(tc
));
651 // These are all probably fairly uncommon, so we'll make them easier to
653 if (pendingUnmaskableInt
) {
655 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
656 return new SystemManagementInterrupt();
657 } else if (pendingNmi
) {
658 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
659 return new NonMaskableInterrupt(nmiVector
);
660 } else if (pendingInit
) {
661 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
662 return new InitInterrupt(initVector
);
663 } else if (pendingStartup
) {
664 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
665 return new StartupInterrupt(startupVector
);
667 panic("pendingUnmaskableInt set, but no unmaskable "
668 "ints were pending.\n");
671 } else if (pendingExtInt
) {
672 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
673 return new ExternalInterrupt(extIntVector
);
675 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
676 // The only thing left are fixed and lowest priority interrupts.
677 return new ExternalInterrupt(IRRV
);
682 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
684 assert(checkInterrupts(tc
));
685 if (pendingUnmaskableInt
) {
687 DPRINTF(LocalApic
, "SMI sent to core.\n");
689 } else if (pendingNmi
) {
690 DPRINTF(LocalApic
, "NMI sent to core.\n");
692 } else if (pendingInit
) {
693 DPRINTF(LocalApic
, "Init sent to core.\n");
696 } else if (pendingStartup
) {
697 DPRINTF(LocalApic
, "SIPI sent to core.\n");
698 pendingStartup
= false;
701 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
702 pendingUnmaskableInt
= false;
703 } else if (pendingExtInt
) {
704 pendingExtInt
= false;
706 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
707 // Mark the interrupt as "in service".
709 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
710 // Clear it out of the IRR.
711 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
717 X86ISA::Interrupts::serialize(std::ostream
&os
)
719 SERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
720 SERIALIZE_SCALAR(clock
);
721 SERIALIZE_SCALAR(pendingSmi
);
722 SERIALIZE_SCALAR(smiVector
);
723 SERIALIZE_SCALAR(pendingNmi
);
724 SERIALIZE_SCALAR(nmiVector
);
725 SERIALIZE_SCALAR(pendingExtInt
);
726 SERIALIZE_SCALAR(extIntVector
);
727 SERIALIZE_SCALAR(pendingInit
);
728 SERIALIZE_SCALAR(initVector
);
729 SERIALIZE_SCALAR(pendingStartup
);
730 SERIALIZE_SCALAR(startupVector
);
731 SERIALIZE_SCALAR(startedUp
);
732 SERIALIZE_SCALAR(pendingUnmaskableInt
);
733 SERIALIZE_SCALAR(pendingIPIs
);
734 SERIALIZE_SCALAR(IRRV
);
735 SERIALIZE_SCALAR(ISRV
);
736 bool apicTimerEventScheduled
= apicTimerEvent
.scheduled();
737 SERIALIZE_SCALAR(apicTimerEventScheduled
);
738 Tick apicTimerEventTick
= apicTimerEvent
.when();
739 SERIALIZE_SCALAR(apicTimerEventTick
);
743 X86ISA::Interrupts::unserialize(Checkpoint
*cp
, const std::string
§ion
)
745 UNSERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
746 UNSERIALIZE_SCALAR(clock
);
747 UNSERIALIZE_SCALAR(pendingSmi
);
748 UNSERIALIZE_SCALAR(smiVector
);
749 UNSERIALIZE_SCALAR(pendingNmi
);
750 UNSERIALIZE_SCALAR(nmiVector
);
751 UNSERIALIZE_SCALAR(pendingExtInt
);
752 UNSERIALIZE_SCALAR(extIntVector
);
753 UNSERIALIZE_SCALAR(pendingInit
);
754 UNSERIALIZE_SCALAR(initVector
);
755 UNSERIALIZE_SCALAR(pendingStartup
);
756 UNSERIALIZE_SCALAR(startupVector
);
757 UNSERIALIZE_SCALAR(startedUp
);
758 UNSERIALIZE_SCALAR(pendingUnmaskableInt
);
759 UNSERIALIZE_SCALAR(pendingIPIs
);
760 UNSERIALIZE_SCALAR(IRRV
);
761 UNSERIALIZE_SCALAR(ISRV
);
762 bool apicTimerEventScheduled
;
763 UNSERIALIZE_SCALAR(apicTimerEventScheduled
);
764 if (apicTimerEventScheduled
) {
765 Tick apicTimerEventTick
;
766 UNSERIALIZE_SCALAR(apicTimerEventTick
);
767 if (apicTimerEvent
.scheduled()) {
768 reschedule(apicTimerEvent
, apicTimerEventTick
, true);
770 schedule(apicTimerEvent
, apicTimerEventTick
);
776 X86LocalApicParams::create()
778 return new X86ISA::Interrupts(this);