src/arch/x86/interrupts.cc

   1 /*
   2  * Copyright (c) 2012-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2008 The Hewlett-Packard Development Company
  15  * All rights reserved.
  16  *
  17  * The license below extends only to copyright in the software and shall
  18  * not be construed as granting a license to any other intellectual
  19  * property including but not limited to intellectual property relating
  20  * to a hardware implementation of the functionality of the software
  21  * licensed hereunder.  You may use the software subject to the license
  22  * terms below provided that you ensure that this notice is replicated
  23  * unmodified and in its entirety in all distributions of the software,
  24  * modified or unmodified, in source code or in binary form.
  25  *
  26  * Redistribution and use in source and binary forms, with or without
  27  * modification, are permitted provided that the following conditions are
  28  * met: redistributions of source code must retain the above copyright
  29  * notice, this list of conditions and the following disclaimer;
  30  * redistributions in binary form must reproduce the above copyright
  31  * notice, this list of conditions and the following disclaimer in the
  32  * documentation and/or other materials provided with the distribution;
  33  * neither the name of the copyright holders nor the names of its
  34  * contributors may be used to endorse or promote products derived from
  35  * this software without specific prior written permission.
  36  *
  37  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  38  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  39  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  40  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  41  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  42  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  43  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  44  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  45  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  46  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48  *
  49  * Authors: Gabe Black
  50  */
  51
  52 #include "arch/x86/interrupts.hh"
  53
  54 #include <list>
  55 #include <memory>
  56
  57 #include "arch/x86/intmessage.hh"
  58 #include "arch/x86/regs/apic.hh"
  59 #include "cpu/base.hh"
  60 #include "debug/LocalApic.hh"
  61 #include "dev/x86/i82094aa.hh"
  62 #include "dev/x86/pc.hh"
  63 #include "dev/x86/south_bridge.hh"
  64 #include "mem/packet_access.hh"
  65 #include "sim/full_system.hh"
  66 #include "sim/system.hh"
  67
  68 int
  69 divideFromConf(uint32_t conf)
  70 {
  71     // This figures out what division we want from the division configuration
  72     // register in the local APIC. The encoding is a little odd but it can
  73     // be deciphered fairly easily.
  74     int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
  75     shift = (shift + 1) % 8;
  76     return 1 << shift;
  77 }
  78
  79 namespace X86ISA
  80 {
  81
  82 ApicRegIndex
  83 decodeAddr(Addr paddr)
  84 {
  85     ApicRegIndex regNum;
  86     paddr &= ~mask(3);
  87     switch (paddr)
  88     {
  89       case 0x20:
  90         regNum = APIC_ID;
  91         break;
  92       case 0x30:
  93         regNum = APIC_VERSION;
  94         break;
  95       case 0x80:
  96         regNum = APIC_TASK_PRIORITY;
  97         break;
  98       case 0x90:
  99         regNum = APIC_ARBITRATION_PRIORITY;
 100         break;
 101       case 0xA0:
 102         regNum = APIC_PROCESSOR_PRIORITY;
 103         break;
 104       case 0xB0:
 105         regNum = APIC_EOI;
 106         break;
 107       case 0xD0:
 108         regNum = APIC_LOGICAL_DESTINATION;
 109         break;
 110       case 0xE0:
 111         regNum = APIC_DESTINATION_FORMAT;
 112         break;
 113       case 0xF0:
 114         regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
 115         break;
 116       case 0x100:
 117       case 0x110:
 118       case 0x120:
 119       case 0x130:
 120       case 0x140:
 121       case 0x150:
 122       case 0x160:
 123       case 0x170:
 124         regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x10);
 125         break;
 126       case 0x180:
 127       case 0x190:
 128       case 0x1A0:
 129       case 0x1B0:
 130       case 0x1C0:
 131       case 0x1D0:
 132       case 0x1E0:
 133       case 0x1F0:
 134         regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x10);
 135         break;
 136       case 0x200:
 137       case 0x210:
 138       case 0x220:
 139       case 0x230:
 140       case 0x240:
 141       case 0x250:
 142       case 0x260:
 143       case 0x270:
 144         regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x10);
 145         break;
 146       case 0x280:
 147         regNum = APIC_ERROR_STATUS;
 148         break;
 149       case 0x300:
 150         regNum = APIC_INTERRUPT_COMMAND_LOW;
 151         break;
 152       case 0x310:
 153         regNum = APIC_INTERRUPT_COMMAND_HIGH;
 154         break;
 155       case 0x320:
 156         regNum = APIC_LVT_TIMER;
 157         break;
 158       case 0x330:
 159         regNum = APIC_LVT_THERMAL_SENSOR;
 160         break;
 161       case 0x340:
 162         regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
 163         break;
 164       case 0x350:
 165         regNum = APIC_LVT_LINT0;
 166         break;
 167       case 0x360:
 168         regNum = APIC_LVT_LINT1;
 169         break;
 170       case 0x370:
 171         regNum = APIC_LVT_ERROR;
 172         break;
 173       case 0x380:
 174         regNum = APIC_INITIAL_COUNT;
 175         break;
 176       case 0x390:
 177         regNum = APIC_CURRENT_COUNT;
 178         break;
 179       case 0x3E0:
 180         regNum = APIC_DIVIDE_CONFIGURATION;
 181         break;
 182       default:
 183         // A reserved register field.
 184         panic("Accessed reserved register field %#x.\n", paddr);
 185         break;
 186     }
 187     return regNum;
 188 }
 189 }
 190
 191 Tick
 192 X86ISA::Interrupts::read(PacketPtr pkt)
 193 {
 194     Addr offset = pkt->getAddr() - pioAddr;
 195     // Make sure we're at least only accessing one register.
 196     if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
 197         panic("Accessed more than one register at a time in the APIC!\n");
 198     ApicRegIndex reg = decodeAddr(offset);
 199     uint32_t val = htog(readReg(reg));
 200     DPRINTF(LocalApic,
 201             "Reading Local APIC register %d at offset %#x as %#x.\n",
 202             reg, offset, val);
 203     pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
 204     pkt->makeAtomicResponse();
 205     return pioDelay;
 206 }
 207
 208 Tick
 209 X86ISA::Interrupts::write(PacketPtr pkt)
 210 {
 211     Addr offset = pkt->getAddr() - pioAddr;
 212     // Make sure we're at least only accessing one register.
 213     if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
 214         panic("Accessed more than one register at a time in the APIC!\n");
 215     ApicRegIndex reg = decodeAddr(offset);
 216     uint32_t val = regs[reg];
 217     pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
 218     DPRINTF(LocalApic,
 219             "Writing Local APIC register %d at offset %#x as %#x.\n",
 220             reg, offset, gtoh(val));
 221     setReg(reg, gtoh(val));
 222     pkt->makeAtomicResponse();
 223     return pioDelay;
 224 }
 225 void
 226 X86ISA::Interrupts::requestInterrupt(uint8_t vector,
 227         uint8_t deliveryMode, bool level)
 228 {
 229     /*
 230      * Fixed and lowest-priority delivery mode interrupts are handled
 231      * using the IRR/ISR registers, checking against the TPR, etc.
 232      * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
 233      */
 234     if (deliveryMode == DeliveryMode::Fixed ||
 235             deliveryMode == DeliveryMode::LowestPriority) {
 236         DPRINTF(LocalApic, "Interrupt is an %s.\n",
 237                 DeliveryMode::names[deliveryMode]);
 238         // Queue up the interrupt in the IRR.
 239         if (vector > IRRV)
 240             IRRV = vector;
 241         if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
 242             setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
 243             if (level) {
 244                 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
 245             } else {
 246                 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
 247             }
 248         }
 249     } else if (!DeliveryMode::isReserved(deliveryMode)) {
 250         DPRINTF(LocalApic, "Interrupt is an %s.\n",
 251                 DeliveryMode::names[deliveryMode]);
 252         if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
 253             pendingUnmaskableInt = pendingSmi = true;
 254             smiVector = vector;
 255         } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
 256             pendingUnmaskableInt = pendingNmi = true;
 257             nmiVector = vector;
 258         } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
 259             pendingExtInt = true;
 260             extIntVector = vector;
 261         } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
 262             pendingUnmaskableInt = pendingInit = true;
 263             initVector = vector;
 264         } else if (deliveryMode == DeliveryMode::SIPI &&
 265                 !pendingStartup && !startedUp) {
 266             pendingUnmaskableInt = pendingStartup = true;
 267             startupVector = vector;
 268         }
 269     }
 270     if (FullSystem)
 271         cpu->wakeup(0);
 272 }
 273
 274
 275 void
 276 X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
 277 {
 278     assert(newCPU);
 279     if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
 280         panic("Local APICs can't be moved between CPUs"
 281                 " with different IDs.\n");
 282     }
 283     cpu = newCPU;
 284     initialApicId = cpu->cpuId();
 285     regs[APIC_ID] = (initialApicId << 24);
 286     pioAddr = x86LocalAPICAddress(initialApicId, 0);
 287 }
 288
 289
 290 void
 291 X86ISA::Interrupts::init()
 292 {
 293     //
 294     // The local apic must register its address ranges on its pio
 295     // port via the basicpiodevice(piodevice) init() function.
 296     PioDevice::init();
 297
 298     // The slave port has a range, so inform the connected master.
 299     intSlavePort.sendRangeChange();
 300     // If the master port isn't connected, we can't send interrupts anywhere.
 301     panic_if(!intMasterPort.isConnected(),
 302             "Int port not connected to anything!");
 303 }
 304
 305
 306 Tick
 307 X86ISA::Interrupts::recvMessage(PacketPtr pkt)
 308 {
 309     Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
 310     assert(pkt->cmd == MemCmd::WriteReq);
 311     switch(offset)
 312     {
 313       case 0:
 314         {
 315             TriggerIntMessage message = pkt->getRaw<TriggerIntMessage>();
 316             DPRINTF(LocalApic,
 317                     "Got Trigger Interrupt message with vector %#x.\n",
 318                     message.vector);
 319
 320             requestInterrupt(message.vector,
 321                     message.deliveryMode, message.trigger);
 322         }
 323         break;
 324       default:
 325         panic("Local apic got unknown interrupt message at offset %#x.\n",
 326                 offset);
 327         break;
 328     }
 329     pkt->makeAtomicResponse();
 330     return pioDelay;
 331 }
 332
 333
 334 bool
 335 X86ISA::Interrupts::recvResponse(PacketPtr pkt)
 336 {
 337     assert(!pkt->isError());
 338     assert(pkt->cmd == MemCmd::WriteResp);
 339     if (--pendingIPIs == 0) {
 340         InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
 341         // Record that the ICR is now idle.
 342         low.deliveryStatus = 0;
 343         regs[APIC_INTERRUPT_COMMAND_LOW] = low;
 344     }
 345     DPRINTF(LocalApic, "ICR is now idle.\n");
 346     return true;
 347 }
 348
 349
 350 AddrRangeList
 351 X86ISA::Interrupts::getAddrRanges() const
 352 {
 353     assert(cpu);
 354     AddrRangeList ranges;
 355     ranges.push_back(RangeSize(pioAddr, PageBytes));
 356     return ranges;
 357 }
 358
 359
 360 AddrRangeList
 361 X86ISA::Interrupts::getIntAddrRange() const
 362 {
 363     AddrRangeList ranges;
 364     ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
 365                              x86InterruptAddress(initialApicId, 0) +
 366                              PhysAddrAPICRangeSize));
 367     return ranges;
 368 }
 369
 370
 371 uint32_t
 372 X86ISA::Interrupts::readReg(ApicRegIndex reg)
 373 {
 374     if (reg >= APIC_TRIGGER_MODE(0) &&
 375             reg <= APIC_TRIGGER_MODE(15)) {
 376         panic("Local APIC Trigger Mode registers are unimplemented.\n");
 377     }
 378     switch (reg) {
 379       case APIC_ARBITRATION_PRIORITY:
 380         panic("Local APIC Arbitration Priority register unimplemented.\n");
 381         break;
 382       case APIC_PROCESSOR_PRIORITY:
 383         panic("Local APIC Processor Priority register unimplemented.\n");
 384         break;
 385       case APIC_ERROR_STATUS:
 386         regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
 387         break;
 388       case APIC_CURRENT_COUNT:
 389         {
 390             if (apicTimerEvent.scheduled()) {
 391                 // Compute how many m5 ticks happen per count.
 392                 uint64_t ticksPerCount = clockPeriod() *
 393                     divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
 394                 // Compute how many m5 ticks are left.
 395                 uint64_t val = apicTimerEvent.when() - curTick();
 396                 // Turn that into a count.
 397                 val = (val + ticksPerCount - 1) / ticksPerCount;
 398                 return val;
 399             } else {
 400                 return 0;
 401             }
 402         }
 403       default:
 404         break;
 405     }
 406     return regs[reg];
 407 }
 408
 409 void
 410 X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
 411 {
 412     uint32_t newVal = val;
 413     if (reg >= APIC_IN_SERVICE(0) &&
 414             reg <= APIC_IN_SERVICE(15)) {
 415         panic("Local APIC In-Service registers are unimplemented.\n");
 416     }
 417     if (reg >= APIC_TRIGGER_MODE(0) &&
 418             reg <= APIC_TRIGGER_MODE(15)) {
 419         panic("Local APIC Trigger Mode registers are unimplemented.\n");
 420     }
 421     if (reg >= APIC_INTERRUPT_REQUEST(0) &&
 422             reg <= APIC_INTERRUPT_REQUEST(15)) {
 423         panic("Local APIC Interrupt Request registers "
 424                 "are unimplemented.\n");
 425     }
 426     switch (reg) {
 427       case APIC_ID:
 428         newVal = val & 0xFF;
 429         break;
 430       case APIC_VERSION:
 431         // The Local APIC Version register is read only.
 432         return;
 433       case APIC_TASK_PRIORITY:
 434         newVal = val & 0xFF;
 435         break;
 436       case APIC_ARBITRATION_PRIORITY:
 437         panic("Local APIC Arbitration Priority register unimplemented.\n");
 438         break;
 439       case APIC_PROCESSOR_PRIORITY:
 440         panic("Local APIC Processor Priority register unimplemented.\n");
 441         break;
 442       case APIC_EOI:
 443         // Remove the interrupt that just completed from the local apic state.
 444         clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
 445         updateISRV();
 446         return;
 447       case APIC_LOGICAL_DESTINATION:
 448         newVal = val & 0xFF000000;
 449         break;
 450       case APIC_DESTINATION_FORMAT:
 451         newVal = val | 0x0FFFFFFF;
 452         break;
 453       case APIC_SPURIOUS_INTERRUPT_VECTOR:
 454         regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
 455         regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
 456         if (val & (1 << 9))
 457             warn("Focus processor checking not implemented.\n");
 458         break;
 459       case APIC_ERROR_STATUS:
 460         {
 461             if (regs[APIC_INTERNAL_STATE] & 0x1) {
 462                 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
 463                 newVal = 0;
 464             } else {
 465                 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
 466                 return;
 467             }
 468
 469         }
 470         break;
 471       case APIC_INTERRUPT_COMMAND_LOW:
 472         {
 473             InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
 474             // Check if we're already sending an IPI.
 475             if (low.deliveryStatus) {
 476                 newVal = low;
 477                 break;
 478             }
 479             low = val;
 480             InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
 481             TriggerIntMessage message = 0;
 482             message.destination = high.destination;
 483             message.vector = low.vector;
 484             message.deliveryMode = low.deliveryMode;
 485             message.destMode = low.destMode;
 486             message.level = low.level;
 487             message.trigger = low.trigger;
 488             std::list<int> apics;
 489             int numContexts = sys->numContexts();
 490             switch (low.destShorthand) {
 491               case 0:
 492                 if (message.deliveryMode == DeliveryMode::LowestPriority) {
 493                     panic("Lowest priority delivery mode "
 494                             "IPIs aren't implemented.\n");
 495                 }
 496                 if (message.destMode == 1) {
 497                     int dest = message.destination;
 498                     hack_once("Assuming logical destinations are 1 << id.\n");
 499                     for (int i = 0; i < numContexts; i++) {
 500                         if (dest & 0x1)
 501                             apics.push_back(i);
 502                         dest = dest >> 1;
 503                     }
 504                 } else {
 505                     if (message.destination == 0xFF) {
 506                         for (int i = 0; i < numContexts; i++) {
 507                             if (i == initialApicId) {
 508                                 requestInterrupt(message.vector,
 509                                         message.deliveryMode, message.trigger);
 510                             } else {
 511                                 apics.push_back(i);
 512                             }
 513                         }
 514                     } else {
 515                         if (message.destination == initialApicId) {
 516                             requestInterrupt(message.vector,
 517                                     message.deliveryMode, message.trigger);
 518                         } else {
 519                             apics.push_back(message.destination);
 520                         }
 521                     }
 522                 }
 523                 break;
 524               case 1:
 525                 newVal = val;
 526                 requestInterrupt(message.vector,
 527                         message.deliveryMode, message.trigger);
 528                 break;
 529               case 2:
 530                 requestInterrupt(message.vector,
 531                         message.deliveryMode, message.trigger);
 532                 // Fall through
 533               case 3:
 534                 {
 535                     for (int i = 0; i < numContexts; i++) {
 536                         if (i != initialApicId) {
 537                             apics.push_back(i);
 538                         }
 539                     }
 540                 }
 541                 break;
 542             }
 543             // Record that an IPI is being sent if one actually is.
 544             if (apics.size()) {
 545                 low.deliveryStatus = 1;
 546                 pendingIPIs += apics.size();
 547             }
 548             regs[APIC_INTERRUPT_COMMAND_LOW] = low;
 549             for (auto id: apics) {
 550                 PacketPtr pkt = buildIntTriggerPacket(id, message);
 551                 intMasterPort.sendMessage(pkt, sys->isTimingMode());
 552             }
 553             newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
 554         }
 555         break;
 556       case APIC_LVT_TIMER:
 557       case APIC_LVT_THERMAL_SENSOR:
 558       case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
 559       case APIC_LVT_LINT0:
 560       case APIC_LVT_LINT1:
 561       case APIC_LVT_ERROR:
 562         {
 563             uint64_t readOnlyMask = (1 << 12) | (1 << 14);
 564             newVal = (val & ~readOnlyMask) |
 565                      (regs[reg] & readOnlyMask);
 566         }
 567         break;
 568       case APIC_INITIAL_COUNT:
 569         {
 570             newVal = bits(val, 31, 0);
 571             // Compute how many timer ticks we're being programmed for.
 572             uint64_t newCount = newVal *
 573                 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
 574             // Schedule on the edge of the next tick plus the new count.
 575             Tick offset = curTick() % clockPeriod();
 576             if (offset) {
 577                 reschedule(apicTimerEvent,
 578                            curTick() + (newCount + 1) *
 579                            clockPeriod() - offset, true);
 580             } else {
 581                 if (newCount)
 582                     reschedule(apicTimerEvent,
 583                                curTick() + newCount *
 584                                clockPeriod(), true);
 585             }
 586         }
 587         break;
 588       case APIC_CURRENT_COUNT:
 589         //Local APIC Current Count register is read only.
 590         return;
 591       case APIC_DIVIDE_CONFIGURATION:
 592         newVal = val & 0xB;
 593         break;
 594       default:
 595         break;
 596     }
 597     regs[reg] = newVal;
 598     return;
 599 }
 600
 601
 602 X86ISA::Interrupts::Interrupts(Params * p)
 603     : PioDevice(p),
 604       apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
 605       pendingSmi(false), smiVector(0),
 606       pendingNmi(false), nmiVector(0),
 607       pendingExtInt(false), extIntVector(0),
 608       pendingInit(false), initVector(0),
 609       pendingStartup(false), startupVector(0),
 610       startedUp(false), pendingUnmaskableInt(false),
 611       pendingIPIs(0), cpu(NULL),
 612       intSlavePort(name() + ".int_slave", this, this),
 613       intMasterPort(name() + ".int_master", this, this, p->int_latency),
 614       pioDelay(p->pio_latency)
 615 {
 616     memset(regs, 0, sizeof(regs));
 617     //Set the local apic DFR to the flat model.
 618     regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
 619     ISRV = 0;
 620     IRRV = 0;
 621 }
 622
 623
 624 bool
 625 X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
 626 {
 627     RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
 628     if (pendingUnmaskableInt) {
 629         DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
 630         return true;
 631     }
 632     if (rflags.intf) {
 633         if (pendingExtInt) {
 634             DPRINTF(LocalApic, "Reported pending external interrupt.\n");
 635             return true;
 636         }
 637         if (IRRV > ISRV && bits(IRRV, 7, 4) >
 638                bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
 639             DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
 640             return true;
 641         }
 642     }
 643     return false;
 644 }
 645
 646 bool
 647 X86ISA::Interrupts::checkInterruptsRaw() const
 648 {
 649     return pendingUnmaskableInt || pendingExtInt ||
 650         (IRRV > ISRV && bits(IRRV, 7, 4) >
 651          bits(regs[APIC_TASK_PRIORITY], 7, 4));
 652 }
 653
 654 Fault
 655 X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
 656 {
 657     assert(checkInterrupts(tc));
 658     // These are all probably fairly uncommon, so we'll make them easier to
 659     // check for.
 660     if (pendingUnmaskableInt) {
 661         if (pendingSmi) {
 662             DPRINTF(LocalApic, "Generated SMI fault object.\n");
 663             return std::make_shared<SystemManagementInterrupt>();
 664         } else if (pendingNmi) {
 665             DPRINTF(LocalApic, "Generated NMI fault object.\n");
 666             return std::make_shared<NonMaskableInterrupt>(nmiVector);
 667         } else if (pendingInit) {
 668             DPRINTF(LocalApic, "Generated INIT fault object.\n");
 669             return std::make_shared<InitInterrupt>(initVector);
 670         } else if (pendingStartup) {
 671             DPRINTF(LocalApic, "Generating SIPI fault object.\n");
 672             return std::make_shared<StartupInterrupt>(startupVector);
 673         } else {
 674             panic("pendingUnmaskableInt set, but no unmaskable "
 675                     "ints were pending.\n");
 676             return NoFault;
 677         }
 678     } else if (pendingExtInt) {
 679         DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
 680         return std::make_shared<ExternalInterrupt>(extIntVector);
 681     } else {
 682         DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
 683         // The only thing left are fixed and lowest priority interrupts.
 684         return std::make_shared<ExternalInterrupt>(IRRV);
 685     }
 686 }
 687
 688 void
 689 X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
 690 {
 691     assert(checkInterrupts(tc));
 692     if (pendingUnmaskableInt) {
 693         if (pendingSmi) {
 694             DPRINTF(LocalApic, "SMI sent to core.\n");
 695             pendingSmi = false;
 696         } else if (pendingNmi) {
 697             DPRINTF(LocalApic, "NMI sent to core.\n");
 698             pendingNmi = false;
 699         } else if (pendingInit) {
 700             DPRINTF(LocalApic, "Init sent to core.\n");
 701             pendingInit = false;
 702             startedUp = false;
 703         } else if (pendingStartup) {
 704             DPRINTF(LocalApic, "SIPI sent to core.\n");
 705             pendingStartup = false;
 706             startedUp = true;
 707         }
 708         if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
 709             pendingUnmaskableInt = false;
 710     } else if (pendingExtInt) {
 711         pendingExtInt = false;
 712     } else {
 713         DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
 714         // Mark the interrupt as "in service".
 715         ISRV = IRRV;
 716         setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
 717         // Clear it out of the IRR.
 718         clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
 719         updateIRRV();
 720     }
 721 }
 722
 723 void
 724 X86ISA::Interrupts::serialize(CheckpointOut &cp) const
 725 {
 726     SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
 727     SERIALIZE_SCALAR(pendingSmi);
 728     SERIALIZE_SCALAR(smiVector);
 729     SERIALIZE_SCALAR(pendingNmi);
 730     SERIALIZE_SCALAR(nmiVector);
 731     SERIALIZE_SCALAR(pendingExtInt);
 732     SERIALIZE_SCALAR(extIntVector);
 733     SERIALIZE_SCALAR(pendingInit);
 734     SERIALIZE_SCALAR(initVector);
 735     SERIALIZE_SCALAR(pendingStartup);
 736     SERIALIZE_SCALAR(startupVector);
 737     SERIALIZE_SCALAR(startedUp);
 738     SERIALIZE_SCALAR(pendingUnmaskableInt);
 739     SERIALIZE_SCALAR(pendingIPIs);
 740     SERIALIZE_SCALAR(IRRV);
 741     SERIALIZE_SCALAR(ISRV);
 742     bool apicTimerEventScheduled = apicTimerEvent.scheduled();
 743     SERIALIZE_SCALAR(apicTimerEventScheduled);
 744     Tick apicTimerEventTick = apicTimerEvent.when();
 745     SERIALIZE_SCALAR(apicTimerEventTick);
 746 }
 747
 748 void
 749 X86ISA::Interrupts::unserialize(CheckpointIn &cp)
 750 {
 751     UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
 752     UNSERIALIZE_SCALAR(pendingSmi);
 753     UNSERIALIZE_SCALAR(smiVector);
 754     UNSERIALIZE_SCALAR(pendingNmi);
 755     UNSERIALIZE_SCALAR(nmiVector);
 756     UNSERIALIZE_SCALAR(pendingExtInt);
 757     UNSERIALIZE_SCALAR(extIntVector);
 758     UNSERIALIZE_SCALAR(pendingInit);
 759     UNSERIALIZE_SCALAR(initVector);
 760     UNSERIALIZE_SCALAR(pendingStartup);
 761     UNSERIALIZE_SCALAR(startupVector);
 762     UNSERIALIZE_SCALAR(startedUp);
 763     UNSERIALIZE_SCALAR(pendingUnmaskableInt);
 764     UNSERIALIZE_SCALAR(pendingIPIs);
 765     UNSERIALIZE_SCALAR(IRRV);
 766     UNSERIALIZE_SCALAR(ISRV);
 767     bool apicTimerEventScheduled;
 768     UNSERIALIZE_SCALAR(apicTimerEventScheduled);
 769     if (apicTimerEventScheduled) {
 770         Tick apicTimerEventTick;
 771         UNSERIALIZE_SCALAR(apicTimerEventTick);
 772         if (apicTimerEvent.scheduled()) {
 773             reschedule(apicTimerEvent, apicTimerEventTick, true);
 774         } else {
 775             schedule(apicTimerEvent, apicTimerEventTick);
 776         }
 777     }
 778 }
 779
 780 X86ISA::Interrupts *
 781 X86LocalApicParams::create()
 782 {
 783     return new X86ISA::Interrupts(this);
 784 }
 785
 786 void
 787 X86ISA::Interrupts::processApicTimerEvent() {
 788     if (triggerTimerInterrupt())
 789         setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT));
 790 }