2 * Copyright (c) 2012-2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
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52 #include "arch/x86/interrupts.hh"
56 #include "arch/x86/intmessage.hh"
57 #include "arch/x86/regs/apic.hh"
58 #include "cpu/base.hh"
59 #include "debug/LocalApic.hh"
60 #include "dev/x86/i82094aa.hh"
61 #include "dev/x86/pc.hh"
62 #include "dev/x86/south_bridge.hh"
63 #include "mem/packet_access.hh"
64 #include "sim/full_system.hh"
65 #include "sim/system.hh"
68 divideFromConf(uint32_t conf
)
70 // This figures out what division we want from the division configuration
71 // register in the local APIC. The encoding is a little odd but it can
72 // be deciphered fairly easily.
73 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
74 shift
= (shift
+ 1) % 8;
82 decodeAddr(Addr paddr
)
92 regNum
= APIC_VERSION
;
95 regNum
= APIC_TASK_PRIORITY
;
98 regNum
= APIC_ARBITRATION_PRIORITY
;
101 regNum
= APIC_PROCESSOR_PRIORITY
;
107 regNum
= APIC_LOGICAL_DESTINATION
;
110 regNum
= APIC_DESTINATION_FORMAT
;
113 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
123 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x10);
133 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x10);
143 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x10);
146 regNum
= APIC_ERROR_STATUS
;
149 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
152 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
155 regNum
= APIC_LVT_TIMER
;
158 regNum
= APIC_LVT_THERMAL_SENSOR
;
161 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
164 regNum
= APIC_LVT_LINT0
;
167 regNum
= APIC_LVT_LINT1
;
170 regNum
= APIC_LVT_ERROR
;
173 regNum
= APIC_INITIAL_COUNT
;
176 regNum
= APIC_CURRENT_COUNT
;
179 regNum
= APIC_DIVIDE_CONFIGURATION
;
182 // A reserved register field.
183 panic("Accessed reserved register field %#x.\n", paddr
);
191 X86ISA::Interrupts::read(PacketPtr pkt
)
193 Addr offset
= pkt
->getAddr() - pioAddr
;
194 //Make sure we're at least only accessing one register.
195 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
196 panic("Accessed more than one register at a time in the APIC!\n");
197 ApicRegIndex reg
= decodeAddr(offset
);
198 uint32_t val
= htog(readReg(reg
));
200 "Reading Local APIC register %d at offset %#x as %#x.\n",
202 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
203 pkt
->makeAtomicResponse();
208 X86ISA::Interrupts::write(PacketPtr pkt
)
210 Addr offset
= pkt
->getAddr() - pioAddr
;
211 //Make sure we're at least only accessing one register.
212 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
213 panic("Accessed more than one register at a time in the APIC!\n");
214 ApicRegIndex reg
= decodeAddr(offset
);
215 uint32_t val
= regs
[reg
];
216 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
218 "Writing Local APIC register %d at offset %#x as %#x.\n",
219 reg
, offset
, gtoh(val
));
220 setReg(reg
, gtoh(val
));
221 pkt
->makeAtomicResponse();
225 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
226 uint8_t deliveryMode
, bool level
)
229 * Fixed and lowest-priority delivery mode interrupts are handled
230 * using the IRR/ISR registers, checking against the TPR, etc.
231 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
233 if (deliveryMode
== DeliveryMode::Fixed
||
234 deliveryMode
== DeliveryMode::LowestPriority
) {
235 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
236 DeliveryMode::names
[deliveryMode
]);
237 // Queue up the interrupt in the IRR.
240 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
241 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
243 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
245 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
248 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
249 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
250 DeliveryMode::names
[deliveryMode
]);
251 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
252 pendingUnmaskableInt
= pendingSmi
= true;
254 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
255 pendingUnmaskableInt
= pendingNmi
= true;
257 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
258 pendingExtInt
= true;
259 extIntVector
= vector
;
260 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
261 pendingUnmaskableInt
= pendingInit
= true;
263 } else if (deliveryMode
== DeliveryMode::SIPI
&&
264 !pendingStartup
&& !startedUp
) {
265 pendingUnmaskableInt
= pendingStartup
= true;
266 startupVector
= vector
;
275 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
278 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
279 panic("Local APICs can't be moved between CPUs"
280 " with different IDs.\n");
283 initialApicId
= cpu
->cpuId();
284 regs
[APIC_ID
] = (initialApicId
<< 24);
285 pioAddr
= x86LocalAPICAddress(initialApicId
, 0);
290 X86ISA::Interrupts::init()
293 // The local apic must register its address ranges on both its pio
294 // port via the basicpiodevice(piodevice) init() function and its
295 // int port that it inherited from IntDevice. Note IntDevice is
296 // not a SimObject itself.
298 BasicPioDevice::init();
301 // the slave port has a range so inform the connected master
302 intSlavePort
.sendRangeChange();
307 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
309 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
310 assert(pkt
->cmd
== MemCmd::MessageReq
);
315 TriggerIntMessage message
= pkt
->getRaw
<TriggerIntMessage
>();
317 "Got Trigger Interrupt message with vector %#x.\n",
320 requestInterrupt(message
.vector
,
321 message
.deliveryMode
, message
.trigger
);
325 panic("Local apic got unknown interrupt message at offset %#x.\n",
329 pkt
->makeAtomicResponse();
335 X86ISA::Interrupts::recvResponse(PacketPtr pkt
)
337 assert(!pkt
->isError());
338 assert(pkt
->cmd
== MemCmd::MessageResp
);
339 if (--pendingIPIs
== 0) {
340 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
341 // Record that the ICR is now idle.
342 low
.deliveryStatus
= 0;
343 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
345 DPRINTF(LocalApic
, "ICR is now idle.\n");
351 X86ISA::Interrupts::getIntAddrRange() const
353 AddrRangeList ranges
;
354 ranges
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
355 x86InterruptAddress(initialApicId
, 0) +
356 PhysAddrAPICRangeSize
));
362 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
364 if (reg
>= APIC_TRIGGER_MODE(0) &&
365 reg
<= APIC_TRIGGER_MODE(15)) {
366 panic("Local APIC Trigger Mode registers are unimplemented.\n");
369 case APIC_ARBITRATION_PRIORITY
:
370 panic("Local APIC Arbitration Priority register unimplemented.\n");
372 case APIC_PROCESSOR_PRIORITY
:
373 panic("Local APIC Processor Priority register unimplemented.\n");
375 case APIC_ERROR_STATUS
:
376 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
378 case APIC_CURRENT_COUNT
:
380 if (apicTimerEvent
.scheduled()) {
381 // Compute how many m5 ticks happen per count.
382 uint64_t ticksPerCount
= clockPeriod() *
383 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
384 // Compute how many m5 ticks are left.
385 uint64_t val
= apicTimerEvent
.when() - curTick();
386 // Turn that into a count.
387 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
400 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
402 uint32_t newVal
= val
;
403 if (reg
>= APIC_IN_SERVICE(0) &&
404 reg
<= APIC_IN_SERVICE(15)) {
405 panic("Local APIC In-Service registers are unimplemented.\n");
407 if (reg
>= APIC_TRIGGER_MODE(0) &&
408 reg
<= APIC_TRIGGER_MODE(15)) {
409 panic("Local APIC Trigger Mode registers are unimplemented.\n");
411 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
412 reg
<= APIC_INTERRUPT_REQUEST(15)) {
413 panic("Local APIC Interrupt Request registers "
414 "are unimplemented.\n");
421 // The Local APIC Version register is read only.
423 case APIC_TASK_PRIORITY
:
426 case APIC_ARBITRATION_PRIORITY
:
427 panic("Local APIC Arbitration Priority register unimplemented.\n");
429 case APIC_PROCESSOR_PRIORITY
:
430 panic("Local APIC Processor Priority register unimplemented.\n");
433 // Remove the interrupt that just completed from the local apic state.
434 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
437 case APIC_LOGICAL_DESTINATION
:
438 newVal
= val
& 0xFF000000;
440 case APIC_DESTINATION_FORMAT
:
441 newVal
= val
| 0x0FFFFFFF;
443 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
444 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
445 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
447 warn("Focus processor checking not implemented.\n");
449 case APIC_ERROR_STATUS
:
451 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
452 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
455 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
461 case APIC_INTERRUPT_COMMAND_LOW
:
463 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
464 // Check if we're already sending an IPI.
465 if (low
.deliveryStatus
) {
470 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
471 TriggerIntMessage message
= 0;
472 message
.destination
= high
.destination
;
473 message
.vector
= low
.vector
;
474 message
.deliveryMode
= low
.deliveryMode
;
475 message
.destMode
= low
.destMode
;
476 message
.level
= low
.level
;
477 message
.trigger
= low
.trigger
;
479 int numContexts
= sys
->numContexts();
480 switch (low
.destShorthand
) {
482 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
483 panic("Lowest priority delivery mode "
484 "IPIs aren't implemented.\n");
486 if (message
.destMode
== 1) {
487 int dest
= message
.destination
;
488 hack_once("Assuming logical destinations are 1 << id.\n");
489 for (int i
= 0; i
< numContexts
; i
++) {
495 if (message
.destination
== 0xFF) {
496 for (int i
= 0; i
< numContexts
; i
++) {
497 if (i
== initialApicId
) {
498 requestInterrupt(message
.vector
,
499 message
.deliveryMode
, message
.trigger
);
505 if (message
.destination
== initialApicId
) {
506 requestInterrupt(message
.vector
,
507 message
.deliveryMode
, message
.trigger
);
509 apics
.push_back(message
.destination
);
516 requestInterrupt(message
.vector
,
517 message
.deliveryMode
, message
.trigger
);
520 requestInterrupt(message
.vector
,
521 message
.deliveryMode
, message
.trigger
);
525 for (int i
= 0; i
< numContexts
; i
++) {
526 if (i
!= initialApicId
) {
533 // Record that an IPI is being sent if one actually is.
535 low
.deliveryStatus
= 1;
536 pendingIPIs
+= apics
.size();
538 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
539 intMasterPort
.sendMessage(apics
, message
, sys
->isTimingMode());
540 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
544 case APIC_LVT_THERMAL_SENSOR
:
545 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
550 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
551 newVal
= (val
& ~readOnlyMask
) |
552 (regs
[reg
] & readOnlyMask
);
555 case APIC_INITIAL_COUNT
:
557 newVal
= bits(val
, 31, 0);
558 // Compute how many timer ticks we're being programmed for.
559 uint64_t newCount
= newVal
*
560 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
561 // Schedule on the edge of the next tick plus the new count.
562 Tick offset
= curTick() % clockPeriod();
564 reschedule(apicTimerEvent
,
565 curTick() + (newCount
+ 1) *
566 clockPeriod() - offset
, true);
569 reschedule(apicTimerEvent
,
570 curTick() + newCount
*
571 clockPeriod(), true);
575 case APIC_CURRENT_COUNT
:
576 //Local APIC Current Count register is read only.
578 case APIC_DIVIDE_CONFIGURATION
:
589 X86ISA::Interrupts::Interrupts(Params
* p
)
590 : BasicPioDevice(p
, PageBytes
), IntDevice(this, p
->int_latency
),
591 apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
592 pendingSmi(false), smiVector(0),
593 pendingNmi(false), nmiVector(0),
594 pendingExtInt(false), extIntVector(0),
595 pendingInit(false), initVector(0),
596 pendingStartup(false), startupVector(0),
597 startedUp(false), pendingUnmaskableInt(false),
598 pendingIPIs(0), cpu(NULL
),
599 intSlavePort(name() + ".int_slave", this, this)
601 memset(regs
, 0, sizeof(regs
));
602 //Set the local apic DFR to the flat model.
603 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
610 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
612 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
613 if (pendingUnmaskableInt
) {
614 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
619 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
622 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
623 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
624 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
632 X86ISA::Interrupts::checkInterruptsRaw() const
634 return pendingUnmaskableInt
|| pendingExtInt
||
635 (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
636 bits(regs
[APIC_TASK_PRIORITY
], 7, 4));
640 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
642 assert(checkInterrupts(tc
));
643 // These are all probably fairly uncommon, so we'll make them easier to
645 if (pendingUnmaskableInt
) {
647 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
648 return std::make_shared
<SystemManagementInterrupt
>();
649 } else if (pendingNmi
) {
650 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
651 return std::make_shared
<NonMaskableInterrupt
>(nmiVector
);
652 } else if (pendingInit
) {
653 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
654 return std::make_shared
<InitInterrupt
>(initVector
);
655 } else if (pendingStartup
) {
656 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
657 return std::make_shared
<StartupInterrupt
>(startupVector
);
659 panic("pendingUnmaskableInt set, but no unmaskable "
660 "ints were pending.\n");
663 } else if (pendingExtInt
) {
664 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
665 return std::make_shared
<ExternalInterrupt
>(extIntVector
);
667 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
668 // The only thing left are fixed and lowest priority interrupts.
669 return std::make_shared
<ExternalInterrupt
>(IRRV
);
674 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
676 assert(checkInterrupts(tc
));
677 if (pendingUnmaskableInt
) {
679 DPRINTF(LocalApic
, "SMI sent to core.\n");
681 } else if (pendingNmi
) {
682 DPRINTF(LocalApic
, "NMI sent to core.\n");
684 } else if (pendingInit
) {
685 DPRINTF(LocalApic
, "Init sent to core.\n");
688 } else if (pendingStartup
) {
689 DPRINTF(LocalApic
, "SIPI sent to core.\n");
690 pendingStartup
= false;
693 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
694 pendingUnmaskableInt
= false;
695 } else if (pendingExtInt
) {
696 pendingExtInt
= false;
698 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
699 // Mark the interrupt as "in service".
701 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
702 // Clear it out of the IRR.
703 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
709 X86ISA::Interrupts::serialize(CheckpointOut
&cp
) const
711 SERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
712 SERIALIZE_SCALAR(pendingSmi
);
713 SERIALIZE_SCALAR(smiVector
);
714 SERIALIZE_SCALAR(pendingNmi
);
715 SERIALIZE_SCALAR(nmiVector
);
716 SERIALIZE_SCALAR(pendingExtInt
);
717 SERIALIZE_SCALAR(extIntVector
);
718 SERIALIZE_SCALAR(pendingInit
);
719 SERIALIZE_SCALAR(initVector
);
720 SERIALIZE_SCALAR(pendingStartup
);
721 SERIALIZE_SCALAR(startupVector
);
722 SERIALIZE_SCALAR(startedUp
);
723 SERIALIZE_SCALAR(pendingUnmaskableInt
);
724 SERIALIZE_SCALAR(pendingIPIs
);
725 SERIALIZE_SCALAR(IRRV
);
726 SERIALIZE_SCALAR(ISRV
);
727 bool apicTimerEventScheduled
= apicTimerEvent
.scheduled();
728 SERIALIZE_SCALAR(apicTimerEventScheduled
);
729 Tick apicTimerEventTick
= apicTimerEvent
.when();
730 SERIALIZE_SCALAR(apicTimerEventTick
);
734 X86ISA::Interrupts::unserialize(CheckpointIn
&cp
)
736 UNSERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
737 UNSERIALIZE_SCALAR(pendingSmi
);
738 UNSERIALIZE_SCALAR(smiVector
);
739 UNSERIALIZE_SCALAR(pendingNmi
);
740 UNSERIALIZE_SCALAR(nmiVector
);
741 UNSERIALIZE_SCALAR(pendingExtInt
);
742 UNSERIALIZE_SCALAR(extIntVector
);
743 UNSERIALIZE_SCALAR(pendingInit
);
744 UNSERIALIZE_SCALAR(initVector
);
745 UNSERIALIZE_SCALAR(pendingStartup
);
746 UNSERIALIZE_SCALAR(startupVector
);
747 UNSERIALIZE_SCALAR(startedUp
);
748 UNSERIALIZE_SCALAR(pendingUnmaskableInt
);
749 UNSERIALIZE_SCALAR(pendingIPIs
);
750 UNSERIALIZE_SCALAR(IRRV
);
751 UNSERIALIZE_SCALAR(ISRV
);
752 bool apicTimerEventScheduled
;
753 UNSERIALIZE_SCALAR(apicTimerEventScheduled
);
754 if (apicTimerEventScheduled
) {
755 Tick apicTimerEventTick
;
756 UNSERIALIZE_SCALAR(apicTimerEventTick
);
757 if (apicTimerEvent
.scheduled()) {
758 reschedule(apicTimerEvent
, apicTimerEventTick
, true);
760 schedule(apicTimerEvent
, apicTimerEventTick
);
766 X86LocalApicParams::create()
768 return new X86ISA::Interrupts(this);
772 X86ISA::Interrupts::processApicTimerEvent() {
773 if (triggerTimerInterrupt())
774 setReg(APIC_INITIAL_COUNT
, readReg(APIC_INITIAL_COUNT
));