src/arch/x86/interrupts.cc

   1 /*
   2  * Copyright (c) 2012-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2008 The Hewlett-Packard Development Company
  15  * All rights reserved.
  16  *
  17  * The license below extends only to copyright in the software and shall
  18  * not be construed as granting a license to any other intellectual
  19  * property including but not limited to intellectual property relating
  20  * to a hardware implementation of the functionality of the software
  21  * licensed hereunder.  You may use the software subject to the license
  22  * terms below provided that you ensure that this notice is replicated
  23  * unmodified and in its entirety in all distributions of the software,
  24  * modified or unmodified, in source code or in binary form.
  25  *
  26  * Redistribution and use in source and binary forms, with or without
  27  * modification, are permitted provided that the following conditions are
  28  * met: redistributions of source code must retain the above copyright
  29  * notice, this list of conditions and the following disclaimer;
  30  * redistributions in binary form must reproduce the above copyright
  31  * notice, this list of conditions and the following disclaimer in the
  32  * documentation and/or other materials provided with the distribution;
  33  * neither the name of the copyright holders nor the names of its
  34  * contributors may be used to endorse or promote products derived from
  35  * this software without specific prior written permission.
  36  *
  37  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  38  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  39  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  40  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  41  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  42  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  43  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  44  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  45  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  46  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48  *
  49  * Authors: Gabe Black
  50  */
  51
  52 #include "arch/x86/interrupts.hh"
  53
  54 #include <memory>
  55
  56 #include "arch/x86/intmessage.hh"
  57 #include "arch/x86/regs/apic.hh"
  58 #include "cpu/base.hh"
  59 #include "debug/LocalApic.hh"
  60 #include "dev/x86/i82094aa.hh"
  61 #include "dev/x86/pc.hh"
  62 #include "dev/x86/south_bridge.hh"
  63 #include "mem/packet_access.hh"
  64 #include "sim/full_system.hh"
  65 #include "sim/system.hh"
  66
  67 int
  68 divideFromConf(uint32_t conf)
  69 {
  70     // This figures out what division we want from the division configuration
  71     // register in the local APIC. The encoding is a little odd but it can
  72     // be deciphered fairly easily.
  73     int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
  74     shift = (shift + 1) % 8;
  75     return 1 << shift;
  76 }
  77
  78 namespace X86ISA
  79 {
  80
  81 ApicRegIndex
  82 decodeAddr(Addr paddr)
  83 {
  84     ApicRegIndex regNum;
  85     paddr &= ~mask(3);
  86     switch (paddr)
  87     {
  88       case 0x20:
  89         regNum = APIC_ID;
  90         break;
  91       case 0x30:
  92         regNum = APIC_VERSION;
  93         break;
  94       case 0x80:
  95         regNum = APIC_TASK_PRIORITY;
  96         break;
  97       case 0x90:
  98         regNum = APIC_ARBITRATION_PRIORITY;
  99         break;
 100       case 0xA0:
 101         regNum = APIC_PROCESSOR_PRIORITY;
 102         break;
 103       case 0xB0:
 104         regNum = APIC_EOI;
 105         break;
 106       case 0xD0:
 107         regNum = APIC_LOGICAL_DESTINATION;
 108         break;
 109       case 0xE0:
 110         regNum = APIC_DESTINATION_FORMAT;
 111         break;
 112       case 0xF0:
 113         regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
 114         break;
 115       case 0x100:
 116       case 0x110:
 117       case 0x120:
 118       case 0x130:
 119       case 0x140:
 120       case 0x150:
 121       case 0x160:
 122       case 0x170:
 123         regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x10);
 124         break;
 125       case 0x180:
 126       case 0x190:
 127       case 0x1A0:
 128       case 0x1B0:
 129       case 0x1C0:
 130       case 0x1D0:
 131       case 0x1E0:
 132       case 0x1F0:
 133         regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x10);
 134         break;
 135       case 0x200:
 136       case 0x210:
 137       case 0x220:
 138       case 0x230:
 139       case 0x240:
 140       case 0x250:
 141       case 0x260:
 142       case 0x270:
 143         regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x10);
 144         break;
 145       case 0x280:
 146         regNum = APIC_ERROR_STATUS;
 147         break;
 148       case 0x300:
 149         regNum = APIC_INTERRUPT_COMMAND_LOW;
 150         break;
 151       case 0x310:
 152         regNum = APIC_INTERRUPT_COMMAND_HIGH;
 153         break;
 154       case 0x320:
 155         regNum = APIC_LVT_TIMER;
 156         break;
 157       case 0x330:
 158         regNum = APIC_LVT_THERMAL_SENSOR;
 159         break;
 160       case 0x340:
 161         regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
 162         break;
 163       case 0x350:
 164         regNum = APIC_LVT_LINT0;
 165         break;
 166       case 0x360:
 167         regNum = APIC_LVT_LINT1;
 168         break;
 169       case 0x370:
 170         regNum = APIC_LVT_ERROR;
 171         break;
 172       case 0x380:
 173         regNum = APIC_INITIAL_COUNT;
 174         break;
 175       case 0x390:
 176         regNum = APIC_CURRENT_COUNT;
 177         break;
 178       case 0x3E0:
 179         regNum = APIC_DIVIDE_CONFIGURATION;
 180         break;
 181       default:
 182         // A reserved register field.
 183         panic("Accessed reserved register field %#x.\n", paddr);
 184         break;
 185     }
 186     return regNum;
 187 }
 188 }
 189
 190 Tick
 191 X86ISA::Interrupts::read(PacketPtr pkt)
 192 {
 193     Addr offset = pkt->getAddr() - pioAddr;
 194     // Make sure we're at least only accessing one register.
 195     if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
 196         panic("Accessed more than one register at a time in the APIC!\n");
 197     ApicRegIndex reg = decodeAddr(offset);
 198     uint32_t val = htog(readReg(reg));
 199     DPRINTF(LocalApic,
 200             "Reading Local APIC register %d at offset %#x as %#x.\n",
 201             reg, offset, val);
 202     pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
 203     pkt->makeAtomicResponse();
 204     return pioDelay;
 205 }
 206
 207 Tick
 208 X86ISA::Interrupts::write(PacketPtr pkt)
 209 {
 210     Addr offset = pkt->getAddr() - pioAddr;
 211     // Make sure we're at least only accessing one register.
 212     if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
 213         panic("Accessed more than one register at a time in the APIC!\n");
 214     ApicRegIndex reg = decodeAddr(offset);
 215     uint32_t val = regs[reg];
 216     pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
 217     DPRINTF(LocalApic,
 218             "Writing Local APIC register %d at offset %#x as %#x.\n",
 219             reg, offset, gtoh(val));
 220     setReg(reg, gtoh(val));
 221     pkt->makeAtomicResponse();
 222     return pioDelay;
 223 }
 224 void
 225 X86ISA::Interrupts::requestInterrupt(uint8_t vector,
 226         uint8_t deliveryMode, bool level)
 227 {
 228     /*
 229      * Fixed and lowest-priority delivery mode interrupts are handled
 230      * using the IRR/ISR registers, checking against the TPR, etc.
 231      * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
 232      */
 233     if (deliveryMode == DeliveryMode::Fixed ||
 234             deliveryMode == DeliveryMode::LowestPriority) {
 235         DPRINTF(LocalApic, "Interrupt is an %s.\n",
 236                 DeliveryMode::names[deliveryMode]);
 237         // Queue up the interrupt in the IRR.
 238         if (vector > IRRV)
 239             IRRV = vector;
 240         if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
 241             setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
 242             if (level) {
 243                 setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
 244             } else {
 245                 clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
 246             }
 247         }
 248     } else if (!DeliveryMode::isReserved(deliveryMode)) {
 249         DPRINTF(LocalApic, "Interrupt is an %s.\n",
 250                 DeliveryMode::names[deliveryMode]);
 251         if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
 252             pendingUnmaskableInt = pendingSmi = true;
 253             smiVector = vector;
 254         } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
 255             pendingUnmaskableInt = pendingNmi = true;
 256             nmiVector = vector;
 257         } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
 258             pendingExtInt = true;
 259             extIntVector = vector;
 260         } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
 261             pendingUnmaskableInt = pendingInit = true;
 262             initVector = vector;
 263         } else if (deliveryMode == DeliveryMode::SIPI &&
 264                 !pendingStartup && !startedUp) {
 265             pendingUnmaskableInt = pendingStartup = true;
 266             startupVector = vector;
 267         }
 268     }
 269     if (FullSystem)
 270         cpu->wakeup(0);
 271 }
 272
 273
 274 void
 275 X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
 276 {
 277     assert(newCPU);
 278     if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
 279         panic("Local APICs can't be moved between CPUs"
 280                 " with different IDs.\n");
 281     }
 282     cpu = newCPU;
 283     initialApicId = cpu->cpuId();
 284     regs[APIC_ID] = (initialApicId << 24);
 285     pioAddr = x86LocalAPICAddress(initialApicId, 0);
 286 }
 287
 288
 289 void
 290 X86ISA::Interrupts::init()
 291 {
 292     //
 293     // The local apic must register its address ranges on its pio
 294     // port via the basicpiodevice(piodevice) init() function.
 295     PioDevice::init();
 296
 297     // The slave port has a range, so inform the connected master.
 298     intSlavePort.sendRangeChange();
 299     // If the master port isn't connected, we can't send interrupts anywhere.
 300     panic_if(!intMasterPort.isConnected(),
 301             "Int port not connected to anything!");
 302 }
 303
 304
 305 Tick
 306 X86ISA::Interrupts::recvMessage(PacketPtr pkt)
 307 {
 308     Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
 309     assert(pkt->cmd == MemCmd::WriteReq);
 310     switch(offset)
 311     {
 312       case 0:
 313         {
 314             TriggerIntMessage message = pkt->getRaw<TriggerIntMessage>();
 315             DPRINTF(LocalApic,
 316                     "Got Trigger Interrupt message with vector %#x.\n",
 317                     message.vector);
 318
 319             requestInterrupt(message.vector,
 320                     message.deliveryMode, message.trigger);
 321         }
 322         break;
 323       default:
 324         panic("Local apic got unknown interrupt message at offset %#x.\n",
 325                 offset);
 326         break;
 327     }
 328     pkt->makeAtomicResponse();
 329     return pioDelay;
 330 }
 331
 332
 333 bool
 334 X86ISA::Interrupts::recvResponse(PacketPtr pkt)
 335 {
 336     assert(!pkt->isError());
 337     assert(pkt->cmd == MemCmd::WriteResp);
 338     if (--pendingIPIs == 0) {
 339         InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
 340         // Record that the ICR is now idle.
 341         low.deliveryStatus = 0;
 342         regs[APIC_INTERRUPT_COMMAND_LOW] = low;
 343     }
 344     DPRINTF(LocalApic, "ICR is now idle.\n");
 345     return true;
 346 }
 347
 348
 349 AddrRangeList
 350 X86ISA::Interrupts::getAddrRanges() const
 351 {
 352     assert(cpu);
 353     AddrRangeList ranges;
 354     ranges.push_back(RangeSize(pioAddr, PageBytes));
 355     return ranges;
 356 }
 357
 358
 359 AddrRangeList
 360 X86ISA::Interrupts::getIntAddrRange() const
 361 {
 362     AddrRangeList ranges;
 363     ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
 364                              x86InterruptAddress(initialApicId, 0) +
 365                              PhysAddrAPICRangeSize));
 366     return ranges;
 367 }
 368
 369
 370 uint32_t
 371 X86ISA::Interrupts::readReg(ApicRegIndex reg)
 372 {
 373     if (reg >= APIC_TRIGGER_MODE(0) &&
 374             reg <= APIC_TRIGGER_MODE(15)) {
 375         panic("Local APIC Trigger Mode registers are unimplemented.\n");
 376     }
 377     switch (reg) {
 378       case APIC_ARBITRATION_PRIORITY:
 379         panic("Local APIC Arbitration Priority register unimplemented.\n");
 380         break;
 381       case APIC_PROCESSOR_PRIORITY:
 382         panic("Local APIC Processor Priority register unimplemented.\n");
 383         break;
 384       case APIC_ERROR_STATUS:
 385         regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
 386         break;
 387       case APIC_CURRENT_COUNT:
 388         {
 389             if (apicTimerEvent.scheduled()) {
 390                 // Compute how many m5 ticks happen per count.
 391                 uint64_t ticksPerCount = clockPeriod() *
 392                     divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
 393                 // Compute how many m5 ticks are left.
 394                 uint64_t val = apicTimerEvent.when() - curTick();
 395                 // Turn that into a count.
 396                 val = (val + ticksPerCount - 1) / ticksPerCount;
 397                 return val;
 398             } else {
 399                 return 0;
 400             }
 401         }
 402       default:
 403         break;
 404     }
 405     return regs[reg];
 406 }
 407
 408 void
 409 X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
 410 {
 411     uint32_t newVal = val;
 412     if (reg >= APIC_IN_SERVICE(0) &&
 413             reg <= APIC_IN_SERVICE(15)) {
 414         panic("Local APIC In-Service registers are unimplemented.\n");
 415     }
 416     if (reg >= APIC_TRIGGER_MODE(0) &&
 417             reg <= APIC_TRIGGER_MODE(15)) {
 418         panic("Local APIC Trigger Mode registers are unimplemented.\n");
 419     }
 420     if (reg >= APIC_INTERRUPT_REQUEST(0) &&
 421             reg <= APIC_INTERRUPT_REQUEST(15)) {
 422         panic("Local APIC Interrupt Request registers "
 423                 "are unimplemented.\n");
 424     }
 425     switch (reg) {
 426       case APIC_ID:
 427         newVal = val & 0xFF;
 428         break;
 429       case APIC_VERSION:
 430         // The Local APIC Version register is read only.
 431         return;
 432       case APIC_TASK_PRIORITY:
 433         newVal = val & 0xFF;
 434         break;
 435       case APIC_ARBITRATION_PRIORITY:
 436         panic("Local APIC Arbitration Priority register unimplemented.\n");
 437         break;
 438       case APIC_PROCESSOR_PRIORITY:
 439         panic("Local APIC Processor Priority register unimplemented.\n");
 440         break;
 441       case APIC_EOI:
 442         // Remove the interrupt that just completed from the local apic state.
 443         clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
 444         updateISRV();
 445         return;
 446       case APIC_LOGICAL_DESTINATION:
 447         newVal = val & 0xFF000000;
 448         break;
 449       case APIC_DESTINATION_FORMAT:
 450         newVal = val | 0x0FFFFFFF;
 451         break;
 452       case APIC_SPURIOUS_INTERRUPT_VECTOR:
 453         regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
 454         regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
 455         if (val & (1 << 9))
 456             warn("Focus processor checking not implemented.\n");
 457         break;
 458       case APIC_ERROR_STATUS:
 459         {
 460             if (regs[APIC_INTERNAL_STATE] & 0x1) {
 461                 regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
 462                 newVal = 0;
 463             } else {
 464                 regs[APIC_INTERNAL_STATE] |= ULL(0x1);
 465                 return;
 466             }
 467
 468         }
 469         break;
 470       case APIC_INTERRUPT_COMMAND_LOW:
 471         {
 472             InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
 473             // Check if we're already sending an IPI.
 474             if (low.deliveryStatus) {
 475                 newVal = low;
 476                 break;
 477             }
 478             low = val;
 479             InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
 480             TriggerIntMessage message = 0;
 481             message.destination = high.destination;
 482             message.vector = low.vector;
 483             message.deliveryMode = low.deliveryMode;
 484             message.destMode = low.destMode;
 485             message.level = low.level;
 486             message.trigger = low.trigger;
 487             ApicList apics;
 488             int numContexts = sys->numContexts();
 489             switch (low.destShorthand) {
 490               case 0:
 491                 if (message.deliveryMode == DeliveryMode::LowestPriority) {
 492                     panic("Lowest priority delivery mode "
 493                             "IPIs aren't implemented.\n");
 494                 }
 495                 if (message.destMode == 1) {
 496                     int dest = message.destination;
 497                     hack_once("Assuming logical destinations are 1 << id.\n");
 498                     for (int i = 0; i < numContexts; i++) {
 499                         if (dest & 0x1)
 500                             apics.push_back(i);
 501                         dest = dest >> 1;
 502                     }
 503                 } else {
 504                     if (message.destination == 0xFF) {
 505                         for (int i = 0; i < numContexts; i++) {
 506                             if (i == initialApicId) {
 507                                 requestInterrupt(message.vector,
 508                                         message.deliveryMode, message.trigger);
 509                             } else {
 510                                 apics.push_back(i);
 511                             }
 512                         }
 513                     } else {
 514                         if (message.destination == initialApicId) {
 515                             requestInterrupt(message.vector,
 516                                     message.deliveryMode, message.trigger);
 517                         } else {
 518                             apics.push_back(message.destination);
 519                         }
 520                     }
 521                 }
 522                 break;
 523               case 1:
 524                 newVal = val;
 525                 requestInterrupt(message.vector,
 526                         message.deliveryMode, message.trigger);
 527                 break;
 528               case 2:
 529                 requestInterrupt(message.vector,
 530                         message.deliveryMode, message.trigger);
 531                 // Fall through
 532               case 3:
 533                 {
 534                     for (int i = 0; i < numContexts; i++) {
 535                         if (i != initialApicId) {
 536                             apics.push_back(i);
 537                         }
 538                     }
 539                 }
 540                 break;
 541             }
 542             // Record that an IPI is being sent if one actually is.
 543             if (apics.size()) {
 544                 low.deliveryStatus = 1;
 545                 pendingIPIs += apics.size();
 546             }
 547             regs[APIC_INTERRUPT_COMMAND_LOW] = low;
 548             intMasterPort.sendMessage(apics, message, sys->isTimingMode());
 549             newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
 550         }
 551         break;
 552       case APIC_LVT_TIMER:
 553       case APIC_LVT_THERMAL_SENSOR:
 554       case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
 555       case APIC_LVT_LINT0:
 556       case APIC_LVT_LINT1:
 557       case APIC_LVT_ERROR:
 558         {
 559             uint64_t readOnlyMask = (1 << 12) | (1 << 14);
 560             newVal = (val & ~readOnlyMask) |
 561                      (regs[reg] & readOnlyMask);
 562         }
 563         break;
 564       case APIC_INITIAL_COUNT:
 565         {
 566             newVal = bits(val, 31, 0);
 567             // Compute how many timer ticks we're being programmed for.
 568             uint64_t newCount = newVal *
 569                 (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
 570             // Schedule on the edge of the next tick plus the new count.
 571             Tick offset = curTick() % clockPeriod();
 572             if (offset) {
 573                 reschedule(apicTimerEvent,
 574                            curTick() + (newCount + 1) *
 575                            clockPeriod() - offset, true);
 576             } else {
 577                 if (newCount)
 578                     reschedule(apicTimerEvent,
 579                                curTick() + newCount *
 580                                clockPeriod(), true);
 581             }
 582         }
 583         break;
 584       case APIC_CURRENT_COUNT:
 585         //Local APIC Current Count register is read only.
 586         return;
 587       case APIC_DIVIDE_CONFIGURATION:
 588         newVal = val & 0xB;
 589         break;
 590       default:
 591         break;
 592     }
 593     regs[reg] = newVal;
 594     return;
 595 }
 596
 597
 598 X86ISA::Interrupts::Interrupts(Params * p)
 599     : PioDevice(p),
 600       apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
 601       pendingSmi(false), smiVector(0),
 602       pendingNmi(false), nmiVector(0),
 603       pendingExtInt(false), extIntVector(0),
 604       pendingInit(false), initVector(0),
 605       pendingStartup(false), startupVector(0),
 606       startedUp(false), pendingUnmaskableInt(false),
 607       pendingIPIs(0), cpu(NULL),
 608       intSlavePort(name() + ".int_slave", this, this),
 609       intMasterPort(name() + ".int_master", this, this, p->int_latency),
 610       pioDelay(p->pio_latency)
 611 {
 612     memset(regs, 0, sizeof(regs));
 613     //Set the local apic DFR to the flat model.
 614     regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
 615     ISRV = 0;
 616     IRRV = 0;
 617 }
 618
 619
 620 bool
 621 X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
 622 {
 623     RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
 624     if (pendingUnmaskableInt) {
 625         DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
 626         return true;
 627     }
 628     if (rflags.intf) {
 629         if (pendingExtInt) {
 630             DPRINTF(LocalApic, "Reported pending external interrupt.\n");
 631             return true;
 632         }
 633         if (IRRV > ISRV && bits(IRRV, 7, 4) >
 634                bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
 635             DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
 636             return true;
 637         }
 638     }
 639     return false;
 640 }
 641
 642 bool
 643 X86ISA::Interrupts::checkInterruptsRaw() const
 644 {
 645     return pendingUnmaskableInt || pendingExtInt ||
 646         (IRRV > ISRV && bits(IRRV, 7, 4) >
 647          bits(regs[APIC_TASK_PRIORITY], 7, 4));
 648 }
 649
 650 Fault
 651 X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
 652 {
 653     assert(checkInterrupts(tc));
 654     // These are all probably fairly uncommon, so we'll make them easier to
 655     // check for.
 656     if (pendingUnmaskableInt) {
 657         if (pendingSmi) {
 658             DPRINTF(LocalApic, "Generated SMI fault object.\n");
 659             return std::make_shared<SystemManagementInterrupt>();
 660         } else if (pendingNmi) {
 661             DPRINTF(LocalApic, "Generated NMI fault object.\n");
 662             return std::make_shared<NonMaskableInterrupt>(nmiVector);
 663         } else if (pendingInit) {
 664             DPRINTF(LocalApic, "Generated INIT fault object.\n");
 665             return std::make_shared<InitInterrupt>(initVector);
 666         } else if (pendingStartup) {
 667             DPRINTF(LocalApic, "Generating SIPI fault object.\n");
 668             return std::make_shared<StartupInterrupt>(startupVector);
 669         } else {
 670             panic("pendingUnmaskableInt set, but no unmaskable "
 671                     "ints were pending.\n");
 672             return NoFault;
 673         }
 674     } else if (pendingExtInt) {
 675         DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
 676         return std::make_shared<ExternalInterrupt>(extIntVector);
 677     } else {
 678         DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
 679         // The only thing left are fixed and lowest priority interrupts.
 680         return std::make_shared<ExternalInterrupt>(IRRV);
 681     }
 682 }
 683
 684 void
 685 X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
 686 {
 687     assert(checkInterrupts(tc));
 688     if (pendingUnmaskableInt) {
 689         if (pendingSmi) {
 690             DPRINTF(LocalApic, "SMI sent to core.\n");
 691             pendingSmi = false;
 692         } else if (pendingNmi) {
 693             DPRINTF(LocalApic, "NMI sent to core.\n");
 694             pendingNmi = false;
 695         } else if (pendingInit) {
 696             DPRINTF(LocalApic, "Init sent to core.\n");
 697             pendingInit = false;
 698             startedUp = false;
 699         } else if (pendingStartup) {
 700             DPRINTF(LocalApic, "SIPI sent to core.\n");
 701             pendingStartup = false;
 702             startedUp = true;
 703         }
 704         if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
 705             pendingUnmaskableInt = false;
 706     } else if (pendingExtInt) {
 707         pendingExtInt = false;
 708     } else {
 709         DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
 710         // Mark the interrupt as "in service".
 711         ISRV = IRRV;
 712         setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
 713         // Clear it out of the IRR.
 714         clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
 715         updateIRRV();
 716     }
 717 }
 718
 719 void
 720 X86ISA::Interrupts::serialize(CheckpointOut &cp) const
 721 {
 722     SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
 723     SERIALIZE_SCALAR(pendingSmi);
 724     SERIALIZE_SCALAR(smiVector);
 725     SERIALIZE_SCALAR(pendingNmi);
 726     SERIALIZE_SCALAR(nmiVector);
 727     SERIALIZE_SCALAR(pendingExtInt);
 728     SERIALIZE_SCALAR(extIntVector);
 729     SERIALIZE_SCALAR(pendingInit);
 730     SERIALIZE_SCALAR(initVector);
 731     SERIALIZE_SCALAR(pendingStartup);
 732     SERIALIZE_SCALAR(startupVector);
 733     SERIALIZE_SCALAR(startedUp);
 734     SERIALIZE_SCALAR(pendingUnmaskableInt);
 735     SERIALIZE_SCALAR(pendingIPIs);
 736     SERIALIZE_SCALAR(IRRV);
 737     SERIALIZE_SCALAR(ISRV);
 738     bool apicTimerEventScheduled = apicTimerEvent.scheduled();
 739     SERIALIZE_SCALAR(apicTimerEventScheduled);
 740     Tick apicTimerEventTick = apicTimerEvent.when();
 741     SERIALIZE_SCALAR(apicTimerEventTick);
 742 }
 743
 744 void
 745 X86ISA::Interrupts::unserialize(CheckpointIn &cp)
 746 {
 747     UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
 748     UNSERIALIZE_SCALAR(pendingSmi);
 749     UNSERIALIZE_SCALAR(smiVector);
 750     UNSERIALIZE_SCALAR(pendingNmi);
 751     UNSERIALIZE_SCALAR(nmiVector);
 752     UNSERIALIZE_SCALAR(pendingExtInt);
 753     UNSERIALIZE_SCALAR(extIntVector);
 754     UNSERIALIZE_SCALAR(pendingInit);
 755     UNSERIALIZE_SCALAR(initVector);
 756     UNSERIALIZE_SCALAR(pendingStartup);
 757     UNSERIALIZE_SCALAR(startupVector);
 758     UNSERIALIZE_SCALAR(startedUp);
 759     UNSERIALIZE_SCALAR(pendingUnmaskableInt);
 760     UNSERIALIZE_SCALAR(pendingIPIs);
 761     UNSERIALIZE_SCALAR(IRRV);
 762     UNSERIALIZE_SCALAR(ISRV);
 763     bool apicTimerEventScheduled;
 764     UNSERIALIZE_SCALAR(apicTimerEventScheduled);
 765     if (apicTimerEventScheduled) {
 766         Tick apicTimerEventTick;
 767         UNSERIALIZE_SCALAR(apicTimerEventTick);
 768         if (apicTimerEvent.scheduled()) {
 769             reschedule(apicTimerEvent, apicTimerEventTick, true);
 770         } else {
 771             schedule(apicTimerEvent, apicTimerEventTick);
 772         }
 773     }
 774 }
 775
 776 X86ISA::Interrupts *
 777 X86LocalApicParams::create()
 778 {
 779     return new X86ISA::Interrupts(this);
 780 }
 781
 782 void
 783 X86ISA::Interrupts::processApicTimerEvent() {
 784     if (triggerTimerInterrupt())
 785         setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT));
 786 }