2 * Copyright (c) 2012-2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder. You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
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52 #include "arch/x86/interrupts.hh"
57 #include "arch/x86/intmessage.hh"
58 #include "arch/x86/regs/apic.hh"
59 #include "cpu/base.hh"
60 #include "debug/LocalApic.hh"
61 #include "dev/x86/i82094aa.hh"
62 #include "dev/x86/pc.hh"
63 #include "dev/x86/south_bridge.hh"
64 #include "mem/packet_access.hh"
65 #include "sim/full_system.hh"
66 #include "sim/system.hh"
69 divideFromConf(uint32_t conf
)
71 // This figures out what division we want from the division configuration
72 // register in the local APIC. The encoding is a little odd but it can
73 // be deciphered fairly easily.
74 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
75 shift
= (shift
+ 1) % 8;
83 decodeAddr(Addr paddr
)
93 regNum
= APIC_VERSION
;
96 regNum
= APIC_TASK_PRIORITY
;
99 regNum
= APIC_ARBITRATION_PRIORITY
;
102 regNum
= APIC_PROCESSOR_PRIORITY
;
108 regNum
= APIC_LOGICAL_DESTINATION
;
111 regNum
= APIC_DESTINATION_FORMAT
;
114 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
124 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x10);
134 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x10);
144 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x10);
147 regNum
= APIC_ERROR_STATUS
;
150 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
153 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
156 regNum
= APIC_LVT_TIMER
;
159 regNum
= APIC_LVT_THERMAL_SENSOR
;
162 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
165 regNum
= APIC_LVT_LINT0
;
168 regNum
= APIC_LVT_LINT1
;
171 regNum
= APIC_LVT_ERROR
;
174 regNum
= APIC_INITIAL_COUNT
;
177 regNum
= APIC_CURRENT_COUNT
;
180 regNum
= APIC_DIVIDE_CONFIGURATION
;
183 // A reserved register field.
184 panic("Accessed reserved register field %#x.\n", paddr
);
192 X86ISA::Interrupts::read(PacketPtr pkt
)
194 Addr offset
= pkt
->getAddr() - pioAddr
;
195 // Make sure we're at least only accessing one register.
196 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
197 panic("Accessed more than one register at a time in the APIC!\n");
198 ApicRegIndex reg
= decodeAddr(offset
);
199 uint32_t val
= htole(readReg(reg
));
201 "Reading Local APIC register %d at offset %#x as %#x.\n",
203 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
204 pkt
->makeAtomicResponse();
209 X86ISA::Interrupts::write(PacketPtr pkt
)
211 Addr offset
= pkt
->getAddr() - pioAddr
;
212 // Make sure we're at least only accessing one register.
213 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
214 panic("Accessed more than one register at a time in the APIC!\n");
215 ApicRegIndex reg
= decodeAddr(offset
);
216 uint32_t val
= regs
[reg
];
217 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
219 "Writing Local APIC register %d at offset %#x as %#x.\n",
220 reg
, offset
, letoh(val
));
221 setReg(reg
, letoh(val
));
222 pkt
->makeAtomicResponse();
226 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
227 uint8_t deliveryMode
, bool level
)
230 * Fixed and lowest-priority delivery mode interrupts are handled
231 * using the IRR/ISR registers, checking against the TPR, etc.
232 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
234 if (deliveryMode
== DeliveryMode::Fixed
||
235 deliveryMode
== DeliveryMode::LowestPriority
) {
236 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
237 DeliveryMode::names
[deliveryMode
]);
238 // Queue up the interrupt in the IRR.
241 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
242 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
244 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
246 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
249 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
250 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
251 DeliveryMode::names
[deliveryMode
]);
252 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
253 pendingUnmaskableInt
= pendingSmi
= true;
255 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
256 pendingUnmaskableInt
= pendingNmi
= true;
258 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
259 pendingExtInt
= true;
260 extIntVector
= vector
;
261 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
262 pendingUnmaskableInt
= pendingInit
= true;
264 } else if (deliveryMode
== DeliveryMode::SIPI
&&
265 !pendingStartup
&& !startedUp
) {
266 pendingUnmaskableInt
= pendingStartup
= true;
267 startupVector
= vector
;
276 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
279 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
280 panic("Local APICs can't be moved between CPUs"
281 " with different IDs.\n");
284 initialApicId
= cpu
->cpuId();
285 regs
[APIC_ID
] = (initialApicId
<< 24);
286 pioAddr
= x86LocalAPICAddress(initialApicId
, 0);
291 X86ISA::Interrupts::init()
293 panic_if(!intMasterPort
.isConnected(),
294 "Int port not connected to anything!");
295 panic_if(!pioPort
.isConnected(),
296 "Pio port of %s not connected to anything!", name());
298 intSlavePort
.sendRangeChange();
299 pioPort
.sendRangeChange();
304 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
306 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
307 assert(pkt
->cmd
== MemCmd::WriteReq
);
312 TriggerIntMessage message
= pkt
->getRaw
<TriggerIntMessage
>();
314 "Got Trigger Interrupt message with vector %#x.\n",
317 requestInterrupt(message
.vector
,
318 message
.deliveryMode
, message
.trigger
);
322 panic("Local apic got unknown interrupt message at offset %#x.\n",
326 pkt
->makeAtomicResponse();
332 X86ISA::Interrupts::completeIPI(PacketPtr pkt
)
334 if (--pendingIPIs
== 0) {
335 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
336 // Record that the ICR is now idle.
337 low
.deliveryStatus
= 0;
338 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
340 DPRINTF(LocalApic
, "ICR is now idle.\n");
346 X86ISA::Interrupts::getAddrRanges() const
349 AddrRangeList ranges
;
350 ranges
.push_back(RangeSize(pioAddr
, PageBytes
));
356 X86ISA::Interrupts::getIntAddrRange() const
358 AddrRangeList ranges
;
359 ranges
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
360 x86InterruptAddress(initialApicId
, 0) +
361 PhysAddrAPICRangeSize
));
367 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
369 if (reg
>= APIC_TRIGGER_MODE(0) &&
370 reg
<= APIC_TRIGGER_MODE(15)) {
371 panic("Local APIC Trigger Mode registers are unimplemented.\n");
374 case APIC_ARBITRATION_PRIORITY
:
375 panic("Local APIC Arbitration Priority register unimplemented.\n");
377 case APIC_PROCESSOR_PRIORITY
:
378 panic("Local APIC Processor Priority register unimplemented.\n");
380 case APIC_ERROR_STATUS
:
381 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
383 case APIC_CURRENT_COUNT
:
385 if (apicTimerEvent
.scheduled()) {
386 // Compute how many m5 ticks happen per count.
387 uint64_t ticksPerCount
= clockPeriod() *
388 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
389 // Compute how many m5 ticks are left.
390 uint64_t val
= apicTimerEvent
.when() - curTick();
391 // Turn that into a count.
392 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
405 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
407 uint32_t newVal
= val
;
408 if (reg
>= APIC_IN_SERVICE(0) &&
409 reg
<= APIC_IN_SERVICE(15)) {
410 panic("Local APIC In-Service registers are unimplemented.\n");
412 if (reg
>= APIC_TRIGGER_MODE(0) &&
413 reg
<= APIC_TRIGGER_MODE(15)) {
414 panic("Local APIC Trigger Mode registers are unimplemented.\n");
416 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
417 reg
<= APIC_INTERRUPT_REQUEST(15)) {
418 panic("Local APIC Interrupt Request registers "
419 "are unimplemented.\n");
426 // The Local APIC Version register is read only.
428 case APIC_TASK_PRIORITY
:
431 case APIC_ARBITRATION_PRIORITY
:
432 panic("Local APIC Arbitration Priority register unimplemented.\n");
434 case APIC_PROCESSOR_PRIORITY
:
435 panic("Local APIC Processor Priority register unimplemented.\n");
438 // Remove the interrupt that just completed from the local apic state.
439 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
442 case APIC_LOGICAL_DESTINATION
:
443 newVal
= val
& 0xFF000000;
445 case APIC_DESTINATION_FORMAT
:
446 newVal
= val
| 0x0FFFFFFF;
448 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
449 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
450 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
452 warn("Focus processor checking not implemented.\n");
454 case APIC_ERROR_STATUS
:
456 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
457 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
460 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
466 case APIC_INTERRUPT_COMMAND_LOW
:
468 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
469 // Check if we're already sending an IPI.
470 if (low
.deliveryStatus
) {
475 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
476 TriggerIntMessage message
= 0;
477 message
.destination
= high
.destination
;
478 message
.vector
= low
.vector
;
479 message
.deliveryMode
= low
.deliveryMode
;
480 message
.destMode
= low
.destMode
;
481 message
.level
= low
.level
;
482 message
.trigger
= low
.trigger
;
483 std::list
<int> apics
;
484 int numContexts
= sys
->numContexts();
485 switch (low
.destShorthand
) {
487 if (message
.deliveryMode
== DeliveryMode::LowestPriority
) {
488 panic("Lowest priority delivery mode "
489 "IPIs aren't implemented.\n");
491 if (message
.destMode
== 1) {
492 int dest
= message
.destination
;
493 hack_once("Assuming logical destinations are 1 << id.\n");
494 for (int i
= 0; i
< numContexts
; i
++) {
500 if (message
.destination
== 0xFF) {
501 for (int i
= 0; i
< numContexts
; i
++) {
502 if (i
== initialApicId
) {
503 requestInterrupt(message
.vector
,
504 message
.deliveryMode
, message
.trigger
);
510 if (message
.destination
== initialApicId
) {
511 requestInterrupt(message
.vector
,
512 message
.deliveryMode
, message
.trigger
);
514 apics
.push_back(message
.destination
);
521 requestInterrupt(message
.vector
,
522 message
.deliveryMode
, message
.trigger
);
525 requestInterrupt(message
.vector
,
526 message
.deliveryMode
, message
.trigger
);
530 for (int i
= 0; i
< numContexts
; i
++) {
531 if (i
!= initialApicId
) {
538 // Record that an IPI is being sent if one actually is.
540 low
.deliveryStatus
= 1;
541 pendingIPIs
+= apics
.size();
543 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
544 for (auto id
: apics
) {
545 PacketPtr pkt
= buildIntTriggerPacket(id
, message
);
546 intMasterPort
.sendMessage(pkt
, sys
->isTimingMode(),
547 [this](PacketPtr pkt
) { completeIPI(pkt
); });
549 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
553 case APIC_LVT_THERMAL_SENSOR
:
554 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
559 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
560 newVal
= (val
& ~readOnlyMask
) |
561 (regs
[reg
] & readOnlyMask
);
564 case APIC_INITIAL_COUNT
:
566 newVal
= bits(val
, 31, 0);
567 // Compute how many timer ticks we're being programmed for.
568 uint64_t newCount
= newVal
*
569 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
570 // Schedule on the edge of the next tick plus the new count.
571 Tick offset
= curTick() % clockPeriod();
573 reschedule(apicTimerEvent
,
574 curTick() + (newCount
+ 1) *
575 clockPeriod() - offset
, true);
578 reschedule(apicTimerEvent
,
579 curTick() + newCount
*
580 clockPeriod(), true);
584 case APIC_CURRENT_COUNT
:
585 //Local APIC Current Count register is read only.
587 case APIC_DIVIDE_CONFIGURATION
:
598 X86ISA::Interrupts::Interrupts(Params
* p
)
599 : BaseInterrupts(p
), sys(p
->system
), clockDomain(*p
->clk_domain
),
600 apicTimerEvent([this]{ processApicTimerEvent(); }, name()),
601 pendingSmi(false), smiVector(0),
602 pendingNmi(false), nmiVector(0),
603 pendingExtInt(false), extIntVector(0),
604 pendingInit(false), initVector(0),
605 pendingStartup(false), startupVector(0),
606 startedUp(false), pendingUnmaskableInt(false),
607 pendingIPIs(0), cpu(NULL
),
608 intSlavePort(name() + ".int_slave", this, this),
609 intMasterPort(name() + ".int_master", this, this, p
->int_latency
),
610 pioPort(this), pioDelay(p
->pio_latency
)
612 memset(regs
, 0, sizeof(regs
));
613 //Set the local apic DFR to the flat model.
614 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
618 regs
[APIC_VERSION
] = (5 << 16) | 0x14;
623 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
625 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
626 if (pendingUnmaskableInt
) {
627 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
632 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
635 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
636 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
637 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
645 X86ISA::Interrupts::checkInterruptsRaw() const
647 return pendingUnmaskableInt
|| pendingExtInt
||
648 (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
649 bits(regs
[APIC_TASK_PRIORITY
], 7, 4));
653 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
655 assert(checkInterrupts(tc
));
656 // These are all probably fairly uncommon, so we'll make them easier to
658 if (pendingUnmaskableInt
) {
660 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
661 return std::make_shared
<SystemManagementInterrupt
>();
662 } else if (pendingNmi
) {
663 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
664 return std::make_shared
<NonMaskableInterrupt
>(nmiVector
);
665 } else if (pendingInit
) {
666 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
667 return std::make_shared
<InitInterrupt
>(initVector
);
668 } else if (pendingStartup
) {
669 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
670 return std::make_shared
<StartupInterrupt
>(startupVector
);
672 panic("pendingUnmaskableInt set, but no unmaskable "
673 "ints were pending.\n");
676 } else if (pendingExtInt
) {
677 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
678 return std::make_shared
<ExternalInterrupt
>(extIntVector
);
680 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
681 // The only thing left are fixed and lowest priority interrupts.
682 return std::make_shared
<ExternalInterrupt
>(IRRV
);
687 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
689 assert(checkInterrupts(tc
));
690 if (pendingUnmaskableInt
) {
692 DPRINTF(LocalApic
, "SMI sent to core.\n");
694 } else if (pendingNmi
) {
695 DPRINTF(LocalApic
, "NMI sent to core.\n");
697 } else if (pendingInit
) {
698 DPRINTF(LocalApic
, "Init sent to core.\n");
701 } else if (pendingStartup
) {
702 DPRINTF(LocalApic
, "SIPI sent to core.\n");
703 pendingStartup
= false;
706 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
707 pendingUnmaskableInt
= false;
708 } else if (pendingExtInt
) {
709 pendingExtInt
= false;
711 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
712 // Mark the interrupt as "in service".
714 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
715 // Clear it out of the IRR.
716 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
722 X86ISA::Interrupts::serialize(CheckpointOut
&cp
) const
724 SERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
725 SERIALIZE_SCALAR(pendingSmi
);
726 SERIALIZE_SCALAR(smiVector
);
727 SERIALIZE_SCALAR(pendingNmi
);
728 SERIALIZE_SCALAR(nmiVector
);
729 SERIALIZE_SCALAR(pendingExtInt
);
730 SERIALIZE_SCALAR(extIntVector
);
731 SERIALIZE_SCALAR(pendingInit
);
732 SERIALIZE_SCALAR(initVector
);
733 SERIALIZE_SCALAR(pendingStartup
);
734 SERIALIZE_SCALAR(startupVector
);
735 SERIALIZE_SCALAR(startedUp
);
736 SERIALIZE_SCALAR(pendingUnmaskableInt
);
737 SERIALIZE_SCALAR(pendingIPIs
);
738 SERIALIZE_SCALAR(IRRV
);
739 SERIALIZE_SCALAR(ISRV
);
740 bool apicTimerEventScheduled
= apicTimerEvent
.scheduled();
741 SERIALIZE_SCALAR(apicTimerEventScheduled
);
742 Tick apicTimerEventTick
= apicTimerEvent
.when();
743 SERIALIZE_SCALAR(apicTimerEventTick
);
747 X86ISA::Interrupts::unserialize(CheckpointIn
&cp
)
749 UNSERIALIZE_ARRAY(regs
, NUM_APIC_REGS
);
750 UNSERIALIZE_SCALAR(pendingSmi
);
751 UNSERIALIZE_SCALAR(smiVector
);
752 UNSERIALIZE_SCALAR(pendingNmi
);
753 UNSERIALIZE_SCALAR(nmiVector
);
754 UNSERIALIZE_SCALAR(pendingExtInt
);
755 UNSERIALIZE_SCALAR(extIntVector
);
756 UNSERIALIZE_SCALAR(pendingInit
);
757 UNSERIALIZE_SCALAR(initVector
);
758 UNSERIALIZE_SCALAR(pendingStartup
);
759 UNSERIALIZE_SCALAR(startupVector
);
760 UNSERIALIZE_SCALAR(startedUp
);
761 UNSERIALIZE_SCALAR(pendingUnmaskableInt
);
762 UNSERIALIZE_SCALAR(pendingIPIs
);
763 UNSERIALIZE_SCALAR(IRRV
);
764 UNSERIALIZE_SCALAR(ISRV
);
765 bool apicTimerEventScheduled
;
766 UNSERIALIZE_SCALAR(apicTimerEventScheduled
);
767 if (apicTimerEventScheduled
) {
768 Tick apicTimerEventTick
;
769 UNSERIALIZE_SCALAR(apicTimerEventTick
);
770 if (apicTimerEvent
.scheduled()) {
771 reschedule(apicTimerEvent
, apicTimerEventTick
, true);
773 schedule(apicTimerEvent
, apicTimerEventTick
);
779 X86LocalApicParams::create()
781 return new X86ISA::Interrupts(this);
785 X86ISA::Interrupts::processApicTimerEvent() {
786 if (triggerTimerInterrupt())
787 setReg(APIC_INITIAL_COUNT
, readReg(APIC_INITIAL_COUNT
));