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58 #include "arch/x86/apicregs.hh"
59 #include "arch/x86/interrupts.hh"
60 #include "arch/x86/intmessage.hh"
61 #include "cpu/base.hh"
62 #include "mem/packet_access.hh"
65 divideFromConf(uint32_t conf
)
67 // This figures out what division we want from the division configuration
68 // register in the local APIC. The encoding is a little odd but it can
69 // be deciphered fairly easily.
70 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
71 shift
= (shift
+ 1) % 8;
79 decodeAddr(Addr paddr
)
89 regNum
= APIC_VERSION
;
92 regNum
= APIC_TASK_PRIORITY
;
95 regNum
= APIC_ARBITRATION_PRIORITY
;
98 regNum
= APIC_PROCESSOR_PRIORITY
;
104 regNum
= APIC_LOGICAL_DESTINATION
;
107 regNum
= APIC_DESTINATION_FORMAT
;
110 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
128 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x8);
146 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x8);
164 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x8);
167 regNum
= APIC_ERROR_STATUS
;
170 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
173 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
176 regNum
= APIC_LVT_TIMER
;
179 regNum
= APIC_LVT_THERMAL_SENSOR
;
182 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
185 regNum
= APIC_LVT_LINT0
;
188 regNum
= APIC_LVT_LINT1
;
191 regNum
= APIC_LVT_ERROR
;
194 regNum
= APIC_INITIAL_COUNT
;
197 regNum
= APIC_CURRENT_COUNT
;
200 regNum
= APIC_DIVIDE_CONFIGURATION
;
203 // A reserved register field.
204 panic("Accessed reserved register field %#x.\n", paddr
);
212 X86ISA::Interrupts::read(PacketPtr pkt
)
214 Addr offset
= pkt
->getAddr() - pioAddr
;
215 //Make sure we're at least only accessing one register.
216 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
217 panic("Accessed more than one register at a time in the APIC!\n");
218 ApicRegIndex reg
= decodeAddr(offset
);
219 uint32_t val
= htog(readReg(reg
));
221 "Reading Local APIC register %d at offset %#x as %#x.\n",
223 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
228 X86ISA::Interrupts::write(PacketPtr pkt
)
230 Addr offset
= pkt
->getAddr() - pioAddr
;
231 //Make sure we're at least only accessing one register.
232 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
233 panic("Accessed more than one register at a time in the APIC!\n");
234 ApicRegIndex reg
= decodeAddr(offset
);
235 uint32_t val
= regs
[reg
];
236 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
238 "Writing Local APIC register %d at offset %#x as %#x.\n",
239 reg
, offset
, gtoh(val
));
240 setReg(reg
, gtoh(val
));
245 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
248 Addr offset
= pkt
->getAddr() - x86InterruptAddress(id
, 0);
249 assert(pkt
->cmd
== MemCmd::MessageReq
);
254 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
255 uint8_t vector
= message
.vector
;
257 "Got Trigger Interrupt message with vector %#x.\n",
259 // Make sure we're really supposed to get this.
260 assert((message
.destMode
== 0 && message
.destination
== id
) ||
261 (bits((int)message
.destination
, id
)));
264 * Fixed and lowest-priority delivery mode interrupts are handled
265 * using the IRR/ISR registers, checking against the TPR, etc.
266 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
268 if (message
.deliveryMode
== DeliveryMode::Fixed
||
269 message
.deliveryMode
== DeliveryMode::LowestPriority
) {
270 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
271 DeliveryMode::names
[message
.deliveryMode
]);
272 // Queue up the interrupt in the IRR.
275 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
276 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
277 if (message
.trigger
) {
279 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
282 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
285 } else if (!DeliveryMode::isReserved(message
.deliveryMode
)) {
286 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
287 DeliveryMode::names
[message
.deliveryMode
]);
288 if (message
.deliveryMode
== DeliveryMode::SMI
&&
290 pendingUnmaskableInt
= pendingSmi
= true;
291 smiMessage
= message
;
292 } else if (message
.deliveryMode
== DeliveryMode::NMI
&&
294 pendingUnmaskableInt
= pendingNmi
= true;
295 nmiMessage
= message
;
296 } else if (message
.deliveryMode
== DeliveryMode::ExtInt
&&
298 pendingExtInt
= true;
299 extIntMessage
= message
;
300 } else if (message
.deliveryMode
== DeliveryMode::INIT
&&
302 pendingUnmaskableInt
= pendingInit
= true;
303 initMessage
= message
;
309 panic("Local apic got unknown interrupt message at offset %#x.\n",
320 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
322 if (reg
>= APIC_TRIGGER_MODE(0) &&
323 reg
<= APIC_TRIGGER_MODE(15)) {
324 panic("Local APIC Trigger Mode registers are unimplemented.\n");
327 case APIC_ARBITRATION_PRIORITY
:
328 panic("Local APIC Arbitration Priority register unimplemented.\n");
330 case APIC_PROCESSOR_PRIORITY
:
331 panic("Local APIC Processor Priority register unimplemented.\n");
333 case APIC_ERROR_STATUS
:
334 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
336 case APIC_INTERRUPT_COMMAND_LOW
:
337 panic("Local APIC Interrupt Command low"
338 " register unimplemented.\n");
340 case APIC_INTERRUPT_COMMAND_HIGH
:
341 panic("Local APIC Interrupt Command high"
342 " register unimplemented.\n");
344 case APIC_CURRENT_COUNT
:
347 uint32_t val
= regs
[reg
] - curTick
/ clock
;
348 val
/= (16 * divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
358 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
360 uint32_t newVal
= val
;
361 if (reg
>= APIC_IN_SERVICE(0) &&
362 reg
<= APIC_IN_SERVICE(15)) {
363 panic("Local APIC In-Service registers are unimplemented.\n");
365 if (reg
>= APIC_TRIGGER_MODE(0) &&
366 reg
<= APIC_TRIGGER_MODE(15)) {
367 panic("Local APIC Trigger Mode registers are unimplemented.\n");
369 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
370 reg
<= APIC_INTERRUPT_REQUEST(15)) {
371 panic("Local APIC Interrupt Request registers "
372 "are unimplemented.\n");
379 // The Local APIC Version register is read only.
381 case APIC_TASK_PRIORITY
:
384 case APIC_ARBITRATION_PRIORITY
:
385 panic("Local APIC Arbitration Priority register unimplemented.\n");
387 case APIC_PROCESSOR_PRIORITY
:
388 panic("Local APIC Processor Priority register unimplemented.\n");
391 // Remove the interrupt that just completed from the local apic state.
392 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
395 case APIC_LOGICAL_DESTINATION
:
396 newVal
= val
& 0xFF000000;
398 case APIC_DESTINATION_FORMAT
:
399 newVal
= val
| 0x0FFFFFFF;
401 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
402 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
403 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
405 warn("Focus processor checking not implemented.\n");
407 case APIC_ERROR_STATUS
:
409 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
410 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
413 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
419 case APIC_INTERRUPT_COMMAND_LOW
:
420 panic("Local APIC Interrupt Command low"
421 " register unimplemented.\n");
423 case APIC_INTERRUPT_COMMAND_HIGH
:
424 panic("Local APIC Interrupt Command high"
425 " register unimplemented.\n");
428 case APIC_LVT_THERMAL_SENSOR
:
429 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
434 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
435 newVal
= (val
& ~readOnlyMask
) |
436 (regs
[reg
] & readOnlyMask
);
439 case APIC_INITIAL_COUNT
:
442 newVal
= bits(val
, 31, 0);
443 uint32_t newCount
= newVal
*
444 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]) * 16);
445 regs
[APIC_CURRENT_COUNT
] = newCount
+ curTick
/ clock
;
446 // Find out how long a "tick" of the timer should take.
447 Tick timerTick
= 16 * clock
;
448 // Schedule on the edge of the next tick plus the new count.
449 Tick offset
= curTick
% timerTick
;
451 reschedule(apicTimerEvent
,
452 curTick
+ (newCount
+ 1) * timerTick
- offset
, true);
454 reschedule(apicTimerEvent
,
455 curTick
+ newCount
* timerTick
, true);
459 case APIC_CURRENT_COUNT
:
460 //Local APIC Current Count register is read only.
462 case APIC_DIVIDE_CONFIGURATION
:
473 X86ISA::Interrupts::check_interrupts(ThreadContext
* tc
) const
475 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
476 if (pendingUnmaskableInt
) {
477 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
482 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
485 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
486 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
487 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
495 X86ISA::Interrupts::getInterrupt(ThreadContext
* tc
)
497 assert(check_interrupts(tc
));
498 // These are all probably fairly uncommon, so we'll make them easier to
500 if (pendingUnmaskableInt
) {
502 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
503 return new SystemManagementInterrupt();
504 } else if (pendingNmi
) {
505 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
506 return new NonMaskableInterrupt(nmiMessage
.vector
);
507 } else if (pendingInit
) {
508 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
509 return new InitInterrupt(initMessage
.vector
);
511 panic("pendingUnmaskableInt set, but no unmaskable "
512 "ints were pending.\n");
515 } else if (pendingExtInt
) {
516 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
517 return new ExternalInterrupt(extIntMessage
.vector
);
519 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
520 // The only thing left are fixed and lowest priority interrupts.
521 return new ExternalInterrupt(IRRV
);
526 X86ISA::Interrupts::updateIntrInfo(ThreadContext
* tc
)
528 assert(check_interrupts(tc
));
529 if (pendingUnmaskableInt
) {
531 DPRINTF(LocalApic
, "SMI sent to core.\n");
533 } else if (pendingNmi
) {
534 DPRINTF(LocalApic
, "NMI sent to core.\n");
536 } else if (pendingInit
) {
537 DPRINTF(LocalApic
, "Init sent to core.\n");
540 if (!(pendingSmi
|| pendingNmi
|| pendingInit
))
541 pendingUnmaskableInt
= false;
542 } else if (pendingExtInt
) {
543 pendingExtInt
= false;
545 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
546 // Mark the interrupt as "in service".
548 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
549 // Clear it out of the IRR.
550 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
556 X86LocalApicParams::create()
558 return new X86ISA::Interrupts(this);