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58 #include "arch/x86/apicregs.hh"
59 #include "arch/x86/interrupts.hh"
60 #include "arch/x86/intmessage.hh"
61 #include "cpu/base.hh"
62 #include "mem/packet_access.hh"
63 #include "sim/system.hh"
66 divideFromConf(uint32_t conf
)
68 // This figures out what division we want from the division configuration
69 // register in the local APIC. The encoding is a little odd but it can
70 // be deciphered fairly easily.
71 int shift
= ((conf
& 0x8) >> 1) | (conf
& 0x3);
72 shift
= (shift
+ 1) % 8;
80 decodeAddr(Addr paddr
)
90 regNum
= APIC_VERSION
;
93 regNum
= APIC_TASK_PRIORITY
;
96 regNum
= APIC_ARBITRATION_PRIORITY
;
99 regNum
= APIC_PROCESSOR_PRIORITY
;
105 regNum
= APIC_LOGICAL_DESTINATION
;
108 regNum
= APIC_DESTINATION_FORMAT
;
111 regNum
= APIC_SPURIOUS_INTERRUPT_VECTOR
;
129 regNum
= APIC_IN_SERVICE((paddr
- 0x100) / 0x8);
147 regNum
= APIC_TRIGGER_MODE((paddr
- 0x180) / 0x8);
165 regNum
= APIC_INTERRUPT_REQUEST((paddr
- 0x200) / 0x8);
168 regNum
= APIC_ERROR_STATUS
;
171 regNum
= APIC_INTERRUPT_COMMAND_LOW
;
174 regNum
= APIC_INTERRUPT_COMMAND_HIGH
;
177 regNum
= APIC_LVT_TIMER
;
180 regNum
= APIC_LVT_THERMAL_SENSOR
;
183 regNum
= APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
;
186 regNum
= APIC_LVT_LINT0
;
189 regNum
= APIC_LVT_LINT1
;
192 regNum
= APIC_LVT_ERROR
;
195 regNum
= APIC_INITIAL_COUNT
;
198 regNum
= APIC_CURRENT_COUNT
;
201 regNum
= APIC_DIVIDE_CONFIGURATION
;
204 // A reserved register field.
205 panic("Accessed reserved register field %#x.\n", paddr
);
213 X86ISA::Interrupts::read(PacketPtr pkt
)
215 Addr offset
= pkt
->getAddr() - pioAddr
;
216 //Make sure we're at least only accessing one register.
217 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
218 panic("Accessed more than one register at a time in the APIC!\n");
219 ApicRegIndex reg
= decodeAddr(offset
);
220 uint32_t val
= htog(readReg(reg
));
222 "Reading Local APIC register %d at offset %#x as %#x.\n",
224 pkt
->setData(((uint8_t *)&val
) + (offset
& mask(3)));
225 pkt
->makeAtomicResponse();
230 X86ISA::Interrupts::write(PacketPtr pkt
)
232 Addr offset
= pkt
->getAddr() - pioAddr
;
233 //Make sure we're at least only accessing one register.
234 if ((offset
& ~mask(3)) != ((offset
+ pkt
->getSize()) & ~mask(3)))
235 panic("Accessed more than one register at a time in the APIC!\n");
236 ApicRegIndex reg
= decodeAddr(offset
);
237 uint32_t val
= regs
[reg
];
238 pkt
->writeData(((uint8_t *)&val
) + (offset
& mask(3)));
240 "Writing Local APIC register %d at offset %#x as %#x.\n",
241 reg
, offset
, gtoh(val
));
242 setReg(reg
, gtoh(val
));
243 pkt
->makeAtomicResponse();
247 X86ISA::Interrupts::requestInterrupt(uint8_t vector
,
248 uint8_t deliveryMode
, bool level
)
251 * Fixed and lowest-priority delivery mode interrupts are handled
252 * using the IRR/ISR registers, checking against the TPR, etc.
253 * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
255 if (deliveryMode
== DeliveryMode::Fixed
||
256 deliveryMode
== DeliveryMode::LowestPriority
) {
257 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
258 DeliveryMode::names
[deliveryMode
]);
259 // Queue up the interrupt in the IRR.
262 if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
)) {
263 setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, vector
);
265 setRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
267 clearRegArrayBit(APIC_TRIGGER_MODE_BASE
, vector
);
270 } else if (!DeliveryMode::isReserved(deliveryMode
)) {
271 DPRINTF(LocalApic
, "Interrupt is an %s.\n",
272 DeliveryMode::names
[deliveryMode
]);
273 if (deliveryMode
== DeliveryMode::SMI
&& !pendingSmi
) {
274 pendingUnmaskableInt
= pendingSmi
= true;
276 } else if (deliveryMode
== DeliveryMode::NMI
&& !pendingNmi
) {
277 pendingUnmaskableInt
= pendingNmi
= true;
279 } else if (deliveryMode
== DeliveryMode::ExtInt
&& !pendingExtInt
) {
280 pendingExtInt
= true;
281 extIntVector
= vector
;
282 } else if (deliveryMode
== DeliveryMode::INIT
&& !pendingInit
) {
283 pendingUnmaskableInt
= pendingInit
= true;
285 } else if (deliveryMode
== DeliveryMode::SIPI
&&
286 !pendingStartup
&& !startedUp
) {
287 pendingUnmaskableInt
= pendingStartup
= true;
288 startupVector
= vector
;
296 X86ISA::Interrupts::setCPU(BaseCPU
* newCPU
)
299 if (cpu
!= NULL
&& cpu
->cpuId() != newCPU
->cpuId()) {
300 panic("Local APICs can't be moved between CPUs"
301 " with different IDs.\n");
304 initialApicId
= cpu
->cpuId();
305 regs
[APIC_ID
] = (initialApicId
<< 24);
310 X86ISA::Interrupts::recvMessage(PacketPtr pkt
)
312 Addr offset
= pkt
->getAddr() - x86InterruptAddress(initialApicId
, 0);
313 assert(pkt
->cmd
== MemCmd::MessageReq
);
318 TriggerIntMessage message
= pkt
->get
<TriggerIntMessage
>();
320 "Got Trigger Interrupt message with vector %#x.\n",
323 requestInterrupt(message
.vector
,
324 message
.deliveryMode
, message
.trigger
);
328 panic("Local apic got unknown interrupt message at offset %#x.\n",
332 pkt
->makeAtomicResponse();
338 X86ISA::Interrupts::recvResponse(PacketPtr pkt
)
340 assert(!pkt
->isError());
341 assert(pkt
->cmd
== MemCmd::MessageResp
);
342 if (--pendingIPIs
== 0) {
343 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
344 // Record that the ICR is now idle.
345 low
.deliveryStatus
= 0;
346 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
350 DPRINTF(LocalApic
, "ICR is now idle.\n");
356 X86ISA::Interrupts::addressRanges(AddrRangeList
&range_list
)
359 Range
<Addr
> range
= RangeEx(x86LocalAPICAddress(initialApicId
, 0),
360 x86LocalAPICAddress(initialApicId
, 0) +
362 range_list
.push_back(range
);
363 pioAddr
= range
.start
;
368 X86ISA::Interrupts::getIntAddrRange(AddrRangeList
&range_list
)
371 range_list
.push_back(RangeEx(x86InterruptAddress(initialApicId
, 0),
372 x86InterruptAddress(initialApicId
, 0) +
373 PhysAddrAPICRangeSize
));
378 X86ISA::Interrupts::readReg(ApicRegIndex reg
)
380 if (reg
>= APIC_TRIGGER_MODE(0) &&
381 reg
<= APIC_TRIGGER_MODE(15)) {
382 panic("Local APIC Trigger Mode registers are unimplemented.\n");
385 case APIC_ARBITRATION_PRIORITY
:
386 panic("Local APIC Arbitration Priority register unimplemented.\n");
388 case APIC_PROCESSOR_PRIORITY
:
389 panic("Local APIC Processor Priority register unimplemented.\n");
391 case APIC_ERROR_STATUS
:
392 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
394 case APIC_CURRENT_COUNT
:
396 if (apicTimerEvent
.scheduled()) {
398 // Compute how many m5 ticks happen per count.
399 uint64_t ticksPerCount
= clock
*
400 divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]);
401 // Compute how many m5 ticks are left.
402 uint64_t val
= apicTimerEvent
.when() - curTick
;
403 // Turn that into a count.
404 val
= (val
+ ticksPerCount
- 1) / ticksPerCount
;
417 X86ISA::Interrupts::setReg(ApicRegIndex reg
, uint32_t val
)
419 uint32_t newVal
= val
;
420 if (reg
>= APIC_IN_SERVICE(0) &&
421 reg
<= APIC_IN_SERVICE(15)) {
422 panic("Local APIC In-Service registers are unimplemented.\n");
424 if (reg
>= APIC_TRIGGER_MODE(0) &&
425 reg
<= APIC_TRIGGER_MODE(15)) {
426 panic("Local APIC Trigger Mode registers are unimplemented.\n");
428 if (reg
>= APIC_INTERRUPT_REQUEST(0) &&
429 reg
<= APIC_INTERRUPT_REQUEST(15)) {
430 panic("Local APIC Interrupt Request registers "
431 "are unimplemented.\n");
438 // The Local APIC Version register is read only.
440 case APIC_TASK_PRIORITY
:
443 case APIC_ARBITRATION_PRIORITY
:
444 panic("Local APIC Arbitration Priority register unimplemented.\n");
446 case APIC_PROCESSOR_PRIORITY
:
447 panic("Local APIC Processor Priority register unimplemented.\n");
450 // Remove the interrupt that just completed from the local apic state.
451 clearRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
454 case APIC_LOGICAL_DESTINATION
:
455 newVal
= val
& 0xFF000000;
457 case APIC_DESTINATION_FORMAT
:
458 newVal
= val
| 0x0FFFFFFF;
460 case APIC_SPURIOUS_INTERRUPT_VECTOR
:
461 regs
[APIC_INTERNAL_STATE
] &= ~ULL(1 << 1);
462 regs
[APIC_INTERNAL_STATE
] |= val
& (1 << 8);
464 warn("Focus processor checking not implemented.\n");
466 case APIC_ERROR_STATUS
:
468 if (regs
[APIC_INTERNAL_STATE
] & 0x1) {
469 regs
[APIC_INTERNAL_STATE
] &= ~ULL(0x1);
472 regs
[APIC_INTERNAL_STATE
] |= ULL(0x1);
478 case APIC_INTERRUPT_COMMAND_LOW
:
480 InterruptCommandRegLow low
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
481 // Check if we're already sending an IPI.
482 if (low
.deliveryStatus
) {
487 InterruptCommandRegHigh high
= regs
[APIC_INTERRUPT_COMMAND_HIGH
];
488 // Record that an IPI is being sent.
489 low
.deliveryStatus
= 1;
490 TriggerIntMessage message
;
491 message
.destination
= high
.destination
;
492 message
.vector
= low
.vector
;
493 message
.deliveryMode
= low
.deliveryMode
;
494 message
.destMode
= low
.destMode
;
495 message
.level
= low
.level
;
496 message
.trigger
= low
.trigger
;
497 bool timing
= sys
->getMemoryMode() == Enums::timing
;
498 // Be careful no updates of the delivery status bit get lost.
499 regs
[APIC_INTERRUPT_COMMAND_LOW
] = low
;
500 switch (low
.destShorthand
) {
503 intPort
->sendMessage(message
, timing
);
504 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
508 requestInterrupt(message
.vector
,
509 message
.deliveryMode
, message
.trigger
);
512 requestInterrupt(message
.vector
,
513 message
.deliveryMode
, message
.trigger
);
517 int numContexts
= sys
->numContexts();
518 pendingIPIs
+= (numContexts
- 1);
519 for (int i
= 0; i
< numContexts
; i
++) {
520 int thisId
= sys
->getThreadContext(i
)->contextId();
521 if (thisId
!= initialApicId
) {
522 PacketPtr pkt
= buildIntRequest(thisId
, message
);
524 intPort
->sendMessageTiming(pkt
, latency
);
526 intPort
->sendMessageAtomic(pkt
);
530 newVal
= regs
[APIC_INTERRUPT_COMMAND_LOW
];
536 case APIC_LVT_THERMAL_SENSOR
:
537 case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS
:
542 uint64_t readOnlyMask
= (1 << 12) | (1 << 14);
543 newVal
= (val
& ~readOnlyMask
) |
544 (regs
[reg
] & readOnlyMask
);
547 case APIC_INITIAL_COUNT
:
550 newVal
= bits(val
, 31, 0);
551 // Compute how many timer ticks we're being programmed for.
552 uint64_t newCount
= newVal
*
553 (divideFromConf(regs
[APIC_DIVIDE_CONFIGURATION
]));
554 // Schedule on the edge of the next tick plus the new count.
555 Tick offset
= curTick
% clock
;
557 reschedule(apicTimerEvent
,
558 curTick
+ (newCount
+ 1) * clock
- offset
, true);
560 reschedule(apicTimerEvent
,
561 curTick
+ newCount
* clock
, true);
565 case APIC_CURRENT_COUNT
:
566 //Local APIC Current Count register is read only.
568 case APIC_DIVIDE_CONFIGURATION
:
579 X86ISA::Interrupts::Interrupts(Params
* p
) :
580 BasicPioDevice(p
), IntDev(this), latency(p
->pio_latency
), clock(0),
581 apicTimerEvent(this),
582 pendingSmi(false), smiVector(0),
583 pendingNmi(false), nmiVector(0),
584 pendingExtInt(false), extIntVector(0),
585 pendingInit(false), initVector(0),
586 pendingStartup(false), startupVector(0),
587 startedUp(false), pendingUnmaskableInt(false),
588 pendingIPIs(0), cpu(NULL
)
591 memset(regs
, 0, sizeof(regs
));
592 //Set the local apic DFR to the flat model.
593 regs
[APIC_DESTINATION_FORMAT
] = (uint32_t)(-1);
600 X86ISA::Interrupts::checkInterrupts(ThreadContext
*tc
) const
602 RFLAGS rflags
= tc
->readMiscRegNoEffect(MISCREG_RFLAGS
);
603 if (pendingUnmaskableInt
) {
604 DPRINTF(LocalApic
, "Reported pending unmaskable interrupt.\n");
609 DPRINTF(LocalApic
, "Reported pending external interrupt.\n");
612 if (IRRV
> ISRV
&& bits(IRRV
, 7, 4) >
613 bits(regs
[APIC_TASK_PRIORITY
], 7, 4)) {
614 DPRINTF(LocalApic
, "Reported pending regular interrupt.\n");
622 X86ISA::Interrupts::getInterrupt(ThreadContext
*tc
)
624 assert(checkInterrupts(tc
));
625 // These are all probably fairly uncommon, so we'll make them easier to
627 if (pendingUnmaskableInt
) {
629 DPRINTF(LocalApic
, "Generated SMI fault object.\n");
630 return new SystemManagementInterrupt();
631 } else if (pendingNmi
) {
632 DPRINTF(LocalApic
, "Generated NMI fault object.\n");
633 return new NonMaskableInterrupt(nmiVector
);
634 } else if (pendingInit
) {
635 DPRINTF(LocalApic
, "Generated INIT fault object.\n");
636 return new InitInterrupt(initVector
);
637 } else if (pendingStartup
) {
638 DPRINTF(LocalApic
, "Generating SIPI fault object.\n");
639 return new StartupInterrupt(startupVector
);
641 panic("pendingUnmaskableInt set, but no unmaskable "
642 "ints were pending.\n");
645 } else if (pendingExtInt
) {
646 DPRINTF(LocalApic
, "Generated external interrupt fault object.\n");
647 return new ExternalInterrupt(extIntVector
);
649 DPRINTF(LocalApic
, "Generated regular interrupt fault object.\n");
650 // The only thing left are fixed and lowest priority interrupts.
651 return new ExternalInterrupt(IRRV
);
656 X86ISA::Interrupts::updateIntrInfo(ThreadContext
*tc
)
658 assert(checkInterrupts(tc
));
659 if (pendingUnmaskableInt
) {
661 DPRINTF(LocalApic
, "SMI sent to core.\n");
663 } else if (pendingNmi
) {
664 DPRINTF(LocalApic
, "NMI sent to core.\n");
666 } else if (pendingInit
) {
667 DPRINTF(LocalApic
, "Init sent to core.\n");
670 } else if (pendingStartup
) {
671 DPRINTF(LocalApic
, "SIPI sent to core.\n");
672 pendingStartup
= false;
675 if (!(pendingSmi
|| pendingNmi
|| pendingInit
|| pendingStartup
))
676 pendingUnmaskableInt
= false;
677 } else if (pendingExtInt
) {
678 pendingExtInt
= false;
680 DPRINTF(LocalApic
, "Interrupt %d sent to core.\n", IRRV
);
681 // Mark the interrupt as "in service".
683 setRegArrayBit(APIC_IN_SERVICE_BASE
, ISRV
);
684 // Clear it out of the IRR.
685 clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE
, IRRV
);
691 X86LocalApicParams::create()
693 return new X86ISA::Interrupts(this);