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40 #ifndef __ARCH_X86_INTERRUPTS_HH__
41 #define __ARCH_X86_INTERRUPTS_HH__
43 #include "arch/x86/faults.hh"
44 #include "arch/x86/intmessage.hh"
45 #include "arch/x86/regs/apic.hh"
46 #include "base/bitfield.hh"
47 #include "cpu/thread_context.hh"
48 #include "dev/io_device.hh"
49 #include "dev/x86/intdev.hh"
50 #include "params/X86LocalApic.hh"
51 #include "sim/eventq.hh"
58 class Interrupts : public BasicPioDevice, IntDev
61 // Storage for the APIC registers
62 uint32_t regs[NUM_APIC_REGS];
65 Bitfield<7, 0> vector;
66 Bitfield<10, 8> deliveryMode;
68 Bitfield<13> polarity;
69 Bitfield<14> remoteIRR;
72 Bitfield<17> periodic;
76 * Timing related stuff.
81 class ApicTimerEvent : public Event
84 Interrupts *localApic;
86 ApicTimerEvent(Interrupts *_localApic) :
87 Event(), localApic(_localApic)
93 if (localApic->triggerTimerInterrupt()) {
94 localApic->setReg(APIC_INITIAL_COUNT,
95 localApic->readReg(APIC_INITIAL_COUNT));
100 ApicTimerEvent apicTimerEvent;
103 * A set of variables to keep track of interrupts that don't go through
111 uint8_t extIntVector;
115 uint8_t startupVector;
118 // This is a quick check whether any of the above (except ExtInt) are set.
119 bool pendingUnmaskableInt;
121 // A count of how many IPIs are in flight.
125 * IRR and ISR maintenance.
131 findRegArrayMSB(ApicRegIndex base)
135 if (regs[base + offset] != 0) {
136 return offset * 32 + findMsbSet(regs[base + offset]);
145 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
151 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
155 setRegArrayBit(ApicRegIndex base, uint8_t vector)
157 regs[base + (vector / 32)] |= (1 << (vector % 32));
161 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
163 regs[base + (vector / 32)] &= ~(1 << (vector % 32));
167 getRegArrayBit(ApicRegIndex base, uint8_t vector)
169 return bits(regs[base + (vector / 32)], vector % 5);
172 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
182 typedef X86LocalApicParams Params;
184 void setCPU(BaseCPU * newCPU);
187 setClock(Tick newClock)
195 return dynamic_cast<const Params *>(_params);
199 * Initialize this object by registering it with the IO APIC.
204 * Functions to interact with the interrupt port from IntDev.
206 Tick read(PacketPtr pkt);
207 Tick write(PacketPtr pkt);
208 Tick recvMessage(PacketPtr pkt);
209 Tick recvResponse(PacketPtr pkt);
212 triggerTimerInterrupt()
214 LVTEntry entry = regs[APIC_LVT_TIMER];
216 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
217 return entry.periodic;
220 void addressRanges(AddrRangeList &range_list);
221 void getIntAddrRange(AddrRangeList &range_list);
223 Port *getPort(const std::string &if_name, int idx = -1)
225 if (if_name == "int_port")
227 return BasicPioDevice::getPort(if_name, idx);
231 * Functions to access and manipulate the APIC's registers.
234 uint32_t readReg(ApicRegIndex miscReg);
235 void setReg(ApicRegIndex reg, uint32_t val);
237 setRegNoEffect(ApicRegIndex reg, uint32_t val)
246 Interrupts(Params * p);
249 * Functions for retrieving interrupts for the CPU to handle.
252 bool checkInterrupts(ThreadContext *tc) const;
253 Fault getInterrupt(ThreadContext *tc);
254 void updateIntrInfo(ThreadContext *tc);
261 serialize(std::ostream &os)
263 warn("Interrupts::serialize unimplemented!\n");
267 unserialize(Checkpoint *cp, const std::string §ion)
269 warn("Interrupts::unserialize unimplemented!\n");
273 * Old functions needed for compatability but which will be phased out
277 post(int int_num, int index)
279 panic("Interrupts::post unimplemented!\n");
283 clear(int int_num, int index)
285 panic("Interrupts::clear unimplemented!\n");
291 panic("Interrupts::clearAll unimplemented!\n");
295 } // namespace X86ISA
297 #endif // __ARCH_X86_INTERRUPTS_HH__