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58 #ifndef __ARCH_X86_INTERRUPTS_HH__
59 #define __ARCH_X86_INTERRUPTS_HH__
61 #include "arch/x86/apicregs.hh"
62 #include "arch/x86/faults.hh"
63 #include "arch/x86/intmessage.hh"
64 #include "base/bitfield.hh"
65 #include "cpu/thread_context.hh"
66 #include "dev/io_device.hh"
67 #include "dev/x86/intdev.hh"
68 #include "params/X86LocalApic.hh"
69 #include "sim/eventq.hh"
75 class Interrupts : public BasicPioDevice, IntDev
78 // Storage for the APIC registers
79 uint32_t regs[NUM_APIC_REGS];
82 Bitfield<7, 0> vector;
83 Bitfield<10, 8> deliveryMode;
85 Bitfield<13> polarity;
86 Bitfield<14> remoteIRR;
89 Bitfield<17> periodic;
93 * Timing related stuff.
98 class ApicTimerEvent : public Event
101 Interrupts *localApic;
103 ApicTimerEvent(Interrupts *_localApic) :
104 Event(), localApic(_localApic)
110 if (localApic->triggerTimerInterrupt()) {
111 localApic->setReg(APIC_INITIAL_COUNT,
112 localApic->readReg(APIC_INITIAL_COUNT));
117 ApicTimerEvent apicTimerEvent;
120 * A set of variables to keep track of interrupts that don't go through
128 uint8_t extIntVector;
132 // This is a quick check whether any of the above (except ExtInt) are set.
133 bool pendingUnmaskableInt;
136 * IRR and ISR maintenance.
142 findRegArrayMSB(ApicRegIndex base)
146 if (regs[base + offset] != 0) {
147 return offset * 32 + findMsbSet(regs[base + offset]);
156 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
162 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
166 setRegArrayBit(ApicRegIndex base, uint8_t vector)
168 regs[base + (vector % 32)] |= (1 << (vector >> 5));
172 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
174 regs[base + (vector % 32)] &= ~(1 << (vector >> 5));
178 getRegArrayBit(ApicRegIndex base, uint8_t vector)
180 return bits(regs[base + (vector % 32)], vector >> 5);
183 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
189 typedef X86LocalApicParams Params;
192 setClock(Tick newClock)
200 return dynamic_cast<const Params *>(_params);
204 * Functions to interact with the interrupt port from IntDev.
206 Tick read(PacketPtr pkt);
207 Tick write(PacketPtr pkt);
208 Tick recvMessage(PacketPtr pkt);
211 triggerTimerInterrupt()
213 LVTEntry entry = regs[APIC_LVT_TIMER];
215 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
216 return entry.periodic;
219 void addressRanges(AddrRangeList &range_list)
222 range_list.push_back(RangeEx(x86LocalAPICAddress(0, 0),
223 x86LocalAPICAddress(0, 0) + PageBytes));
226 void getIntAddrRange(AddrRangeList &range_list)
229 range_list.push_back(RangeEx(x86InterruptAddress(0, 0),
230 x86InterruptAddress(0, 0) + PhysAddrAPICRangeSize));
233 Port *getPort(const std::string &if_name, int idx = -1)
235 if (if_name == "int_port")
237 return BasicPioDevice::getPort(if_name, idx);
241 * Functions to access and manipulate the APIC's registers.
244 uint32_t readReg(ApicRegIndex miscReg);
245 void setReg(ApicRegIndex reg, uint32_t val);
247 setRegNoEffect(ApicRegIndex reg, uint32_t val)
256 Interrupts(Params * p)
257 : BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
258 apicTimerEvent(this),
259 pendingSmi(false), smiVector(0),
260 pendingNmi(false), nmiVector(0),
261 pendingExtInt(false), extIntVector(0),
262 pendingInit(false), initVector(0),
263 pendingUnmaskableInt(false)
266 memset(regs, 0, sizeof(regs));
267 //Set the local apic DFR to the flat model.
268 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
274 * Functions for retrieving interrupts for the CPU to handle.
277 bool checkInterrupts(ThreadContext *tc) const;
278 Fault getInterrupt(ThreadContext *tc);
279 void updateIntrInfo(ThreadContext *tc);
286 serialize(std::ostream &os)
288 panic("Interrupts::serialize unimplemented!\n");
292 unserialize(Checkpoint *cp, const std::string §ion)
294 panic("Interrupts::unserialize unimplemented!\n");
298 * Old functions needed for compatability but which will be phased out
302 post(int int_num, int index)
304 panic("Interrupts::post unimplemented!\n");
308 clear(int int_num, int index)
310 panic("Interrupts::clear unimplemented!\n");
316 panic("Interrupts::clearAll unimplemented!\n");
320 } // namespace X86ISA
322 #endif // __ARCH_X86_INTERRUPTS_HH__