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19 * property including but not limited to intellectual property relating
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53 #ifndef __ARCH_X86_INTERRUPTS_HH__
54 #define __ARCH_X86_INTERRUPTS_HH__
56 #include "arch/x86/regs/apic.hh"
57 #include "arch/x86/faults.hh"
58 #include "arch/x86/intmessage.hh"
59 #include "base/bitfield.hh"
60 #include "cpu/thread_context.hh"
61 #include "dev/x86/intdev.hh"
62 #include "dev/io_device.hh"
63 #include "params/X86LocalApic.hh"
64 #include "sim/eventq.hh"
71 class Interrupts : public BasicPioDevice, IntDev
74 // Storage for the APIC registers
75 uint32_t regs[NUM_APIC_REGS];
78 Bitfield<7, 0> vector;
79 Bitfield<10, 8> deliveryMode;
81 Bitfield<13> polarity;
82 Bitfield<14> remoteIRR;
85 Bitfield<17> periodic;
89 * Timing related stuff.
94 class ApicTimerEvent : public Event
97 Interrupts *localApic;
99 ApicTimerEvent(Interrupts *_localApic) :
100 Event(), localApic(_localApic)
106 if (localApic->triggerTimerInterrupt()) {
107 localApic->setReg(APIC_INITIAL_COUNT,
108 localApic->readReg(APIC_INITIAL_COUNT));
113 ApicTimerEvent apicTimerEvent;
116 * A set of variables to keep track of interrupts that don't go through
124 uint8_t extIntVector;
128 uint8_t startupVector;
131 // This is a quick check whether any of the above (except ExtInt) are set.
132 bool pendingUnmaskableInt;
134 // A count of how many IPIs are in flight.
138 * IRR and ISR maintenance.
144 findRegArrayMSB(ApicRegIndex base)
148 if (regs[base + offset] != 0) {
149 return offset * 32 + findMsbSet(regs[base + offset]);
158 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
164 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
168 setRegArrayBit(ApicRegIndex base, uint8_t vector)
170 regs[base + (vector / 32)] |= (1 << (vector % 32));
174 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
176 regs[base + (vector / 32)] &= ~(1 << (vector % 32));
180 getRegArrayBit(ApicRegIndex base, uint8_t vector)
182 return bits(regs[base + (vector / 32)], vector % 5);
185 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
191 // Port for receiving interrupts
192 IntPort intSlavePort;
196 int getInitialApicId() { return initialApicId; }
201 typedef X86LocalApicParams Params;
203 void setCPU(BaseCPU * newCPU);
206 setClock(Tick newClock)
214 return dynamic_cast<const Params *>(_params);
218 * Initialize this object by registering it with the IO APIC.
223 * Functions to interact with the interrupt port from IntDev.
225 Tick read(PacketPtr pkt);
226 Tick write(PacketPtr pkt);
227 Tick recvMessage(PacketPtr pkt);
228 Tick recvResponse(PacketPtr pkt);
231 triggerTimerInterrupt()
233 LVTEntry entry = regs[APIC_LVT_TIMER];
235 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
236 return entry.periodic;
239 AddrRangeList getAddrRanges();
240 AddrRangeList getIntAddrRange();
242 Port *getPort(const std::string &if_name, int idx = -1)
244 // a bit of an odd one since there is now two ports in the
245 // Python class we also need two ports even if they are
247 if (if_name == "int_master") {
249 } else if (if_name == "int_slave") {
250 return &intSlavePort;
252 return BasicPioDevice::getPort(if_name, idx);
256 * Functions to access and manipulate the APIC's registers.
259 uint32_t readReg(ApicRegIndex miscReg);
260 void setReg(ApicRegIndex reg, uint32_t val);
262 setRegNoEffect(ApicRegIndex reg, uint32_t val)
271 Interrupts(Params * p);
274 * Functions for retrieving interrupts for the CPU to handle.
277 bool checkInterrupts(ThreadContext *tc) const;
278 Fault getInterrupt(ThreadContext *tc);
279 void updateIntrInfo(ThreadContext *tc);
285 virtual void serialize(std::ostream &os);
286 virtual void unserialize(Checkpoint *cp, const std::string §ion);
289 * Old functions needed for compatability but which will be phased out
293 post(int int_num, int index)
295 panic("Interrupts::post unimplemented!\n");
299 clear(int int_num, int index)
301 panic("Interrupts::clear unimplemented!\n");
307 panic("Interrupts::clearAll unimplemented!\n");
311 } // namespace X86ISA
313 #endif // __ARCH_X86_INTERRUPTS_HH__