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19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
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53 #ifndef __ARCH_X86_INTERRUPTS_HH__
54 #define __ARCH_X86_INTERRUPTS_HH__
56 #include "arch/x86/regs/apic.hh"
57 #include "arch/x86/faults.hh"
58 #include "arch/x86/intmessage.hh"
59 #include "base/bitfield.hh"
60 #include "cpu/thread_context.hh"
61 #include "dev/x86/intdev.hh"
62 #include "dev/io_device.hh"
63 #include "params/X86LocalApic.hh"
64 #include "sim/eventq.hh"
69 int divideFromConf(uint32_t conf);
73 ApicRegIndex decodeAddr(Addr paddr);
75 class Interrupts : public BasicPioDevice, IntDevice
78 // Storage for the APIC registers
79 uint32_t regs[NUM_APIC_REGS];
82 Bitfield<7, 0> vector;
83 Bitfield<10, 8> deliveryMode;
85 Bitfield<13> polarity;
86 Bitfield<14> remoteIRR;
89 Bitfield<17> periodic;
93 * Timing related stuff.
95 class ApicTimerEvent : public Event
98 Interrupts *localApic;
100 ApicTimerEvent(Interrupts *_localApic) :
101 Event(), localApic(_localApic)
107 if (localApic->triggerTimerInterrupt()) {
108 localApic->setReg(APIC_INITIAL_COUNT,
109 localApic->readReg(APIC_INITIAL_COUNT));
114 ApicTimerEvent apicTimerEvent;
117 * A set of variables to keep track of interrupts that don't go through
125 uint8_t extIntVector;
129 uint8_t startupVector;
132 // This is a quick check whether any of the above (except ExtInt) are set.
133 bool pendingUnmaskableInt;
135 // A count of how many IPIs are in flight.
139 * IRR and ISR maintenance.
145 findRegArrayMSB(ApicRegIndex base)
149 if (regs[base + offset] != 0) {
150 return offset * 32 + findMsbSet(regs[base + offset]);
159 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
165 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
169 setRegArrayBit(ApicRegIndex base, uint8_t vector)
171 regs[base + (vector / 32)] |= (1 << (vector % 32));
175 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
177 regs[base + (vector / 32)] &= ~(1 << (vector % 32));
181 getRegArrayBit(ApicRegIndex base, uint8_t vector)
183 return bits(regs[base + (vector / 32)], vector % 5);
186 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
192 // Port for receiving interrupts
193 IntSlavePort intSlavePort;
197 int getInitialApicId() { return initialApicId; }
202 typedef X86LocalApicParams Params;
204 void setCPU(BaseCPU * newCPU);
209 return dynamic_cast<const Params *>(_params);
213 * Initialize this object by registering it with the IO APIC.
218 * Functions to interact with the interrupt port from IntDevice.
220 Tick read(PacketPtr pkt);
221 Tick write(PacketPtr pkt);
222 Tick recvMessage(PacketPtr pkt);
223 Tick recvResponse(PacketPtr pkt);
226 triggerTimerInterrupt()
228 LVTEntry entry = regs[APIC_LVT_TIMER];
230 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
231 return entry.periodic;
234 AddrRangeList getIntAddrRange() const;
236 BaseMasterPort &getMasterPort(const std::string &if_name,
237 PortID idx = InvalidPortID)
239 if (if_name == "int_master") {
240 return intMasterPort;
242 return BasicPioDevice::getMasterPort(if_name, idx);
245 BaseSlavePort &getSlavePort(const std::string &if_name,
246 PortID idx = InvalidPortID)
248 if (if_name == "int_slave") {
251 return BasicPioDevice::getSlavePort(if_name, idx);
255 * Functions to access and manipulate the APIC's registers.
258 uint32_t readReg(ApicRegIndex miscReg);
259 void setReg(ApicRegIndex reg, uint32_t val);
261 setRegNoEffect(ApicRegIndex reg, uint32_t val)
270 Interrupts(Params * p);
273 * Functions for retrieving interrupts for the CPU to handle.
276 bool checkInterrupts(ThreadContext *tc) const;
278 * Check if there are pending interrupts without ignoring the
279 * interrupts disabled flag.
281 * @return true if there are interrupts pending.
283 bool checkInterruptsRaw() const;
285 * Check if there are pending unmaskable interrupts.
287 * @return true there are unmaskable interrupts pending.
289 bool hasPendingUnmaskable() const { return pendingUnmaskableInt; }
290 Fault getInterrupt(ThreadContext *tc);
291 void updateIntrInfo(ThreadContext *tc);
297 virtual void serialize(std::ostream &os);
298 virtual void unserialize(Checkpoint *cp, const std::string §ion);
301 * Old functions needed for compatability but which will be phased out
305 post(int int_num, int index)
307 panic("Interrupts::post unimplemented!\n");
311 clear(int int_num, int index)
313 panic("Interrupts::clear unimplemented!\n");
319 panic("Interrupts::clearAll unimplemented!\n");
323 } // namespace X86ISA
325 #endif // __ARCH_X86_INTERRUPTS_HH__