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58 #ifndef __ARCH_X86_INTERRUPTS_HH__
59 #define __ARCH_X86_INTERRUPTS_HH__
61 #include "arch/x86/apicregs.hh"
62 #include "arch/x86/faults.hh"
63 #include "arch/x86/intmessage.hh"
64 #include "base/bitfield.hh"
65 #include "cpu/thread_context.hh"
66 #include "dev/io_device.hh"
67 #include "dev/x86/intdev.hh"
68 #include "params/X86LocalApic.hh"
69 #include "sim/eventq.hh"
76 class Interrupts : public BasicPioDevice, IntDev
79 // Storage for the APIC registers
80 uint32_t regs[NUM_APIC_REGS];
83 Bitfield<7, 0> vector;
84 Bitfield<10, 8> deliveryMode;
86 Bitfield<13> polarity;
87 Bitfield<14> remoteIRR;
90 Bitfield<17> periodic;
94 * Timing related stuff.
99 class ApicTimerEvent : public Event
102 Interrupts *localApic;
104 ApicTimerEvent(Interrupts *_localApic) :
105 Event(), localApic(_localApic)
111 if (localApic->triggerTimerInterrupt()) {
112 localApic->setReg(APIC_INITIAL_COUNT,
113 localApic->readReg(APIC_INITIAL_COUNT));
118 ApicTimerEvent apicTimerEvent;
121 * A set of variables to keep track of interrupts that don't go through
129 uint8_t extIntVector;
133 uint8_t startupVector;
136 // This is a quick check whether any of the above (except ExtInt) are set.
137 bool pendingUnmaskableInt;
139 // A count of how many IPIs are in flight.
143 * IRR and ISR maintenance.
149 findRegArrayMSB(ApicRegIndex base)
153 if (regs[base + offset] != 0) {
154 return offset * 32 + findMsbSet(regs[base + offset]);
163 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
169 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
173 setRegArrayBit(ApicRegIndex base, uint8_t vector)
175 regs[base + (vector / 32)] |= (1 << (vector % 32));
179 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
181 regs[base + (vector / 32)] &= ~(1 << (vector % 32));
185 getRegArrayBit(ApicRegIndex base, uint8_t vector)
187 return bits(regs[base + (vector / 32)], vector % 5);
190 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
200 typedef X86LocalApicParams Params;
202 void setCPU(BaseCPU * newCPU);
205 setClock(Tick newClock)
213 return dynamic_cast<const Params *>(_params);
217 * Initialize this object by registering it with the IO APIC.
222 * Functions to interact with the interrupt port from IntDev.
224 Tick read(PacketPtr pkt);
225 Tick write(PacketPtr pkt);
226 Tick recvMessage(PacketPtr pkt);
227 Tick recvResponse(PacketPtr pkt);
230 triggerTimerInterrupt()
232 LVTEntry entry = regs[APIC_LVT_TIMER];
234 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
235 return entry.periodic;
238 void addressRanges(AddrRangeList &range_list);
239 void getIntAddrRange(AddrRangeList &range_list);
241 Port *getPort(const std::string &if_name, int idx = -1)
243 if (if_name == "int_port")
245 return BasicPioDevice::getPort(if_name, idx);
249 * Functions to access and manipulate the APIC's registers.
252 uint32_t readReg(ApicRegIndex miscReg);
253 void setReg(ApicRegIndex reg, uint32_t val);
255 setRegNoEffect(ApicRegIndex reg, uint32_t val)
264 Interrupts(Params * p);
267 * Functions for retrieving interrupts for the CPU to handle.
270 bool checkInterrupts(ThreadContext *tc) const;
271 Fault getInterrupt(ThreadContext *tc);
272 void updateIntrInfo(ThreadContext *tc);
279 serialize(std::ostream &os)
281 panic("Interrupts::serialize unimplemented!\n");
285 unserialize(Checkpoint *cp, const std::string §ion)
287 panic("Interrupts::unserialize unimplemented!\n");
291 * Old functions needed for compatability but which will be phased out
295 post(int int_num, int index)
297 panic("Interrupts::post unimplemented!\n");
301 clear(int int_num, int index)
303 panic("Interrupts::clear unimplemented!\n");
309 panic("Interrupts::clearAll unimplemented!\n");
313 } // namespace X86ISA
315 #endif // __ARCH_X86_INTERRUPTS_HH__