src/arch/x86/interrupts.hh

   1 /*
   2  * Copyright (c) 2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007 The Hewlett-Packard Development Company
  15  * All rights reserved.
  16  *
  17  * The license below extends only to copyright in the software and shall
  18  * not be construed as granting a license to any other intellectual
  19  * property including but not limited to intellectual property relating
  20  * to a hardware implementation of the functionality of the software
  21  * licensed hereunder.  You may use the software subject to the license
  22  * terms below provided that you ensure that this notice is replicated
  23  * unmodified and in its entirety in all distributions of the software,
  24  * modified or unmodified, in source code or in binary form.
  25  *
  26  * Redistribution and use in source and binary forms, with or without
  27  * modification, are permitted provided that the following conditions are
  28  * met: redistributions of source code must retain the above copyright
  29  * notice, this list of conditions and the following disclaimer;
  30  * redistributions in binary form must reproduce the above copyright
  31  * notice, this list of conditions and the following disclaimer in the
  32  * documentation and/or other materials provided with the distribution;
  33  * neither the name of the copyright holders nor the names of its
  34  * contributors may be used to endorse or promote products derived from
  35  * this software without specific prior written permission.
  36  *
  37  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  38  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  39  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  40  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  41  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  42  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  43  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  44  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  45  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  46  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  47  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  48  */
  49
  50 #ifndef __ARCH_X86_INTERRUPTS_HH__
  51 #define __ARCH_X86_INTERRUPTS_HH__
  52
  53 #include "arch/generic/interrupts.hh"
  54 #include "arch/x86/faults.hh"
  55 #include "arch/x86/intmessage.hh"
  56 #include "arch/x86/regs/apic.hh"
  57 #include "base/bitfield.hh"
  58 #include "cpu/thread_context.hh"
  59 #include "dev/io_device.hh"
  60 #include "dev/x86/intdev.hh"
  61 #include "params/X86LocalApic.hh"
  62 #include "sim/eventq.hh"
  63
  64 class ThreadContext;
  65 class BaseCPU;
  66
  67 int divideFromConf(uint32_t conf);
  68
  69 namespace X86ISA
  70 {
  71
  72 ApicRegIndex decodeAddr(Addr paddr);
  73
  74 class Interrupts : public BaseInterrupts
  75 {
  76   protected:
  77     System *sys;
  78     ClockDomain &clockDomain;
  79
  80     // Storage for the APIC registers
  81     uint32_t regs[NUM_APIC_REGS];
  82
  83     BitUnion32(LVTEntry)
  84         Bitfield<7, 0> vector;
  85         Bitfield<10, 8> deliveryMode;
  86         Bitfield<12> status;
  87         Bitfield<13> polarity;
  88         Bitfield<14> remoteIRR;
  89         Bitfield<15> trigger;
  90         Bitfield<16> masked;
  91         Bitfield<17> periodic;
  92     EndBitUnion(LVTEntry)
  93
  94     /*
  95      * Timing related stuff.
  96      */
  97     EventFunctionWrapper apicTimerEvent;
  98     void processApicTimerEvent();
  99
 100     /*
 101      * A set of variables to keep track of interrupts that don't go through
 102      * the IRR.
 103      */
 104     bool pendingSmi;
 105     uint8_t smiVector;
 106     bool pendingNmi;
 107     uint8_t nmiVector;
 108     bool pendingExtInt;
 109     uint8_t extIntVector;
 110     bool pendingInit;
 111     uint8_t initVector;
 112     bool pendingStartup;
 113     uint8_t startupVector;
 114     bool startedUp;
 115
 116     // This is a quick check whether any of the above (except ExtInt) are set.
 117     bool pendingUnmaskableInt;
 118
 119     // A count of how many IPIs are in flight.
 120     int pendingIPIs;
 121
 122     /*
 123      * IRR and ISR maintenance.
 124      */
 125     uint8_t IRRV;
 126     uint8_t ISRV;
 127
 128     int
 129     findRegArrayMSB(ApicRegIndex base)
 130     {
 131         int offset = 7;
 132         do {
 133             if (regs[base + offset] != 0) {
 134                 return offset * 32 + findMsbSet(regs[base + offset]);
 135             }
 136         } while (offset--);
 137         return 0;
 138     }
 139
 140     void
 141     updateIRRV()
 142     {
 143         IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
 144     }
 145
 146     void
 147     updateISRV()
 148     {
 149         ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
 150     }
 151
 152     void
 153     setRegArrayBit(ApicRegIndex base, uint8_t vector)
 154     {
 155         regs[base + (vector / 32)] |= (1 << (vector % 32));
 156     }
 157
 158     void
 159     clearRegArrayBit(ApicRegIndex base, uint8_t vector)
 160     {
 161         regs[base + (vector / 32)] &= ~(1 << (vector % 32));
 162     }
 163
 164     bool
 165     getRegArrayBit(ApicRegIndex base, uint8_t vector)
 166     {
 167         return bits(regs[base + (vector / 32)], vector % 32);
 168     }
 169
 170     Tick clockPeriod() const { return clockDomain.clockPeriod(); }
 171
 172     void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
 173
 174     int initialApicId;
 175
 176     // Ports for interrupts.
 177     IntResponsePort<Interrupts> intResponsePort;
 178     IntRequestPort<Interrupts> intRequestPort;
 179
 180     // Port for memory mapped register accesses.
 181     PioPort<Interrupts> pioPort;
 182
 183     Tick pioDelay;
 184     Addr pioAddr = MaxAddr;
 185
 186   public:
 187
 188     int getInitialApicId() { return initialApicId; }
 189
 190     /*
 191      * Params stuff.
 192      */
 193     typedef X86LocalApicParams Params;
 194
 195     void setThreadContext(ThreadContext *_tc) override;
 196
 197     const Params *
 198     params() const
 199     {
 200         return dynamic_cast<const Params *>(_params);
 201     }
 202
 203     /*
 204      * Initialize this object by registering it with the IO APIC.
 205      */
 206     void init() override;
 207
 208     /*
 209      * Functions to interact with the interrupt port.
 210      */
 211     Tick read(PacketPtr pkt);
 212     Tick write(PacketPtr pkt);
 213     Tick recvMessage(PacketPtr pkt);
 214     void completeIPI(PacketPtr pkt);
 215
 216     bool
 217     triggerTimerInterrupt()
 218     {
 219         LVTEntry entry = regs[APIC_LVT_TIMER];
 220         if (!entry.masked)
 221             requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
 222         return entry.periodic;
 223     }
 224
 225     AddrRangeList getAddrRanges() const;
 226     AddrRangeList getIntAddrRange() const;
 227
 228     Port &getPort(const std::string &if_name,
 229                   PortID idx=InvalidPortID) override
 230     {
 231         if (if_name == "int_requestor") {
 232             return intRequestPort;
 233         } else if (if_name == "int_responder") {
 234             return intResponsePort;
 235         } else if (if_name == "pio") {
 236             return pioPort;
 237         }
 238         return SimObject::getPort(if_name, idx);
 239     }
 240
 241     /*
 242      * Functions to access and manipulate the APIC's registers.
 243      */
 244
 245     uint32_t readReg(ApicRegIndex miscReg);
 246     void setReg(ApicRegIndex reg, uint32_t val);
 247     void
 248     setRegNoEffect(ApicRegIndex reg, uint32_t val)
 249     {
 250         regs[reg] = val;
 251     }
 252
 253     /*
 254      * Constructor.
 255      */
 256
 257     Interrupts(Params * p);
 258
 259     /*
 260      * Functions for retrieving interrupts for the CPU to handle.
 261      */
 262
 263     bool checkInterrupts() const override;
 264     /**
 265      * Check if there are pending interrupts without ignoring the
 266      * interrupts disabled flag.
 267      *
 268      * @return true if there are interrupts pending.
 269      */
 270     bool checkInterruptsRaw() const;
 271     /**
 272      * Check if there are pending unmaskable interrupts.
 273      *
 274      * @return true there are unmaskable interrupts pending.
 275      */
 276     bool hasPendingUnmaskable() const { return pendingUnmaskableInt; }
 277     Fault getInterrupt() override;
 278     void updateIntrInfo() override;
 279
 280     /*
 281      * Serialization.
 282      */
 283     void serialize(CheckpointOut &cp) const override;
 284     void unserialize(CheckpointIn &cp) override;
 285
 286     /*
 287      * Old functions needed for compatability but which will be phased out
 288      * eventually.
 289      */
 290     void
 291     post(int int_num, int index) override
 292     {
 293         panic("Interrupts::post unimplemented!\n");
 294     }
 295
 296     void
 297     clear(int int_num, int index) override
 298     {
 299         panic("Interrupts::clear unimplemented!\n");
 300     }
 301
 302     void
 303     clearAll() override
 304     {
 305         panic("Interrupts::clearAll unimplemented!\n");
 306     }
 307 };
 308
 309 } // namespace X86ISA
 310
 311 #endif // __ARCH_X86_INTERRUPTS_HH__