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58 #ifndef __ARCH_X86_INTERRUPTS_HH__
59 #define __ARCH_X86_INTERRUPTS_HH__
61 #include "arch/x86/apicregs.hh"
62 #include "arch/x86/faults.hh"
63 #include "arch/x86/intmessage.hh"
64 #include "base/bitfield.hh"
65 #include "cpu/thread_context.hh"
66 #include "dev/io_device.hh"
67 #include "dev/x86/intdev.hh"
68 #include "params/X86LocalApic.hh"
69 #include "sim/eventq.hh"
76 class Interrupts : public BasicPioDevice, IntDev
79 // Storage for the APIC registers
80 uint32_t regs[NUM_APIC_REGS];
83 Bitfield<7, 0> vector;
84 Bitfield<10, 8> deliveryMode;
86 Bitfield<13> polarity;
87 Bitfield<14> remoteIRR;
90 Bitfield<17> periodic;
94 * Timing related stuff.
99 class ApicTimerEvent : public Event
102 Interrupts *localApic;
104 ApicTimerEvent(Interrupts *_localApic) :
105 Event(), localApic(_localApic)
111 if (localApic->triggerTimerInterrupt()) {
112 localApic->setReg(APIC_INITIAL_COUNT,
113 localApic->readReg(APIC_INITIAL_COUNT));
118 ApicTimerEvent apicTimerEvent;
121 * A set of variables to keep track of interrupts that don't go through
129 uint8_t extIntVector;
133 // This is a quick check whether any of the above (except ExtInt) are set.
134 bool pendingUnmaskableInt;
137 * IRR and ISR maintenance.
143 findRegArrayMSB(ApicRegIndex base)
147 if (regs[base + offset] != 0) {
148 return offset * 32 + findMsbSet(regs[base + offset]);
157 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
163 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
167 setRegArrayBit(ApicRegIndex base, uint8_t vector)
169 regs[base + (vector % 32)] |= (1 << (vector >> 5));
173 clearRegArrayBit(ApicRegIndex base, uint8_t vector)
175 regs[base + (vector % 32)] &= ~(1 << (vector >> 5));
179 getRegArrayBit(ApicRegIndex base, uint8_t vector)
181 return bits(regs[base + (vector % 32)], vector >> 5);
184 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
192 typedef X86LocalApicParams Params;
195 setCPU(BaseCPU * newCPU)
201 setClock(Tick newClock)
209 return dynamic_cast<const Params *>(_params);
213 * Functions to interact with the interrupt port from IntDev.
215 Tick read(PacketPtr pkt);
216 Tick write(PacketPtr pkt);
217 Tick recvMessage(PacketPtr pkt);
220 triggerTimerInterrupt()
222 LVTEntry entry = regs[APIC_LVT_TIMER];
224 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
225 return entry.periodic;
228 void addressRanges(AddrRangeList &range_list)
231 range_list.push_back(RangeEx(x86LocalAPICAddress(0, 0),
232 x86LocalAPICAddress(0, 0) + PageBytes));
235 void getIntAddrRange(AddrRangeList &range_list)
238 range_list.push_back(RangeEx(x86InterruptAddress(0, 0),
239 x86InterruptAddress(0, 0) + PhysAddrAPICRangeSize));
242 Port *getPort(const std::string &if_name, int idx = -1)
244 if (if_name == "int_port")
246 return BasicPioDevice::getPort(if_name, idx);
250 * Functions to access and manipulate the APIC's registers.
253 uint32_t readReg(ApicRegIndex miscReg);
254 void setReg(ApicRegIndex reg, uint32_t val);
256 setRegNoEffect(ApicRegIndex reg, uint32_t val)
265 Interrupts(Params * p)
266 : BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
267 apicTimerEvent(this),
268 pendingSmi(false), smiVector(0),
269 pendingNmi(false), nmiVector(0),
270 pendingExtInt(false), extIntVector(0),
271 pendingInit(false), initVector(0),
272 pendingUnmaskableInt(false)
275 memset(regs, 0, sizeof(regs));
276 //Set the local apic DFR to the flat model.
277 regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
283 * Functions for retrieving interrupts for the CPU to handle.
286 bool checkInterrupts(ThreadContext *tc) const;
287 Fault getInterrupt(ThreadContext *tc);
288 void updateIntrInfo(ThreadContext *tc);
295 serialize(std::ostream &os)
297 panic("Interrupts::serialize unimplemented!\n");
301 unserialize(Checkpoint *cp, const std::string §ion)
303 panic("Interrupts::unserialize unimplemented!\n");
307 * Old functions needed for compatability but which will be phased out
311 post(int int_num, int index)
313 panic("Interrupts::post unimplemented!\n");
317 clear(int int_num, int index)
319 panic("Interrupts::clear unimplemented!\n");
325 panic("Interrupts::clearAll unimplemented!\n");
329 } // namespace X86ISA
331 #endif // __ARCH_X86_INTERRUPTS_HH__