X86: Set the flags on a rotate right instruction.
[gem5.git] / src / arch / x86 / isa / insts / general_purpose / rotate_and_shift / rotate.py
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54 # Authors: Gabe Black
55
56 microcode = '''
57 def macroop ROL_R_I
58 {
59 roli reg, reg, imm, flags=(OF,CF)
60 };
61
62 def macroop ROL_M_I
63 {
64 ldst t1, seg, sib, disp
65 roli t1, t1, imm, flags=(OF,CF)
66 st t1, seg, sib, disp
67 };
68
69 def macroop ROL_P_I
70 {
71 rdip t7
72 ldst t1, seg, riprel, disp
73 roli t1, t1, imm, flags=(OF,CF)
74 st t1, seg, riprel, disp
75 };
76
77 def macroop ROL_1_R
78 {
79 roli reg, reg, 1, flags=(OF,CF)
80 };
81
82 def macroop ROL_1_M
83 {
84 ldst t1, seg, sib, disp
85 roli t1, t1, 1, flags=(OF,CF)
86 st t1, seg, sib, disp
87 };
88
89 def macroop ROL_1_P
90 {
91 rdip t7
92 ldst t1, seg, riprel, disp
93 roli t1, t1, 1, flags=(OF,CF)
94 st t1, seg, riprel, disp
95 };
96
97 def macroop ROL_R_R
98 {
99 rol reg, reg, regm, flags=(OF,CF)
100 };
101
102 def macroop ROL_M_R
103 {
104 ldst t1, seg, sib, disp
105 rol t1, t1, reg, flags=(OF,CF)
106 st t1, seg, sib, disp
107 };
108
109 def macroop ROL_P_R
110 {
111 rdip t7
112 ldst t1, seg, riprel, disp
113 rol t1, t1, reg, flags=(OF,CF)
114 st t1, seg, riprel, disp
115 };
116
117 def macroop ROR_R_I
118 {
119 rori reg, reg, imm, flags=(OF,CF)
120 };
121
122 def macroop ROR_M_I
123 {
124 ldst t1, seg, sib, disp
125 rori t1, t1, imm, flags=(OF,CF)
126 st t1, seg, sib, disp
127 };
128
129 def macroop ROR_P_I
130 {
131 rdip t7
132 ldst t1, seg, riprel, disp
133 rori t1, t1, imm, flags=(OF,CF)
134 st t1, seg, riprel, disp
135 };
136
137 def macroop ROR_1_R
138 {
139 rori reg, reg, 1, flags=(OF,CF)
140 };
141
142 def macroop ROR_1_M
143 {
144 ldst t1, seg, sib, disp
145 rori t1, t1, 1, flags=(OF,CF)
146 st t1, seg, sib, disp
147 };
148
149 def macroop ROR_1_P
150 {
151 rdip t7
152 ldst t1, seg, riprel, disp
153 rori t1, t1, 1, flags=(OF,CF)
154 st t1, seg, riprel, disp
155 };
156
157 def macroop ROR_R_R
158 {
159 ror reg, reg, regm, flags=(OF,CF)
160 };
161
162 def macroop ROR_M_R
163 {
164 ldst t1, seg, sib, disp
165 ror t1, t1, reg, flags=(OF,CF)
166 st t1, seg, sib, disp
167 };
168
169 def macroop ROR_P_R
170 {
171 rdip t7
172 ldst t1, seg, riprel, disp
173 ror t1, t1, reg, flags=(OF,CF)
174 st t1, seg, riprel, disp
175 };
176
177 def macroop RCL_R_I
178 {
179 rcli reg, reg, imm
180 };
181
182 def macroop RCL_M_I
183 {
184 ldst t1, seg, sib, disp
185 rcli t1, t1, imm
186 st t1, seg, sib, disp
187 };
188
189 def macroop RCL_P_I
190 {
191 rdip t7
192 ldst t1, seg, riprel, disp
193 rcli t1, t1, imm
194 st t1, seg, riprel, disp
195 };
196
197 def macroop RCL_1_R
198 {
199 rcli reg, reg, 1
200 };
201
202 def macroop RCL_1_M
203 {
204 ldst t1, seg, sib, disp
205 rcli t1, t1, 1
206 st t1, seg, sib, disp
207 };
208
209 def macroop RCL_1_P
210 {
211 rdip t7
212 ldst t1, seg, riprel, disp
213 rcli t1, t1, 1
214 st t1, seg, riprel, disp
215 };
216
217 def macroop RCL_R_R
218 {
219 rcl reg, reg, regm
220 };
221
222 def macroop RCL_M_R
223 {
224 ldst t1, seg, sib, disp
225 rcl t1, t1, reg
226 st t1, seg, sib, disp
227 };
228
229 def macroop RCL_P_R
230 {
231 rdip t7
232 ldst t1, seg, riprel, disp
233 rcl t1, t1, reg
234 st t1, seg, riprel, disp
235 };
236
237 def macroop RCR_R_I
238 {
239 rcri reg, reg, imm
240 };
241
242 def macroop RCR_M_I
243 {
244 ldst t1, seg, sib, disp
245 rcri t1, t1, imm
246 st t1, seg, sib, disp
247 };
248
249 def macroop RCR_P_I
250 {
251 rdip t7
252 ldst t1, seg, riprel, disp
253 rcri t1, t1, imm
254 st t1, seg, riprel, disp
255 };
256
257 def macroop RCR_1_R
258 {
259 rcri reg, reg, 1
260 };
261
262 def macroop RCR_1_M
263 {
264 ldst t1, seg, sib, disp
265 rcri t1, t1, 1
266 st t1, seg, sib, disp
267 };
268
269 def macroop RCR_1_P
270 {
271 rdip t7
272 ldst t1, seg, riprel, disp
273 rcri t1, t1, 1
274 st t1, seg, riprel, disp
275 };
276
277 def macroop RCR_R_R
278 {
279 rcr reg, reg, regm
280 };
281
282 def macroop RCR_M_R
283 {
284 ldst t1, seg, sib, disp
285 rcr t1, t1, reg
286 st t1, seg, sib, disp
287 };
288
289 def macroop RCR_P_R
290 {
291 rdip t7
292 ldst t1, seg, riprel, disp
293 rcr t1, t1, reg
294 st t1, seg, riprel, disp
295 };
296 '''