X86: Implement the LIDT instruction.
[gem5.git] / src / arch / x86 / isa / microasm.isa
1 // -*- mode:c++ -*-
2
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56 // Authors: Gabe Black
57
58 //Include the definitions of the micro ops.
59 //These are python representations of static insts which stand on their own
60 //and make up an internal instruction set. They are used by the micro
61 //assembler.
62 ##include "microops/microops.isa"
63
64 //Include code to build macroops in both C++ and python.
65 ##include "macroop.isa"
66
67 let {{
68 import sys
69 sys.path[0:0] = ["src/arch/x86/isa/"]
70 from insts import microcode
71 # print microcode
72 from micro_asm import MicroAssembler, Rom_Macroop, Rom
73 mainRom = Rom('main ROM')
74 assembler = MicroAssembler(X86Macroop, microopClasses, mainRom, Rom_Macroop)
75 # Add in symbols for the microcode registers
76 for num in range(15):
77 assembler.symbols["t%d" % num] = "NUM_INTREGS+%d" % num
78 for num in range(7):
79 assembler.symbols["ufp%d" % num] = "FLOATREG_MICROFP(%d)" % num
80 # Add in symbols for the segment descriptor registers
81 for letter in ("C", "D", "E", "F", "G", "S"):
82 assembler.symbols["%ss" % letter.lower()] = "SEGMENT_REG_%sS" % letter
83
84 for reg in ("LDTR", "TR", "GDTR", "IDTR"):
85 assembler.symbols[reg.lower()] = "SYS_SEGMENT_REG_%s" % reg
86
87 # Miscellaneous symbols
88 symbols = {
89 "reg" : "env.reg",
90 "xmml" : "FLOATREG_XMM_LOW(env.reg)",
91 "xmmh" : "FLOATREG_XMM_HIGH(env.reg)",
92 "regm" : "env.regm",
93 "xmmlm" : "FLOATREG_XMM_LOW(env.regm)",
94 "xmmhm" : "FLOATREG_XMM_HIGH(env.regm)",
95 "imm" : "adjustedImm",
96 "disp" : "adjustedDisp",
97 "seg" : "env.seg",
98 "scale" : "env.scale",
99 "index" : "env.index",
100 "base" : "env.base",
101 "dsz" : "env.dataSize",
102 "asz" : "env.addressSize",
103 "ssz" : "env.stackSize"
104 }
105 assembler.symbols.update(symbols)
106
107 # Short hand for common scale-index-base combinations.
108 assembler.symbols["sib"] = \
109 [symbols["scale"], symbols["index"], symbols["base"]]
110 assembler.symbols["riprel"] = \
111 ["1", assembler.symbols["t0"], assembler.symbols["t7"]]
112
113 # This segment selects an internal address space mapped to MSRs,
114 # CPUID info, etc.
115 assembler.symbols["intseg"] = "SEGMENT_REG_INT"
116
117 for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
118 assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
119
120 for reg in range(15):
121 assembler.symbols["cr%d" % reg] = "MISCREG_CR%d" % reg
122
123 for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF'):
124 assembler.symbols[flag] = flag + "Bit"
125
126 for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
127 'MSTRZ', 'STRZ', 'MSTRC',
128 'OF', 'CF', 'ZF', 'CvZF',
129 'SF', 'PF', 'SxOF', 'SxOvZF'):
130 assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond
131 assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond
132 assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF"
133 assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF"
134
135 assembler.symbols["CTrue"] = "ConditionTests::True"
136 assembler.symbols["CFalse"] = "ConditionTests::False"
137
138 # Code literal which forces a default 64 bit operand size in 64 bit mode.
139 assembler.symbols["oszIn64Override"] = '''
140 if (machInst.mode.submode == SixtyFourBitMode &&
141 env.dataSize == 4)
142 env.dataSize = 8;
143 '''
144
145 assembler.symbols["oszForPseudoDesc"] = '''
146 if (machInst.mode.submode == SixtyFourBitMode)
147 env.dataSize = 8;
148 else
149 env.dataSize = 4;
150 '''
151
152 def trimImm(width):
153 return "adjustedImm = adjustedImm & mask(%s);" % width
154
155 assembler.symbols["trimImm"] = trimImm
156
157 def labeler(labelStr):
158 return "label_%s" % labelStr
159
160 assembler.symbols["label"] = labeler
161
162 def stack_index(index):
163 return "(NUM_FLOATREGS + (((%s) + 8) %% 8))" % index
164
165 assembler.symbols["st"] = stack_index
166
167 macroopDict = assembler.assemble(microcode)
168 }};