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40 // applicable, this list of conditions and the disclaimer below.
42 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
45 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
46 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
47 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
48 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
50 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
51 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 // Authors: Gabe Black
56 //////////////////////////////////////////////////////////////////////////
58 // RegOp Microop templates
60 //////////////////////////////////////////////////////////////////////////
62 def template MicroRegOpExecute {{
63 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
64 Trace::InstRecord *traceData) const
66 Fault fault = NoFault;
68 DPRINTF(X86, "The data size is %d\n", dataSize);
82 //Write the resulting state to the execution context
91 def template MicroRegOpImmExecute {{
92 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
93 Trace::InstRecord *traceData) const
95 Fault fault = NoFault;
110 //Write the resulting state to the execution context
119 def template MicroRegOpDeclare {{
120 class %(class_name)s : public %(base_class)s
126 %(class_name)s(ExtMachInst _machInst,
127 const char * instMnem,
128 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
129 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
130 uint8_t _dataSize, uint16_t _ext);
132 %(class_name)s(ExtMachInst _machInst,
133 const char * instMnem,
134 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
135 uint8_t _dataSize, uint16_t _ext);
141 def template MicroRegOpImmDeclare {{
143 class %(class_name)s : public %(base_class)s
149 %(class_name)s(ExtMachInst _machInst,
150 const char * instMnem,
151 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
152 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
153 uint8_t _dataSize, uint16_t _ext);
155 %(class_name)s(ExtMachInst _machInst,
156 const char * instMnem,
157 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
158 uint8_t _dataSize, uint16_t _ext);
164 def template MicroRegOpConstructor {{
166 inline void %(class_name)s::buildMe()
171 inline %(class_name)s::%(class_name)s(
172 ExtMachInst machInst, const char * instMnem,
173 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
174 uint8_t _dataSize, uint16_t _ext) :
175 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
176 false, false, false, false,
177 _src1, _src2, _dest, _dataSize, _ext,
183 inline %(class_name)s::%(class_name)s(
184 ExtMachInst machInst, const char * instMnem,
185 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
186 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
187 uint8_t _dataSize, uint16_t _ext) :
188 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
189 isMicro, isDelayed, isFirst, isLast,
190 _src1, _src2, _dest, _dataSize, _ext,
197 def template MicroRegOpImmConstructor {{
199 inline void %(class_name)s::buildMe()
204 inline %(class_name)s::%(class_name)s(
205 ExtMachInst machInst, const char * instMnem,
206 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
207 uint8_t _dataSize, uint16_t _ext) :
208 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
209 false, false, false, false,
210 _src1, _imm8, _dest, _dataSize, _ext,
216 inline %(class_name)s::%(class_name)s(
217 ExtMachInst machInst, const char * instMnem,
218 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
219 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
220 uint8_t _dataSize, uint16_t _ext) :
221 %(base_class)s(machInst, "%(mnemonic)s", instMnem,
222 isMicro, isDelayed, isFirst, isLast,
223 _src1, _imm8, _dest, _dataSize, _ext,
232 divide(uint64_t dividend, uint64_t divisor,
233 uint64_t "ient, uint64_t &remainder);
235 enum SegmentSelectorCheck {
236 SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
237 SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck,
238 SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck
241 enum LongModeDescriptorType {
253 divide(uint64_t dividend, uint64_t divisor,
254 uint64_t "ient, uint64_t &remainder)
256 //Check for divide by zero.
258 panic("Divide by zero!\\n");
259 //If the divisor is bigger than the dividend, don't do anything.
260 if (divisor <= dividend) {
261 //Shift the divisor so it's msb lines up with the dividend.
262 int dividendMsb = findMsbSet(dividend);
263 int divisorMsb = findMsbSet(divisor);
264 int shift = dividendMsb - divisorMsb;
266 //Compute what we'll add to the quotient if the divisor isn't
267 //now larger than the dividend.
268 uint64_t quotientBit = 1;
269 quotientBit <<= shift;
270 //If we need to step back a bit (no pun intended) because the
271 //divisor got too to large, do that here. This is the "or two"
272 //part of one or two bit division.
273 if (divisor > dividend) {
277 //Decrement the remainder and increment the quotient.
278 quotient += quotientBit;
279 remainder -= divisor;
285 # Make these empty strings so that concatenating onto
286 # them will always work.
292 MicroRegOpImmDeclare,
293 MicroRegOpImmConstructor,
294 MicroRegOpImmExecute)
298 MicroRegOpConstructor,
301 class RegOpMeta(type):
302 def buildCppClasses(self, name, Name, suffix, \
303 code, flag_code, cond_check, else_code):
305 # Globals to stick the output in
307 global decoder_output
310 # Stick all the code together so it can be searched at once
311 allCode = "|".join((code, flag_code, cond_check, else_code))
313 # If op2 is used anywhere, make register and immediate versions
315 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
316 match = matcher.search(allCode)
319 if match.group("typeQual"):
320 typeQual = match.group("typeQual")
321 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
322 self.buildCppClasses(name, Name, suffix,
323 matcher.sub(src2_name, code),
324 matcher.sub(src2_name, flag_code),
325 matcher.sub(src2_name, cond_check),
326 matcher.sub(src2_name, else_code))
327 self.buildCppClasses(name + "i", Name, suffix + "Imm",
328 matcher.sub("imm8", code),
329 matcher.sub("imm8", flag_code),
330 matcher.sub("imm8", cond_check),
331 matcher.sub("imm8", else_code))
334 # If there's something optional to do with flags, generate
335 # a version without it and fix up this version to use it.
336 if flag_code != "" or cond_check != "true":
337 self.buildCppClasses(name, Name, suffix,
338 code, "", "true", else_code)
339 suffix = "Flags" + suffix
341 # If psrc1 or psrc2 is used, we need to actually insert code to
343 matcher = re.compile("(?<!\w)psrc1(?!\w)")
344 if matcher.search(allCode):
345 code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
346 matcher = re.compile("(?<!\w)psrc2(?!\w)")
347 if matcher.search(allCode):
348 code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
349 # Also make available versions which do sign extension
350 matcher = re.compile("(?<!\w)spsrc1(?!\w)")
351 if matcher.search(allCode):
352 code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
353 matcher = re.compile("(?<!\w)spsrc2(?!\w)")
354 if matcher.search(allCode):
355 code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
357 base = "X86ISA::RegOp"
359 # If imm8 shows up in the code, use the immediate templates, if
360 # not, hopefully the register ones will be correct.
361 templates = regTemplates
362 matcher = re.compile("(?<!\w)imm8(?!\w)")
363 if matcher.search(allCode):
365 templates = immTemplates
367 # Get everything ready for the substitution
368 iop = InstObjParams(name, Name + suffix, base,
370 "flag_code" : flag_code,
371 "cond_check" : cond_check,
372 "else_code" : else_code})
374 # Generate the actual code (finally!)
375 header_output += templates[0].subst(iop)
376 decoder_output += templates[1].subst(iop)
377 exec_output += templates[2].subst(iop)
380 def __new__(mcls, Name, bases, dict):
383 if "abstract" in dict:
384 abstract = dict['abstract']
387 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
390 cls.base_mnemonic = name
392 flag_code = cls.flag_code
393 cond_check = cls.cond_check
394 else_code = cls.else_code
396 # Set up the C++ classes
397 mcls.buildCppClasses(cls, name, Name, "",
398 code, flag_code, cond_check, else_code)
400 # Hook into the microassembler dict
401 global microopClasses
402 microopClasses[name] = cls
404 allCode = "|".join((code, flag_code, cond_check, else_code))
406 # If op2 is used anywhere, make register and immediate versions
408 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
409 if matcher.search(allCode):
410 microopClasses[name + 'i'] = cls
414 class RegOp(X86Microop):
415 __metaclass__ = RegOpMeta
416 # This class itself doesn't act as a microop
419 # Default template parameter values
424 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
429 self.dataSize = dataSize
433 if not isinstance(flags, (list, tuple)):
434 raise Exception, "flags must be a list or tuple of flags"
435 self.ext = " | ".join(flags)
436 self.className += "Flags"
438 def getAllocator(self, *microFlags):
439 className = self.className
440 if self.mnemonic == self.base_mnemonic + 'i':
442 allocator = '''new %(class_name)s(machInst, macrocodeBlock
443 %(flags)s, %(src1)s, %(op2)s, %(dest)s,
444 %(dataSize)s, %(ext)s)''' % {
445 "class_name" : className,
446 "flags" : self.microFlagsText(microFlags),
447 "src1" : self.src1, "op2" : self.op2,
449 "dataSize" : self.dataSize,
453 class LogicRegOp(RegOp):
456 //Don't have genFlags handle the OF or CF bits
457 uint64_t mask = CFBit | ECFBit | OFBit;
458 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
459 //If a logic microop wants to set these, it wants to set them to 0.
460 ccFlagBits &= ~(CFBit & ext);
461 ccFlagBits &= ~(ECFBit & ext);
462 ccFlagBits &= ~(OFBit & ext);
465 class FlagRegOp(RegOp):
468 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
470 class SubRegOp(RegOp):
473 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
475 class CondRegOp(RegOp):
477 cond_check = "checkCondition(ccFlagBits, ext)"
479 class RdRegOp(RegOp):
481 def __init__(self, dest, src1=None, dataSize="env.dataSize"):
484 super(RdRegOp, self).__init__(dest, src1, \
485 "InstRegIndex(NUM_INTREGS)", None, dataSize)
487 class WrRegOp(RegOp):
489 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
490 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
491 src1, src2, flags, dataSize)
493 class Add(FlagRegOp):
494 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
496 class Or(LogicRegOp):
497 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
499 class Adc(FlagRegOp):
501 CCFlagBits flags = ccFlagBits;
502 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
507 CCFlagBits flags = ccFlagBits;
508 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
511 class And(LogicRegOp):
512 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
515 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
517 class Xor(LogicRegOp):
518 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
520 class Mul1s(WrRegOp):
522 ProdLow = psrc1 * op2;
523 int halfSize = (dataSize * 8) / 2;
524 uint64_t shifter = (1ULL << halfSize);
526 uint64_t psrc1_h = psrc1 / shifter;
527 uint64_t psrc1_l = psrc1 & mask(halfSize);
528 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
529 uint64_t psrc2_l = op2 & mask(halfSize);
530 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
531 ((psrc1_l * psrc2_l) / shifter)) /shifter) +
533 if (bits(psrc1, dataSize * 8 - 1))
535 if (bits(op2, dataSize * 8 - 1))
540 if ((-ProdHi & mask(dataSize * 8)) !=
541 bits(ProdLow, dataSize * 8 - 1)) {
542 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
544 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
548 class Mul1u(WrRegOp):
550 ProdLow = psrc1 * op2;
551 int halfSize = (dataSize * 8) / 2;
552 uint64_t shifter = (1ULL << halfSize);
553 uint64_t psrc1_h = psrc1 / shifter;
554 uint64_t psrc1_l = psrc1 & mask(halfSize);
555 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
556 uint64_t psrc2_l = op2 & mask(halfSize);
557 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
558 ((psrc1_l * psrc2_l) / shifter)) / shifter) +
563 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
565 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
569 class Mulel(RdRegOp):
570 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
572 class Muleh(RdRegOp):
573 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
576 super(RdRegOp, self).__init__(dest, src1, \
577 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
578 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
580 # One or two bit divide
583 //These are temporaries so that modifying them later won't make
584 //the ISA parser think they're also sources.
585 uint64_t quotient = 0;
586 uint64_t remainder = psrc1;
587 //Similarly, this is a temporary so changing it doesn't make it
589 uint64_t divisor = op2;
590 //This is a temporary just for consistency and clarity.
591 uint64_t dividend = remainder;
593 divide(dividend, divisor, quotient, remainder);
594 //Record the final results.
595 Remainder = remainder;
603 uint64_t dividend = Remainder;
604 uint64_t divisor = Divisor;
605 uint64_t quotient = Quotient;
606 uint64_t remainder = dividend;
608 //If we overshot, do nothing. This lets us unrool division loops a
611 //Shift in bits from the low order portion of the dividend
612 while(dividend < divisor && remaining) {
613 dividend = (dividend << 1) | bits(SrcReg1, remaining - 1);
617 remainder = dividend;
619 divide(dividend, divisor, quotient, remainder);
621 //Keep track of how many bits there are still to pull in.
622 DestReg = merge(DestReg, remaining, dataSize);
623 //Record the final results
624 Remainder = remainder;
629 ccFlagBits = ccFlagBits | (ext & EZFBit);
631 ccFlagBits = ccFlagBits & ~(ext & EZFBit);
635 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
638 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
640 class Mov(CondRegOp):
641 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
642 else_code = 'DestReg = DestReg;'
648 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
649 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
652 // If the shift amount is zero, no flags should be modified.
654 //Zero out any flags we might modify. This way we only have to
655 //worry about setting them.
656 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
658 //Figure out if we -would- set the CF bits if requested.
659 if (shiftAmt <= dataSize * 8 &&
660 bits(SrcReg1, dataSize * 8 - shiftAmt)) {
663 //If some combination of the CF bits need to be set, set them.
664 if ((ext & (CFBit | ECFBit)) && CFBits)
665 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
666 //Figure out what the OF bit should be.
667 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
668 ccFlagBits = ccFlagBits | OFBit;
669 //Use the regular mechanisms to calculate the other flags.
670 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
671 DestReg, psrc1, op2);
677 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
678 // Because what happens to the bits shift -in- on a right shift
679 // is not defined in the C/C++ standard, we have to mask them out
680 // to be sure they're zero.
681 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
682 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
685 // If the shift amount is zero, no flags should be modified.
687 //Zero out any flags we might modify. This way we only have to
688 //worry about setting them.
689 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
690 //If some combination of the CF bits need to be set, set them.
691 if ((ext & (CFBit | ECFBit)) &&
692 shiftAmt <= dataSize * 8 &&
693 bits(SrcReg1, shiftAmt - 1)) {
694 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
696 //Figure out what the OF bit should be.
697 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
698 ccFlagBits = ccFlagBits | OFBit;
699 //Use the regular mechanisms to calculate the other flags.
700 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
701 DestReg, psrc1, op2);
707 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
708 // Because what happens to the bits shift -in- on a right shift
709 // is not defined in the C/C++ standard, we have to sign extend
710 // them manually to be sure.
711 uint64_t arithMask = (shiftAmt == 0) ? 0 :
712 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
713 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
716 // If the shift amount is zero, no flags should be modified.
718 //Zero out any flags we might modify. This way we only have to
719 //worry about setting them.
720 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
721 //If some combination of the CF bits need to be set, set them.
722 uint8_t effectiveShift =
723 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
724 if ((ext & (CFBit | ECFBit)) &&
725 bits(SrcReg1, effectiveShift - 1)) {
726 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
728 //Use the regular mechanisms to calculate the other flags.
729 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
730 DestReg, psrc1, op2);
737 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
738 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
741 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
742 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
743 DestReg = merge(DestReg, top | bottom, dataSize);
746 DestReg = merge(DestReg, DestReg, dataSize);
749 // If the shift amount is zero, no flags should be modified.
751 //Zero out any flags we might modify. This way we only have to
752 //worry about setting them.
753 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
754 //Find the most and second most significant bits of the result.
755 int msb = bits(DestReg, dataSize * 8 - 1);
756 int smsb = bits(DestReg, dataSize * 8 - 2);
757 //If some combination of the CF bits need to be set, set them.
758 if ((ext & (CFBit | ECFBit)) && msb)
759 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
760 //Figure out what the OF bit should be.
761 if ((ext & OFBit) && (msb ^ smsb))
762 ccFlagBits = ccFlagBits | OFBit;
763 //Use the regular mechanisms to calculate the other flags.
764 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
765 DestReg, psrc1, op2);
772 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
773 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
776 CCFlagBits flags = ccFlagBits;
777 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
778 if (realShiftAmt > 1)
779 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
780 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
781 DestReg = merge(DestReg, top | bottom, dataSize);
784 DestReg = merge(DestReg, DestReg, dataSize);
787 // If the shift amount is zero, no flags should be modified.
789 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
790 //Zero out any flags we might modify. This way we only have to
791 //worry about setting them.
792 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
793 //Figure out what the OF bit should be.
794 if ((ext & OFBit) && (origCFBit ^
795 bits(SrcReg1, dataSize * 8 - 1))) {
796 ccFlagBits = ccFlagBits | OFBit;
798 //If some combination of the CF bits need to be set, set them.
799 if ((ext & (CFBit | ECFBit)) &&
800 (realShiftAmt == 0) ? origCFBit :
801 bits(SrcReg1, realShiftAmt - 1)) {
802 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
804 //Use the regular mechanisms to calculate the other flags.
805 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
806 DestReg, psrc1, op2);
813 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
814 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
817 uint64_t top = psrc1 << realShiftAmt;
819 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
820 DestReg = merge(DestReg, top | bottom, dataSize);
823 DestReg = merge(DestReg, DestReg, dataSize);
826 // If the shift amount is zero, no flags should be modified.
828 //Zero out any flags we might modify. This way we only have to
829 //worry about setting them.
830 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
831 //The CF bits, if set, would be set to the lsb of the result.
832 int lsb = DestReg & 0x1;
833 int msb = bits(DestReg, dataSize * 8 - 1);
834 //If some combination of the CF bits need to be set, set them.
835 if ((ext & (CFBit | ECFBit)) && lsb)
836 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
837 //Figure out what the OF bit should be.
838 if ((ext & OFBit) && (msb ^ lsb))
839 ccFlagBits = ccFlagBits | OFBit;
840 //Use the regular mechanisms to calculate the other flags.
841 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
842 DestReg, psrc1, op2);
849 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
850 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
853 CCFlagBits flags = ccFlagBits;
854 uint64_t top = psrc1 << realShiftAmt;
855 uint64_t bottom = flags.cf << (realShiftAmt - 1);
858 bits(psrc1, dataSize * 8 - 1,
859 dataSize * 8 - realShiftAmt + 1);
860 DestReg = merge(DestReg, top | bottom, dataSize);
863 DestReg = merge(DestReg, DestReg, dataSize);
866 // If the shift amount is zero, no flags should be modified.
868 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
869 //Zero out any flags we might modify. This way we only have to
870 //worry about setting them.
871 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
872 int msb = bits(DestReg, dataSize * 8 - 1);
873 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
874 //If some combination of the CF bits need to be set, set them.
875 if ((ext & (CFBit | ECFBit)) &&
876 (realShiftAmt == 0) ? origCFBit : CFBits)
877 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
878 //Figure out what the OF bit should be.
879 if ((ext & OFBit) && (msb ^ CFBits))
880 ccFlagBits = ccFlagBits | OFBit;
881 //Use the regular mechanisms to calculate the other flags.
882 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
883 DestReg, psrc1, op2);
889 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
890 uint8_t dataBits = dataSize * 8;
891 uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
893 if (realShiftAmt == 0) {
895 } else if (realShiftAmt < dataBits) {
896 result = (psrc1 << realShiftAmt) |
897 (DoubleBits >> (dataBits - realShiftAmt));
899 result = (DoubleBits << (realShiftAmt - dataBits)) |
900 (psrc1 >> (2 * dataBits - realShiftAmt));
902 DestReg = merge(DestReg, result, dataSize);
905 // If the shift amount is zero, no flags should be modified.
907 //Zero out any flags we might modify. This way we only have to
908 //worry about setting them.
909 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
911 //Figure out if we -would- set the CF bits if requested.
912 if ((realShiftAmt == 0 &&
913 bits(DoubleBits, 0)) ||
914 (realShiftAmt <= dataBits &&
915 bits(SrcReg1, dataBits - realShiftAmt)) ||
916 (realShiftAmt > dataBits &&
917 bits(DoubleBits, 2 * dataBits - realShiftAmt))) {
920 //If some combination of the CF bits need to be set, set them.
921 if ((ext & (CFBit | ECFBit)) && CFBits)
922 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
923 //Figure out what the OF bit should be.
924 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
925 bits(result, dataBits - 1)))
926 ccFlagBits = ccFlagBits | OFBit;
927 //Use the regular mechanisms to calculate the other flags.
928 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
929 DestReg, psrc1, op2);
935 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
936 uint8_t dataBits = dataSize * 8;
937 uint8_t realShiftAmt = shiftAmt % (2 * dataBits);
939 if (realShiftAmt == 0) {
941 } else if (realShiftAmt < dataBits) {
942 // Because what happens to the bits shift -in- on a right
943 // shift is not defined in the C/C++ standard, we have to
944 // mask them out to be sure they're zero.
945 uint64_t logicalMask = mask(dataBits - realShiftAmt);
946 result = ((psrc1 >> realShiftAmt) & logicalMask) |
947 (DoubleBits << (dataBits - realShiftAmt));
949 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt);
950 result = ((DoubleBits >> (realShiftAmt - dataBits)) &
952 (psrc1 << (2 * dataBits - realShiftAmt));
954 DestReg = merge(DestReg, result, dataSize);
957 // If the shift amount is zero, no flags should be modified.
959 //Zero out any flags we might modify. This way we only have to
960 //worry about setting them.
961 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
963 //If some combination of the CF bits need to be set, set them.
964 if ((realShiftAmt == 0 &&
965 bits(DoubleBits, dataBits - 1)) ||
966 (realShiftAmt <= dataBits &&
967 bits(SrcReg1, realShiftAmt - 1)) ||
968 (realShiftAmt > dataBits &&
969 bits(DoubleBits, realShiftAmt - dataBits - 1))) {
972 //If some combination of the CF bits need to be set, set them.
973 if ((ext & (CFBit | ECFBit)) && CFBits)
974 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
975 //Figure out what the OF bit should be.
976 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
977 bits(result, dataBits - 1)))
978 ccFlagBits = ccFlagBits | OFBit;
979 //Use the regular mechanisms to calculate the other flags.
980 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
981 DestReg, psrc1, op2);
986 code = 'DoubleBits = psrc1 ^ op2;'
988 class Wrip(WrRegOp, CondRegOp):
989 code = 'RIP = psrc1 + sop2 + CSBase'
990 else_code="RIP = RIP;"
992 class Wruflags(WrRegOp):
993 code = 'ccFlagBits = psrc1 ^ op2'
995 class Wrflags(WrRegOp):
997 MiscReg newFlags = psrc1 ^ op2;
998 MiscReg userFlagMask = 0xDD5;
999 // Get only the user flags
1000 ccFlagBits = newFlags & userFlagMask;
1001 // Get everything else
1002 nccFlagBits = newFlags & ~userFlagMask;
1005 class Rdip(RdRegOp):
1006 code = 'DestReg = RIP - CSBase'
1008 class Ruflags(RdRegOp):
1009 code = 'DestReg = ccFlagBits'
1011 class Rflags(RdRegOp):
1012 code = 'DestReg = ccFlagBits | nccFlagBits'
1014 class Ruflag(RegOp):
1016 int flag = bits(ccFlagBits, imm8);
1017 DestReg = merge(DestReg, flag, dataSize);
1018 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1019 (ccFlagBits & ~EZFBit);
1021 def __init__(self, dest, imm, flags=None, \
1022 dataSize="env.dataSize"):
1023 super(Ruflag, self).__init__(dest, \
1024 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1028 MiscReg flagMask = 0x3F7FDD5;
1029 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
1030 int flag = bits(flags, imm8);
1031 DestReg = merge(DestReg, flag, dataSize);
1032 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1033 (ccFlagBits & ~EZFBit);
1035 def __init__(self, dest, imm, flags=None, \
1036 dataSize="env.dataSize"):
1037 super(Rflag, self).__init__(dest, \
1038 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1043 // Mask the bit position so that it wraps.
1044 int bitPos = op2 & (dataSize * 8 - 1);
1045 int sign_bit = bits(val, bitPos, bitPos);
1046 uint64_t maskVal = mask(bitPos+1);
1047 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1048 DestReg = merge(DestReg, val, dataSize);
1052 ccFlagBits = ccFlagBits &
1053 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
1055 ccFlagBits = ccFlagBits |
1056 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
1060 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1063 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1064 super(Rddr, self).__init__(dest, \
1065 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1069 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
1070 fault = new InvalidOpcode();
1071 } else if (dr7.gd) {
1072 fault = new DebugException();
1074 DestReg = merge(DestReg, DebugSrc1, dataSize);
1079 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1080 super(Wrdr, self).__init__(dest, \
1081 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1085 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
1086 fault = new InvalidOpcode();
1087 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) &&
1088 machInst.mode.mode == LongMode) {
1089 fault = new GeneralProtection(0);
1090 } else if (dr7.gd) {
1091 fault = new DebugException();
1098 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1099 super(Rdcr, self).__init__(dest, \
1100 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1102 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
1103 fault = new InvalidOpcode();
1105 DestReg = merge(DestReg, ControlSrc1, dataSize);
1110 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1111 super(Wrcr, self).__init__(dest, \
1112 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1114 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1115 fault = new InvalidOpcode();
1117 // There are *s in the line below so it doesn't confuse the
1118 // parser. They may be unnecessary.
1119 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
1120 MiscReg newVal = psrc1;
1122 // Check for any modifications that would cause a fault.
1129 if (bits(newVal, 63, 32) ||
1130 (!cr0.pe && cr0.pg) ||
1131 (!cr0.cd && cr0.nw) ||
1132 (cr0.pg && efer.lme && !oldCr4.pae))
1133 fault = new GeneralProtection(0);
1143 // PAE can't be disabled in long mode.
1144 if (bits(newVal, 63, 11) ||
1145 (machInst.mode.mode == LongMode && !cr4.pae))
1146 fault = new GeneralProtection(0);
1151 if (bits(newVal, 63, 4))
1152 fault = new GeneralProtection(0);
1155 panic("Unrecognized control register %d.\\n", dest);
1157 ControlDest = newVal;
1161 # Microops for manipulating segmentation registers
1162 class SegOp(CondRegOp):
1164 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1165 super(SegOp, self).__init__(dest, \
1166 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1168 class Wrbase(SegOp):
1170 SegBaseDest = psrc1;
1173 class Wrlimit(SegOp):
1175 SegLimitDest = psrc1;
1183 class WrAttr(SegOp):
1185 SegAttrDest = psrc1;
1188 class Rdbase(SegOp):
1190 DestReg = merge(DestReg, SegBaseSrc1, dataSize);
1193 class Rdlimit(SegOp):
1195 DestReg = merge(DestReg, SegLimitSrc1, dataSize);
1198 class RdAttr(SegOp):
1200 DestReg = merge(DestReg, SegAttrSrc1, dataSize);
1205 DestReg = merge(DestReg, SegSelSrc1, dataSize);
1209 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1210 super(Rdval, self).__init__(dest, src1, \
1211 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1213 DestReg = MiscRegSrc1;
1217 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1218 super(Wrval, self).__init__(dest, src1, \
1219 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1221 MiscRegDest = SrcReg1;
1225 def __init__(self, dest, src1, src2=0,
1226 flags=None, dataSize="env.dataSize"):
1227 super(Chks, self).__init__(dest,
1228 src1, src2, flags, dataSize)
1230 // The selector is in source 1 and can be at most 16 bits.
1231 SegSelector selector = DestReg;
1232 SegDescriptor desc = SrcReg1;
1233 HandyM5Reg m5reg = M5Reg;
1240 // Make sure it's the right type
1241 if (desc.s == 0 || desc.type.codeOrData != 1) {
1242 fault = new GeneralProtection(0);
1243 } else if (m5reg.cpl != desc.dpl) {
1244 fault = new GeneralProtection(0);
1247 case SegCallGateCheck:
1248 panic("CS checks for far calls/jumps through call gates"
1249 "not implemented.\\n");
1251 case SegSoftIntGateCheck:
1252 // Check permissions.
1253 if (desc.dpl < m5reg.cpl) {
1254 fault = new GeneralProtection(selector);
1257 // Fall through on purpose
1258 case SegIntGateCheck:
1259 // Make sure the gate's the right type.
1260 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
1261 ((desc.type & 0x6) != 0x6)) {
1262 fault = new GeneralProtection(0);
1266 if (selector.si || selector.ti) {
1268 fault = new StackFault(selector);
1271 if ((m5reg.submode != SixtyFourBitMode ||
1274 desc.type.codeOrData == 0 && desc.type.w) ||
1275 (desc.dpl != m5reg.cpl) ||
1276 (selector.rpl != m5reg.cpl)) {
1277 fault = new GeneralProtection(selector);
1283 if ((!selector.si && !selector.ti) ||
1284 (selector.rpl < m5reg.cpl) ||
1285 !(desc.s == 1 && desc.type.codeOrData == 1) ||
1286 (!desc.type.c && desc.dpl != selector.rpl) ||
1287 (desc.type.c && desc.dpl > selector.rpl)) {
1288 fault = new GeneralProtection(selector);
1289 } else if (!desc.p) {
1290 fault = new SegmentNotPresent(selector);
1295 if (m5reg.mode == LongMode) {
1296 if (desc.l != 1 || desc.d != 0) {
1297 fault = new GeneralProtection(selector);
1300 panic("Interrupt CS checks not implemented "
1301 "in legacy mode.\\n");
1305 if (!selector.si || selector.ti) {
1306 fault = new GeneralProtection(selector);
1311 fault = new SegmentNotPresent(selector);
1312 } else if (!(desc.type == 0x9 ||
1314 m5reg.mode != LongMode))) {
1315 fault = new GeneralProtection(selector);
1320 fault = new GeneralProtection(selector);
1325 fault = new SegmentNotPresent(selector);
1326 } else if (desc.type != 0x2) {
1327 fault = new GeneralProtection(selector);
1331 panic("Undefined segment check type.\\n");
1335 // Check for a NULL selector and set ZF,EZF appropriately.
1336 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1337 if (!selector.si && !selector.ti)
1338 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1343 SegDescriptor desc = SrcReg1;
1345 uint64_t target = bits(SrcReg2, 31, 0) << 32;
1348 case AvailableTSS64:
1350 replaceBits(target, 23, 0, desc.baseLow);
1351 replaceBits(target, 31, 24, desc.baseHigh);
1356 replaceBits(target, 15, 0, bits(desc, 15, 0));
1357 replaceBits(target, 31, 16, bits(desc, 63, 48));
1360 panic("Wrdh used with wrong descriptor type!\\n");
1365 class Wrtsc(WrRegOp):
1370 class Rdtsc(RdRegOp):
1375 class Rdm5reg(RdRegOp):
1382 SegDescriptor desc = SrcReg1;
1383 SegSelector selector = SrcReg2;
1384 if (selector.si || selector.ti) {
1386 panic("Segment not present.\\n");
1388 attr.dpl = desc.dpl;
1390 attr.defaultSize = desc.d;
1391 attr.longMode = desc.l;
1392 attr.avl = desc.avl;
1393 attr.granularity = desc.g;
1394 attr.present = desc.p;
1395 attr.system = desc.s;
1396 attr.type = desc.type;
1398 // The expand down bit happens to be set for gates.
1400 panic("Gate descriptor encountered.\\n");
1404 attr.expandDown = 0;
1406 if (desc.type.codeOrData) {
1407 attr.expandDown = 0;
1408 attr.readable = desc.type.r;
1411 attr.expandDown = desc.type.e;
1413 attr.writable = desc.type.w;
1416 Addr base = desc.baseLow | (desc.baseHigh << 24);
1417 Addr limit = desc.limitLow | (desc.limitHigh << 16);
1419 limit = (limit << 12) | mask(12);
1421 SegLimitDest = limit;
1424 SegBaseDest = SegBaseDest;
1425 SegLimitDest = SegLimitDest;
1426 SegAttrDest = SegAttrDest;