1 // Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2 // All rights reserved.
4 // The license below extends only to copyright in the software and shall
5 // not be construed as granting a license to any other intellectual
6 // property including but not limited to intellectual property relating
7 // to a hardware implementation of the functionality of the software
8 // licensed hereunder. You may use the software subject to the license
9 // terms below provided that you ensure that this notice is replicated
10 // unmodified and in its entirety in all distributions of the software,
11 // modified or unmodified, in source code or in binary form.
13 // Redistribution and use in source and binary forms, with or without
14 // modification, are permitted provided that the following conditions are
15 // met: redistributions of source code must retain the above copyright
16 // notice, this list of conditions and the following disclaimer;
17 // redistributions in binary form must reproduce the above copyright
18 // notice, this list of conditions and the following disclaimer in the
19 // documentation and/or other materials provided with the distribution;
20 // neither the name of the copyright holders nor the names of its
21 // contributors may be used to endorse or promote products derived from
22 // this software without specific prior written permission.
24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 // Authors: Gabe Black
38 //////////////////////////////////////////////////////////////////////////
40 // RegOp Microop templates
42 //////////////////////////////////////////////////////////////////////////
44 def template MicroRegOpExecute {{
45 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
46 Trace::InstRecord *traceData) const
48 Fault fault = NoFault;
50 DPRINTF(X86, "The data size is %d\n", dataSize);
54 IntReg result M5_VAR_USED;
66 //Write the resulting state to the execution context
75 def template MicroRegOpImmExecute {{
76 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
77 Trace::InstRecord *traceData) const
79 Fault fault = NoFault;
84 IntReg result M5_VAR_USED;
96 //Write the resulting state to the execution context
105 def template MicroRegOpDeclare {{
106 class %(class_name)s : public %(base_class)s
109 %(class_name)s(ExtMachInst _machInst,
110 const char * instMnem, uint64_t setFlags,
111 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
112 uint8_t _dataSize, uint16_t _ext);
118 def template MicroRegOpImmDeclare {{
120 class %(class_name)s : public %(base_class)s
123 %(class_name)s(ExtMachInst _machInst,
124 const char * instMnem, uint64_t setFlags,
125 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
126 uint8_t _dataSize, uint16_t _ext);
132 def template MicroRegOpConstructor {{
133 inline %(class_name)s::%(class_name)s(
134 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
135 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
136 uint8_t _dataSize, uint16_t _ext) :
137 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
138 _src1, _src2, _dest, _dataSize, _ext,
142 %(cond_control_flag_init)s;
146 def template MicroRegOpImmConstructor {{
147 inline %(class_name)s::%(class_name)s(
148 ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
149 InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest,
150 uint8_t _dataSize, uint16_t _ext) :
151 %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
152 _src1, _imm8, _dest, _dataSize, _ext,
156 %(cond_control_flag_init)s;
162 divide(uint64_t dividend, uint64_t divisor,
163 uint64_t "ient, uint64_t &remainder);
165 enum SegmentSelectorCheck {
166 SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
167 SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck,
168 SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck
171 enum LongModeDescriptorType {
183 divide(uint64_t dividend, uint64_t divisor,
184 uint64_t "ient, uint64_t &remainder)
186 //Check for divide by zero.
187 assert(divisor != 0);
188 //If the divisor is bigger than the dividend, don't do anything.
189 if (divisor <= dividend) {
190 //Shift the divisor so it's msb lines up with the dividend.
191 int dividendMsb = findMsbSet(dividend);
192 int divisorMsb = findMsbSet(divisor);
193 int shift = dividendMsb - divisorMsb;
195 //Compute what we'll add to the quotient if the divisor isn't
196 //now larger than the dividend.
197 uint64_t quotientBit = 1;
198 quotientBit <<= shift;
199 //If we need to step back a bit (no pun intended) because the
200 //divisor got too to large, do that here. This is the "or two"
201 //part of one or two bit division.
202 if (divisor > dividend) {
206 //Decrement the remainder and increment the quotient.
207 quotient += quotientBit;
208 remainder -= divisor;
214 # Make these empty strings so that concatenating onto
215 # them will always work.
221 MicroRegOpImmDeclare,
222 MicroRegOpImmConstructor,
223 MicroRegOpImmExecute)
227 MicroRegOpConstructor,
230 class RegOpMeta(type):
231 def buildCppClasses(self, name, Name, suffix, code, big_code, \
232 flag_code, cond_check, else_code, cond_control_flag_init):
234 # Globals to stick the output in
236 global decoder_output
239 # Stick all the code together so it can be searched at once
240 allCode = "|".join((code, flag_code, cond_check, else_code,
241 cond_control_flag_init))
242 allBigCode = "|".join((big_code, flag_code, cond_check, else_code,
243 cond_control_flag_init))
245 # If op2 is used anywhere, make register and immediate versions
247 matcher = re.compile(r"(?<!\w)(?P<prefix>s?)op2(?P<typeQual>_[^\W_]+)?")
248 match = matcher.search(allCode + allBigCode)
251 if match.group("typeQual"):
252 typeQual = match.group("typeQual")
253 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
254 self.buildCppClasses(name, Name, suffix,
255 matcher.sub(src2_name, code),
256 matcher.sub(src2_name, big_code),
257 matcher.sub(src2_name, flag_code),
258 matcher.sub(src2_name, cond_check),
259 matcher.sub(src2_name, else_code),
260 matcher.sub(src2_name, cond_control_flag_init))
261 imm_name = "%simm8" % match.group("prefix")
262 self.buildCppClasses(name + "i", Name, suffix + "Imm",
263 matcher.sub(imm_name, code),
264 matcher.sub(imm_name, big_code),
265 matcher.sub(imm_name, flag_code),
266 matcher.sub(imm_name, cond_check),
267 matcher.sub(imm_name, else_code),
268 matcher.sub(imm_name, cond_control_flag_init))
271 # If there's something optional to do with flags, generate
272 # a version without it and fix up this version to use it.
273 if flag_code != "" or cond_check != "true":
274 self.buildCppClasses(name, Name, suffix,
275 code, big_code, "", "true", else_code, "")
276 suffix = "Flags" + suffix
278 # If psrc1 or psrc2 is used, we need to actually insert code to
280 for (big, all) in ((False, allCode), (True, allBigCode)):
283 ("(?<!\w)psrc1(?!\w)",
284 "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);"),
285 ("(?<!\w)psrc2(?!\w)",
286 "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);"),
287 ("(?<!\w)spsrc1(?!\w)",
288 "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);"),
289 ("(?<!\w)spsrc2(?!\w)",
290 "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);"),
291 ("(?<!\w)simm8(?!\w)",
292 "int8_t simm8 = imm8;")):
293 matcher = re.compile(rex)
294 if matcher.search(all):
295 prefix += decl + "\n"
298 big_code = prefix + big_code
302 base = "X86ISA::RegOp"
304 # If imm8 shows up in the code, use the immediate templates, if
305 # not, hopefully the register ones will be correct.
306 templates = regTemplates
307 matcher = re.compile("(?<!\w)s?imm8(?!\w)")
308 if matcher.search(allCode):
310 templates = immTemplates
312 # Get everything ready for the substitution
313 iops = [InstObjParams(name, Name + suffix, base,
315 "flag_code" : flag_code,
316 "cond_check" : cond_check,
317 "else_code" : else_code,
318 "cond_control_flag_init" : cond_control_flag_init})]
320 iops += [InstObjParams(name, Name + suffix + "Big", base,
322 "flag_code" : flag_code,
323 "cond_check" : cond_check,
324 "else_code" : else_code,
325 "cond_control_flag_init" :
326 cond_control_flag_init})]
328 # Generate the actual code (finally!)
330 header_output += templates[0].subst(iop)
331 decoder_output += templates[1].subst(iop)
332 exec_output += templates[2].subst(iop)
335 def __new__(mcls, Name, bases, dict):
338 if "abstract" in dict:
339 abstract = dict['abstract']
342 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
345 cls.base_mnemonic = name
347 big_code = cls.big_code
348 flag_code = cls.flag_code
349 cond_check = cls.cond_check
350 else_code = cls.else_code
351 cond_control_flag_init = cls.cond_control_flag_init
353 # Set up the C++ classes
354 mcls.buildCppClasses(cls, name, Name, "", code, big_code,
355 flag_code, cond_check, else_code,
356 cond_control_flag_init)
358 # Hook into the microassembler dict
359 global microopClasses
360 microopClasses[name] = cls
362 allCode = "|".join((code, flag_code, cond_check, else_code,
363 cond_control_flag_init))
365 # If op2 is used anywhere, make register and immediate versions
367 matcher = re.compile(r"op2(?P<typeQual>_[^\W_]+)?")
368 if matcher.search(allCode):
369 microopClasses[name + 'i'] = cls
373 class RegOp(X86Microop):
374 __metaclass__ = RegOpMeta
375 # This class itself doesn't act as a microop
378 # Default template parameter values
383 cond_control_flag_init = ""
385 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
390 self.dataSize = dataSize
394 if not isinstance(flags, (list, tuple)):
395 raise Exception, "flags must be a list or tuple of flags"
396 self.ext = " | ".join(flags)
397 self.className += "Flags"
399 def getAllocator(self, microFlags):
400 if self.big_code != "":
401 className = self.className
402 if self.mnemonic == self.base_mnemonic + 'i':
405 (%(dataSize)s >= 4) ?
406 (StaticInstPtr)(new %(class_name)sBig(machInst,
407 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
408 %(dest)s, %(dataSize)s, %(ext)s)) :
409 (StaticInstPtr)(new %(class_name)s(machInst,
410 macrocodeBlock, %(flags)s, %(src1)s, %(op2)s,
411 %(dest)s, %(dataSize)s, %(ext)s))
413 allocator = allocString % {
414 "class_name" : className,
415 "flags" : self.microFlagsText(microFlags),
416 "src1" : self.src1, "op2" : self.op2,
418 "dataSize" : self.dataSize,
422 className = self.className
423 if self.mnemonic == self.base_mnemonic + 'i':
425 allocator = '''new %(class_name)s(machInst, macrocodeBlock,
426 %(flags)s, %(src1)s, %(op2)s, %(dest)s,
427 %(dataSize)s, %(ext)s)''' % {
428 "class_name" : className,
429 "flags" : self.microFlagsText(microFlags),
430 "src1" : self.src1, "op2" : self.op2,
432 "dataSize" : self.dataSize,
436 class LogicRegOp(RegOp):
439 //Don't have genFlags handle the OF or CF bits
440 uint64_t mask = CFBit | ECFBit | OFBit;
441 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2);
442 //If a logic microop wants to set these, it wants to set them to 0.
443 ccFlagBits &= ~(CFBit & ext);
444 ccFlagBits &= ~(ECFBit & ext);
445 ccFlagBits &= ~(OFBit & ext);
448 class FlagRegOp(RegOp):
451 "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);"
453 class SubRegOp(RegOp):
456 "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);"
458 class CondRegOp(RegOp):
460 cond_check = "checkCondition(ccFlagBits, ext)"
461 cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
463 class RdRegOp(RegOp):
465 def __init__(self, dest, src1=None, dataSize="env.dataSize"):
468 super(RdRegOp, self).__init__(dest, src1, \
469 "InstRegIndex(NUM_INTREGS)", None, dataSize)
471 class WrRegOp(RegOp):
473 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
474 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
475 src1, src2, flags, dataSize)
477 class Add(FlagRegOp):
478 code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);'
479 big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);'
481 class Or(LogicRegOp):
482 code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);'
483 big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);'
485 class Adc(FlagRegOp):
487 CCFlagBits flags = ccFlagBits;
488 DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize);
491 CCFlagBits flags = ccFlagBits;
492 DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
497 CCFlagBits flags = ccFlagBits;
498 DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize);
501 CCFlagBits flags = ccFlagBits;
502 DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
505 class And(LogicRegOp):
506 code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)'
507 big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)'
510 code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)'
511 big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)'
513 class Xor(LogicRegOp):
514 code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)'
515 big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)'
517 class Mul1s(WrRegOp):
519 ProdLow = psrc1 * op2;
520 int halfSize = (dataSize * 8) / 2;
521 uint64_t shifter = (ULL(1) << halfSize);
523 uint64_t psrc1_h = psrc1 / shifter;
524 uint64_t psrc1_l = psrc1 & mask(halfSize);
525 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
526 uint64_t psrc2_l = op2 & mask(halfSize);
527 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
528 ((psrc1_l * psrc2_l) / shifter)) /shifter) +
530 if (bits(psrc1, dataSize * 8 - 1))
532 if (bits(op2, dataSize * 8 - 1))
537 if ((-ProdHi & mask(dataSize * 8)) !=
538 bits(ProdLow, dataSize * 8 - 1)) {
539 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
541 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
545 class Mul1u(WrRegOp):
547 ProdLow = psrc1 * op2;
548 int halfSize = (dataSize * 8) / 2;
549 uint64_t shifter = (ULL(1) << halfSize);
550 uint64_t psrc1_h = psrc1 / shifter;
551 uint64_t psrc1_l = psrc1 & mask(halfSize);
552 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize);
553 uint64_t psrc2_l = op2 & mask(halfSize);
554 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
555 ((psrc1_l * psrc2_l) / shifter)) / shifter) +
560 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
562 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
566 class Mulel(RdRegOp):
567 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
568 big_code = 'DestReg = ProdLow & mask(dataSize * 8);'
570 class Muleh(RdRegOp):
571 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
574 super(RdRegOp, self).__init__(dest, src1, \
575 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
576 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
577 big_code = 'DestReg = ProdHi & mask(dataSize * 8);'
579 # One or two bit divide
582 //These are temporaries so that modifying them later won't make
583 //the ISA parser think they're also sources.
584 uint64_t quotient = 0;
585 uint64_t remainder = psrc1;
586 //Similarly, this is a temporary so changing it doesn't make it
588 uint64_t divisor = op2;
589 //This is a temporary just for consistency and clarity.
590 uint64_t dividend = remainder;
593 fault = new DivideByZero;
595 divide(dividend, divisor, quotient, remainder);
596 //Record the final results.
597 Remainder = remainder;
606 uint64_t dividend = Remainder;
607 uint64_t divisor = Divisor;
608 uint64_t quotient = Quotient;
609 uint64_t remainder = dividend;
611 //If we overshot, do nothing. This lets us unrool division loops a
614 fault = new DivideByZero;
615 } else if (remaining) {
616 if (divisor & (ULL(1) << 63)) {
617 while (remaining && !(dividend & (ULL(1) << 63))) {
618 dividend = (dividend << 1) |
619 bits(SrcReg1, remaining - 1);
623 if (dividend & (ULL(1) << 63)) {
624 bool highBit = false;
625 if (dividend < divisor && remaining) {
627 dividend = (dividend << 1) |
628 bits(SrcReg1, remaining - 1);
632 if (highBit || divisor <= dividend) {
637 remainder = dividend;
639 //Shift in bits from the low order portion of the dividend
640 while (dividend < divisor && remaining) {
641 dividend = (dividend << 1) |
642 bits(SrcReg1, remaining - 1);
646 remainder = dividend;
648 divide(dividend, divisor, quotient, remainder);
651 //Keep track of how many bits there are still to pull in.
653 //Record the final results
654 Remainder = remainder;
657 code = divCode % "DestReg = merge(DestReg, remaining, dataSize);"
658 big_code = divCode % "DestReg = remaining & mask(dataSize * 8);"
661 ccFlagBits = ccFlagBits | (ext & EZFBit);
663 ccFlagBits = ccFlagBits & ~(ext & EZFBit);
667 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
668 big_code = 'DestReg = Quotient & mask(dataSize * 8);'
671 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
672 big_code = 'DestReg = Remainder & mask(dataSize * 8);'
674 class Mov(CondRegOp):
675 code = 'DestReg = merge(SrcReg1, op2, dataSize)'
676 else_code = 'DestReg = DestReg;'
682 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
683 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
686 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
687 DestReg = (psrc1 << shiftAmt) & mask(dataSize * 8);
690 // If the shift amount is zero, no flags should be modified.
692 //Zero out any flags we might modify. This way we only have to
693 //worry about setting them.
694 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
696 //Figure out if we -would- set the CF bits if requested.
697 if (shiftAmt <= dataSize * 8 &&
698 bits(SrcReg1, dataSize * 8 - shiftAmt)) {
701 //If some combination of the CF bits need to be set, set them.
702 if ((ext & (CFBit | ECFBit)) && CFBits)
703 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
704 //Figure out what the OF bit should be.
705 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
706 ccFlagBits = ccFlagBits | OFBit;
707 //Use the regular mechanisms to calculate the other flags.
708 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
709 DestReg, psrc1, op2);
714 # Because what happens to the bits shift -in- on a right shift
715 # is not defined in the C/C++ standard, we have to mask them out
716 # to be sure they're zero.
718 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
719 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
720 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
723 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
724 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
725 DestReg = (psrc1 >> shiftAmt) & logicalMask;
728 // If the shift amount is zero, no flags should be modified.
730 //Zero out any flags we might modify. This way we only have to
731 //worry about setting them.
732 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
733 //If some combination of the CF bits need to be set, set them.
734 if ((ext & (CFBit | ECFBit)) &&
735 shiftAmt <= dataSize * 8 &&
736 bits(SrcReg1, shiftAmt - 1)) {
737 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
739 //Figure out what the OF bit should be.
740 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
741 ccFlagBits = ccFlagBits | OFBit;
742 //Use the regular mechanisms to calculate the other flags.
743 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
744 DestReg, psrc1, op2);
749 # Because what happens to the bits shift -in- on a right shift
750 # is not defined in the C/C++ standard, we have to sign extend
751 # them manually to be sure.
753 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
754 uint64_t arithMask = (shiftAmt == 0) ? 0 :
755 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
756 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
759 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
760 uint64_t arithMask = (shiftAmt == 0) ? 0 :
761 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
762 DestReg = ((psrc1 >> shiftAmt) | arithMask) & mask(dataSize * 8);
765 // If the shift amount is zero, no flags should be modified.
767 //Zero out any flags we might modify. This way we only have to
768 //worry about setting them.
769 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
770 //If some combination of the CF bits need to be set, set them.
771 uint8_t effectiveShift =
772 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
773 if ((ext & (CFBit | ECFBit)) &&
774 bits(SrcReg1, effectiveShift - 1)) {
775 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
777 //Use the regular mechanisms to calculate the other flags.
778 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
779 DestReg, psrc1, op2);
786 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
787 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
789 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt);
790 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt);
791 DestReg = merge(DestReg, top | bottom, dataSize);
793 DestReg = merge(DestReg, DestReg, dataSize);
796 // If the shift amount is zero, no flags should be modified.
798 //Zero out any flags we might modify. This way we only have to
799 //worry about setting them.
800 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
801 //Find the most and second most significant bits of the result.
802 int msb = bits(DestReg, dataSize * 8 - 1);
803 int smsb = bits(DestReg, dataSize * 8 - 2);
804 //If some combination of the CF bits need to be set, set them.
805 if ((ext & (CFBit | ECFBit)) && msb)
806 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
807 //Figure out what the OF bit should be.
808 if ((ext & OFBit) && (msb ^ smsb))
809 ccFlagBits = ccFlagBits | OFBit;
810 //Use the regular mechanisms to calculate the other flags.
811 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
812 DestReg, psrc1, op2);
819 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
820 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
822 CCFlagBits flags = ccFlagBits;
823 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt);
824 if (realShiftAmt > 1)
825 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1);
826 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt);
827 DestReg = merge(DestReg, top | bottom, dataSize);
829 DestReg = merge(DestReg, DestReg, dataSize);
832 // If the shift amount is zero, no flags should be modified.
834 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
835 //Zero out any flags we might modify. This way we only have to
836 //worry about setting them.
837 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
838 //Figure out what the OF bit should be.
839 if ((ext & OFBit) && (origCFBit ^
840 bits(SrcReg1, dataSize * 8 - 1))) {
841 ccFlagBits = ccFlagBits | OFBit;
843 //If some combination of the CF bits need to be set, set them.
844 if ((ext & (CFBit | ECFBit)) &&
845 (realShiftAmt == 0) ? origCFBit :
846 bits(SrcReg1, realShiftAmt - 1)) {
847 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
849 //Use the regular mechanisms to calculate the other flags.
850 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
851 DestReg, psrc1, op2);
858 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
859 uint8_t realShiftAmt = shiftAmt % (dataSize * 8);
861 uint64_t top = psrc1 << realShiftAmt;
863 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt);
864 DestReg = merge(DestReg, top | bottom, dataSize);
866 DestReg = merge(DestReg, DestReg, dataSize);
869 // If the shift amount is zero, no flags should be modified.
871 //Zero out any flags we might modify. This way we only have to
872 //worry about setting them.
873 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
874 //The CF bits, if set, would be set to the lsb of the result.
875 int lsb = DestReg & 0x1;
876 int msb = bits(DestReg, dataSize * 8 - 1);
877 //If some combination of the CF bits need to be set, set them.
878 if ((ext & (CFBit | ECFBit)) && lsb)
879 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
880 //Figure out what the OF bit should be.
881 if ((ext & OFBit) && (msb ^ lsb))
882 ccFlagBits = ccFlagBits | OFBit;
883 //Use the regular mechanisms to calculate the other flags.
884 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
885 DestReg, psrc1, op2);
892 (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
893 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1);
895 CCFlagBits flags = ccFlagBits;
896 uint64_t top = psrc1 << realShiftAmt;
897 uint64_t bottom = flags.cf << (realShiftAmt - 1);
900 bits(psrc1, dataSize * 8 - 1,
901 dataSize * 8 - realShiftAmt + 1);
902 DestReg = merge(DestReg, top | bottom, dataSize);
904 DestReg = merge(DestReg, DestReg, dataSize);
907 // If the shift amount is zero, no flags should be modified.
909 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0;
910 //Zero out any flags we might modify. This way we only have to
911 //worry about setting them.
912 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
913 int msb = bits(DestReg, dataSize * 8 - 1);
914 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt);
915 //If some combination of the CF bits need to be set, set them.
916 if ((ext & (CFBit | ECFBit)) &&
917 (realShiftAmt == 0) ? origCFBit : CFBits)
918 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
919 //Figure out what the OF bit should be.
920 if ((ext & OFBit) && (msb ^ CFBits))
921 ccFlagBits = ccFlagBits | OFBit;
922 //Use the regular mechanisms to calculate the other flags.
923 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
924 DestReg, psrc1, op2);
930 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
931 uint8_t dataBits = dataSize * 8;
932 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
934 if (realShiftAmt == 0) {
936 } else if (realShiftAmt < dataBits) {
937 result = (psrc1 << realShiftAmt) |
938 (DoubleBits >> (dataBits - realShiftAmt));
940 result = (DoubleBits << (realShiftAmt - dataBits)) |
941 (psrc1 >> (2 * dataBits - realShiftAmt));
945 code = sldCode % "DestReg = merge(DestReg, result, dataSize);"
946 big_code = sldCode % "DestReg = result & mask(dataSize * 8);"
948 // If the shift amount is zero, no flags should be modified.
950 //Zero out any flags we might modify. This way we only have to
951 //worry about setting them.
952 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
954 //Figure out if we -would- set the CF bits if requested.
955 if ((realShiftAmt == 0 &&
956 bits(DoubleBits, 0)) ||
957 (realShiftAmt <= dataBits &&
958 bits(SrcReg1, dataBits - realShiftAmt)) ||
959 (realShiftAmt > dataBits &&
960 bits(DoubleBits, 2 * dataBits - realShiftAmt))) {
963 //If some combination of the CF bits need to be set, set them.
964 if ((ext & (CFBit | ECFBit)) && CFBits)
965 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
966 //Figure out what the OF bit should be.
967 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
968 bits(result, dataBits - 1)))
969 ccFlagBits = ccFlagBits | OFBit;
970 //Use the regular mechanisms to calculate the other flags.
971 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
972 DestReg, psrc1, op2);
978 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
979 uint8_t dataBits = dataSize * 8;
980 uint8_t realShiftAmt = shiftAmt %% (2 * dataBits);
982 if (realShiftAmt == 0) {
984 } else if (realShiftAmt < dataBits) {
985 // Because what happens to the bits shift -in- on a right
986 // shift is not defined in the C/C++ standard, we have to
987 // mask them out to be sure they're zero.
988 uint64_t logicalMask = mask(dataBits - realShiftAmt);
989 result = ((psrc1 >> realShiftAmt) & logicalMask) |
990 (DoubleBits << (dataBits - realShiftAmt));
992 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt);
993 result = ((DoubleBits >> (realShiftAmt - dataBits)) &
995 (psrc1 << (2 * dataBits - realShiftAmt));
999 code = srdCode % "DestReg = merge(DestReg, result, dataSize);"
1000 big_code = srdCode % "DestReg = result & mask(dataSize * 8);"
1002 // If the shift amount is zero, no flags should be modified.
1004 //Zero out any flags we might modify. This way we only have to
1005 //worry about setting them.
1006 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
1008 //If some combination of the CF bits need to be set, set them.
1009 if ((realShiftAmt == 0 &&
1010 bits(DoubleBits, dataBits - 1)) ||
1011 (realShiftAmt <= dataBits &&
1012 bits(SrcReg1, realShiftAmt - 1)) ||
1013 (realShiftAmt > dataBits &&
1014 bits(DoubleBits, realShiftAmt - dataBits - 1))) {
1017 //If some combination of the CF bits need to be set, set them.
1018 if ((ext & (CFBit | ECFBit)) && CFBits)
1019 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
1020 //Figure out what the OF bit should be.
1021 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^
1022 bits(result, dataBits - 1)))
1023 ccFlagBits = ccFlagBits | OFBit;
1024 //Use the regular mechanisms to calculate the other flags.
1025 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
1026 DestReg, psrc1, op2);
1031 code = 'DoubleBits = psrc1 ^ op2;'
1033 class Wrip(WrRegOp, CondRegOp):
1034 code = 'NRIP = psrc1 + sop2 + CSBase;'
1035 else_code = "NRIP = NRIP;"
1037 class Wruflags(WrRegOp):
1038 code = 'ccFlagBits = psrc1 ^ op2'
1040 class Wrflags(WrRegOp):
1042 MiscReg newFlags = psrc1 ^ op2;
1043 MiscReg userFlagMask = 0xDD5;
1044 // Get only the user flags
1045 ccFlagBits = newFlags & userFlagMask;
1046 // Get everything else
1047 nccFlagBits = newFlags & ~userFlagMask;
1050 class Rdip(RdRegOp):
1051 code = 'DestReg = NRIP - CSBase;'
1053 class Ruflags(RdRegOp):
1054 code = 'DestReg = ccFlagBits'
1056 class Rflags(RdRegOp):
1057 code = 'DestReg = ccFlagBits | nccFlagBits'
1059 class Ruflag(RegOp):
1061 int flag = bits(ccFlagBits, imm8);
1062 DestReg = merge(DestReg, flag, dataSize);
1063 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1064 (ccFlagBits & ~EZFBit);
1067 int flag = bits(ccFlagBits, imm8);
1068 DestReg = flag & mask(dataSize * 8);
1069 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1070 (ccFlagBits & ~EZFBit);
1072 def __init__(self, dest, imm, flags=None, \
1073 dataSize="env.dataSize"):
1074 super(Ruflag, self).__init__(dest, \
1075 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1079 MiscReg flagMask = 0x3F7FDD5;
1080 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
1081 int flag = bits(flags, imm8);
1082 DestReg = merge(DestReg, flag, dataSize);
1083 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1084 (ccFlagBits & ~EZFBit);
1087 MiscReg flagMask = 0x3F7FDD5;
1088 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
1089 int flag = bits(flags, imm8);
1090 DestReg = flag & mask(dataSize * 8);
1091 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
1092 (ccFlagBits & ~EZFBit);
1094 def __init__(self, dest, imm, flags=None, \
1095 dataSize="env.dataSize"):
1096 super(Rflag, self).__init__(dest, \
1097 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
1102 // Mask the bit position so that it wraps.
1103 int bitPos = op2 & (dataSize * 8 - 1);
1104 int sign_bit = bits(val, bitPos, bitPos);
1105 uint64_t maskVal = mask(bitPos+1);
1106 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1107 DestReg = merge(DestReg, val, dataSize);
1111 // Mask the bit position so that it wraps.
1112 int bitPos = op2 & (dataSize * 8 - 1);
1113 int sign_bit = bits(val, bitPos, bitPos);
1114 uint64_t maskVal = mask(bitPos+1);
1115 val = sign_bit ? (val | ~maskVal) : (val & maskVal);
1116 DestReg = val & mask(dataSize * 8);
1120 ccFlagBits = ccFlagBits &
1121 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
1123 ccFlagBits = ccFlagBits |
1124 (ext & (CFBit | ECFBit | ZFBit | EZFBit));
1128 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
1129 big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);'
1132 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1133 super(Rddr, self).__init__(dest, \
1134 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1138 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
1139 fault = new InvalidOpcode();
1140 } else if (dr7.gd) {
1141 fault = new DebugException();
1146 code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);"
1147 big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);"
1150 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1151 super(Wrdr, self).__init__(dest, \
1152 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1156 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
1157 fault = new InvalidOpcode();
1158 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) &&
1159 machInst.mode.mode == LongMode) {
1160 fault = new GeneralProtection(0);
1161 } else if (dr7.gd) {
1162 fault = new DebugException();
1169 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1170 super(Rdcr, self).__init__(dest, \
1171 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1173 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
1174 fault = new InvalidOpcode();
1179 code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);"
1180 big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);"
1183 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1184 super(Wrcr, self).__init__(dest, \
1185 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1187 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
1188 fault = new InvalidOpcode();
1190 // There are *s in the line below so it doesn't confuse the
1191 // parser. They may be unnecessary.
1192 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
1193 MiscReg newVal = psrc1;
1195 // Check for any modifications that would cause a fault.
1202 if (bits(newVal, 63, 32) ||
1203 (!cr0.pe && cr0.pg) ||
1204 (!cr0.cd && cr0.nw) ||
1205 (cr0.pg && efer.lme && !oldCr4.pae))
1206 fault = new GeneralProtection(0);
1216 // PAE can't be disabled in long mode.
1217 if (bits(newVal, 63, 11) ||
1218 (machInst.mode.mode == LongMode && !cr4.pae))
1219 fault = new GeneralProtection(0);
1224 if (bits(newVal, 63, 4))
1225 fault = new GeneralProtection(0);
1228 panic("Unrecognized control register %d.\\n", dest);
1230 ControlDest = newVal;
1234 # Microops for manipulating segmentation registers
1235 class SegOp(CondRegOp):
1237 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1238 super(SegOp, self).__init__(dest, \
1239 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1241 class Wrbase(SegOp):
1243 SegBaseDest = psrc1;
1246 class Wrlimit(SegOp):
1248 SegLimitDest = psrc1;
1256 class WrAttr(SegOp):
1258 SegAttrDest = psrc1;
1261 class Rdbase(SegOp):
1262 code = 'DestReg = merge(DestReg, SegBaseSrc1, dataSize);'
1263 big_code = 'DestReg = SegBaseSrc1 & mask(dataSize * 8);'
1265 class Rdlimit(SegOp):
1266 code = 'DestReg = merge(DestReg, SegLimitSrc1, dataSize);'
1267 big_code = 'DestReg = SegLimitSrc1 & mask(dataSize * 8);'
1269 class RdAttr(SegOp):
1270 code = 'DestReg = merge(DestReg, SegAttrSrc1, dataSize);'
1271 big_code = 'DestReg = SegAttrSrc1 & mask(dataSize * 8);'
1274 code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);'
1275 big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);'
1278 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1279 super(Rdval, self).__init__(dest, src1, \
1280 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1282 DestReg = MiscRegSrc1;
1286 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
1287 super(Wrval, self).__init__(dest, src1, \
1288 "InstRegIndex(NUM_INTREGS)", flags, dataSize)
1290 MiscRegDest = SrcReg1;
1294 def __init__(self, dest, src1, src2=0,
1295 flags=None, dataSize="env.dataSize"):
1296 super(Chks, self).__init__(dest,
1297 src1, src2, flags, dataSize)
1299 // The selector is in source 1 and can be at most 16 bits.
1300 SegSelector selector = DestReg;
1301 SegDescriptor desc = SrcReg1;
1302 HandyM5Reg m5reg = M5Reg;
1309 // Make sure it's the right type
1310 if (desc.s == 0 || desc.type.codeOrData != 1) {
1311 fault = new GeneralProtection(0);
1312 } else if (m5reg.cpl != desc.dpl) {
1313 fault = new GeneralProtection(0);
1316 case SegCallGateCheck:
1317 panic("CS checks for far calls/jumps through call gates"
1318 "not implemented.\\n");
1320 case SegSoftIntGateCheck:
1321 // Check permissions.
1322 if (desc.dpl < m5reg.cpl) {
1323 fault = new GeneralProtection(selector);
1326 // Fall through on purpose
1327 case SegIntGateCheck:
1328 // Make sure the gate's the right type.
1329 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
1330 ((desc.type & 0x6) != 0x6)) {
1331 fault = new GeneralProtection(0);
1335 if (selector.si || selector.ti) {
1337 fault = new StackFault(selector);
1340 if ((m5reg.submode != SixtyFourBitMode ||
1343 desc.type.codeOrData == 0 && desc.type.w) ||
1344 (desc.dpl != m5reg.cpl) ||
1345 (selector.rpl != m5reg.cpl)) {
1346 fault = new GeneralProtection(selector);
1352 if ((!selector.si && !selector.ti) ||
1353 (selector.rpl < m5reg.cpl) ||
1354 !(desc.s == 1 && desc.type.codeOrData == 1) ||
1355 (!desc.type.c && desc.dpl != selector.rpl) ||
1356 (desc.type.c && desc.dpl > selector.rpl)) {
1357 fault = new GeneralProtection(selector);
1358 } else if (!desc.p) {
1359 fault = new SegmentNotPresent(selector);
1364 if (m5reg.mode == LongMode) {
1365 if (desc.l != 1 || desc.d != 0) {
1366 fault = new GeneralProtection(selector);
1369 panic("Interrupt CS checks not implemented "
1370 "in legacy mode.\\n");
1374 if (!selector.si || selector.ti) {
1375 fault = new GeneralProtection(selector);
1380 fault = new SegmentNotPresent(selector);
1381 } else if (!(desc.type == 0x9 ||
1383 m5reg.mode != LongMode))) {
1384 fault = new GeneralProtection(selector);
1389 fault = new GeneralProtection(selector);
1394 fault = new SegmentNotPresent(selector);
1395 } else if (desc.type != 0x2) {
1396 fault = new GeneralProtection(selector);
1400 panic("Undefined segment check type.\\n");
1404 // Check for a NULL selector and set ZF,EZF appropriately.
1405 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
1406 if (!selector.si && !selector.ti)
1407 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
1412 SegDescriptor desc = SrcReg1;
1414 uint64_t target = bits(SrcReg2, 31, 0) << 32;
1417 case AvailableTSS64:
1419 replaceBits(target, 23, 0, desc.baseLow);
1420 replaceBits(target, 31, 24, desc.baseHigh);
1425 replaceBits(target, 15, 0, bits(desc, 15, 0));
1426 replaceBits(target, 31, 16, bits(desc, 63, 48));
1429 panic("Wrdh used with wrong descriptor type!\\n");
1434 class Wrtsc(WrRegOp):
1439 class Rdtsc(RdRegOp):
1444 class Rdm5reg(RdRegOp):
1451 SegDescriptor desc = SrcReg1;
1452 SegSelector selector = SrcReg2;
1453 if (selector.si || selector.ti) {
1455 panic("Segment not present.\\n");
1457 attr.dpl = desc.dpl;
1459 attr.defaultSize = desc.d;
1460 attr.longMode = desc.l;
1461 attr.avl = desc.avl;
1462 attr.granularity = desc.g;
1463 attr.present = desc.p;
1464 attr.system = desc.s;
1465 attr.type = desc.type;
1467 // The expand down bit happens to be set for gates.
1469 panic("Gate descriptor encountered.\\n");
1473 attr.expandDown = 0;
1475 if (desc.type.codeOrData) {
1476 attr.expandDown = 0;
1477 attr.readable = desc.type.r;
1480 attr.expandDown = desc.type.e;
1482 attr.writable = desc.type.w;
1485 Addr base = desc.baseLow | (desc.baseHigh << 24);
1486 Addr limit = desc.limitLow | (desc.limitHigh << 16);
1488 limit = (limit << 12) | mask(12);
1490 SegLimitDest = limit;
1493 SegBaseDest = SegBaseDest;
1494 SegLimitDest = SegLimitDest;
1495 SegAttrDest = SegAttrDest;