src/arch/x86/isa/operands.isa

   1 // Copyright (c) 2007 The Regents of The University of Michigan
   2 // All rights reserved.
   3 //
   4 // Redistribution and use in source and binary forms, with or without
   5 // modification, are permitted provided that the following conditions are
   6 // met: redistributions of source code must retain the above copyright
   7 // notice, this list of conditions and the following disclaimer;
   8 // redistributions in binary form must reproduce the above copyright
   9 // notice, this list of conditions and the following disclaimer in the
  10 // documentation and/or other materials provided with the distribution;
  11 // neither the name of the copyright holders nor the names of its
  12 // contributors may be used to endorse or promote products derived from
  13 // this software without specific prior written permission.
  14 //
  15 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 //
  27 // Authors: Gabe Black
  28
  29 // Copyright (c) 2007-2008 The Hewlett-Packard Development Company
  30 // All rights reserved.
  31 //
  32 // Redistribution and use of this software in source and binary forms,
  33 // with or without modification, are permitted provided that the
  34 // following conditions are met:
  35 //
  36 // The software must be used only for Non-Commercial Use which means any
  37 // use which is NOT directed to receiving any direct monetary
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  39 // examples of non-commercial use are academic research, personal study,
  40 // teaching, education and corporate research & development.
  41 // Illustrative examples of commercial use are distributing products for
  42 // commercial advantage and providing services using the software for
  43 // commercial advantage.
  44 //
  45 // If you wish to use this software or functionality therein that may be
  46 // covered by patents for commercial use, please contact:
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  49 //     Hewlett-Packard Company
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  52 //
  53 // Redistributions of source code must retain the above copyright notice,
  54 // this list of conditions and the following disclaimer.  Redistributions
  55 // in binary form must reproduce the above copyright notice, this list of
  56 // conditions and the following disclaimer in the documentation and/or
  57 // other materials provided with the distribution.  Neither the name of
  58 // the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  59 // contributors may be used to endorse or promote products derived from
  60 // this software without specific prior written permission.  No right of
  61 // sublicense is granted herewith.  Derivatives of the software and
  62 // output created using the software may be prepared, but only for
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  67 // notice to acknowledge the contribution from this software where
  68 // applicable, this list of conditions and the disclaimer below.
  69 //
  70 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  71 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  72 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  73 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  74 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  75 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  76 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  77 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  78 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  79 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  80 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  81 //
  82 // Authors: Gabe Black
  83
  84 def operand_types {{
  85     'sb' : ('signed int', 8),
  86     'ub' : ('unsigned int', 8),
  87     'sw' : ('signed int', 16),
  88     'uw' : ('unsigned int', 16),
  89     'sdw' : ('signed int', 32),
  90     'udw' : ('unsigned int', 32),
  91     'sqw' : ('signed int', 64),
  92     'uqw' : ('unsigned int', 64),
  93     'sf' : ('float', 32),
  94     'df' : ('float', 64),
  95 }};
  96
  97 def operands {{
  98         'SrcReg1':       ('IntReg', 'uqw', 'INTREG_FOLDED(src1, foldOBit)', 'IsInteger', 1),
  99         'SSrcReg1':      ('IntReg', 'uqw', 'src1', 'IsInteger', 1),
 100         'SrcReg2':       ('IntReg', 'uqw', 'INTREG_FOLDED(src2, foldOBit)', 'IsInteger', 2),
 101         'SSrcReg2':      ('IntReg', 'uqw', 'src2', 'IsInteger', 1),
 102         'Index':         ('IntReg', 'uqw', 'INTREG_FOLDED(index, foldABit)', 'IsInteger', 3),
 103         'Base':          ('IntReg', 'uqw', 'INTREG_FOLDED(base, foldABit)', 'IsInteger', 4),
 104         'DestReg':       ('IntReg', 'uqw', 'INTREG_FOLDED(dest, foldOBit)', 'IsInteger', 5),
 105         'SDestReg':      ('IntReg', 'uqw', 'dest', 'IsInteger', 5),
 106         'Data':          ('IntReg', 'uqw', 'INTREG_FOLDED(data, foldOBit)', 'IsInteger', 6),
 107         'ProdLow':       ('IntReg', 'uqw', 'INTREG_IMPLICIT(0)', 'IsInteger', 7),
 108         'ProdHi':        ('IntReg', 'uqw', 'INTREG_IMPLICIT(1)', 'IsInteger', 8),
 109         'Quotient':      ('IntReg', 'uqw', 'INTREG_IMPLICIT(2)', 'IsInteger', 9),
 110         'Remainder':     ('IntReg', 'uqw', 'INTREG_IMPLICIT(3)', 'IsInteger', 10),
 111         'Divisor':       ('IntReg', 'uqw', 'INTREG_IMPLICIT(4)', 'IsInteger', 11),
 112         'Rax':           ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 12),
 113         'Rbx':           ('IntReg', 'uqw', '(INTREG_RBX)', 'IsInteger', 13),
 114         'Rcx':           ('IntReg', 'uqw', '(INTREG_RCX)', 'IsInteger', 14),
 115         'Rdx':           ('IntReg', 'uqw', '(INTREG_RDX)', 'IsInteger', 15),
 116         'Rsp':           ('IntReg', 'uqw', '(INTREG_RSP)', 'IsInteger', 16),
 117         'Rbp':           ('IntReg', 'uqw', '(INTREG_RBP)', 'IsInteger', 17),
 118         'Rsi':           ('IntReg', 'uqw', '(INTREG_RSI)', 'IsInteger', 18),
 119         'Rdi':           ('IntReg', 'uqw', '(INTREG_RDI)', 'IsInteger', 19),
 120         'FpSrcReg1':     ('FloatReg', 'df', 'src1', 'IsFloating', 20),
 121         'FpSrcReg2':     ('FloatReg', 'df', 'src2', 'IsFloating', 21),
 122         'FpDestReg':     ('FloatReg', 'df', 'dest', 'IsFloating', 22),
 123         'FpData':        ('FloatReg', 'df', 'data', 'IsFloating', 23),
 124         'RIP':           ('NPC', 'uqw', None, (None, None, 'IsControl'), 50),
 125         'uIP':           ('UPC', 'uqw', None, (None, None, 'IsControl'), 51),
 126         'nuIP':          ('NUPC', 'uqw', None, (None, None, 'IsControl'), 52),
 127         # This holds the condition code portion of the flag register. The
 128         # nccFlagBits version holds the rest.
 129         'ccFlagBits':    ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', None, 60),
 130         # These register should needs to be more protected so that later
 131         # instructions don't map their indexes with an old value.
 132         'nccFlagBits':   ('ControlReg', 'uqw', 'MISCREG_RFLAGS', None, 61),
 133         'TOP':           ('ControlReg', 'ub', 'MISCREG_X87_TOP', None, 62),
 134         # The segment base as used by memory instructions.
 135         'SegBase':       ('ControlReg', 'uqw', 'MISCREG_SEG_EFF_BASE(segment)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 70),
 136
 137         # Operands to get and set registers indexed by the operands of the
 138         # original instruction.
 139         'ControlDest':   ('ControlReg', 'uqw', 'MISCREG_CR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 100),
 140         'ControlSrc1':   ('ControlReg', 'uqw', 'MISCREG_CR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 101),
 141         'DebugDest':   ('ControlReg', 'uqw', 'MISCREG_DR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 102),
 142         'DebugSrc1':   ('ControlReg', 'uqw', 'MISCREG_DR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 103),
 143         'SegBaseDest':  ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 104),
 144         'SegBaseSrc1':  ('ControlReg', 'uqw', 'MISCREG_SEG_BASE(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 105),
 145         'SegLimitDest': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 106),
 146         'SegLimitSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_LIMIT(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 107),
 147         'SegSelDest': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 108),
 148         'SegSelSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_SEL(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 109),
 149         'SegAttrDest': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(dest)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 110),
 150         'SegAttrSrc1': ('ControlReg', 'uqw', 'MISCREG_SEG_ATTR(src1)', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 111),
 151
 152         # Operands to access specific control registers directly.
 153         'EferOp':        ('ControlReg', 'uqw', 'MISCREG_EFER', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 200),
 154         'CR4Op':         ('ControlReg', 'uqw', 'MISCREG_CR4', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 201),
 155         'DR7Op':         ('ControlReg', 'uqw', 'MISCREG_DR7', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 202),
 156         'LDTRBase':      ('ControlReg', 'uqw', 'MISCREG_TSL_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 203),
 157         'LDTRLimit':     ('ControlReg', 'uqw', 'MISCREG_TSL_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 204),
 158         'LDTRSel':       ('ControlReg', 'uqw', 'MISCREG_TSL', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 205),
 159         'GDTRBase':      ('ControlReg', 'uqw', 'MISCREG_TSG_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 206),
 160         'GDTRLimit':     ('ControlReg', 'uqw', 'MISCREG_TSG_LIMIT', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 207),
 161         'CSBase':        ('ControlReg', 'udw', 'MISCREG_CS_EFF_BASE', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 208),
 162         'CSAttr':        ('ControlReg', 'udw', 'MISCREG_CS_ATTR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 209),
 163         'MiscRegDest':   ('ControlReg', 'uqw', 'dest', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 210),
 164         'MiscRegSrc1':   ('ControlReg', 'uqw', 'src1', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 211),
 165         'TscOp':         ('ControlReg', 'uqw', 'MISCREG_TSC', (None, None, ['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']), 212),
 166         'M5Reg':         ('ControlReg', 'uqw', 'MISCREG_M5_REG', (None, None, None), 213),
 167         'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 300)
 168 }};