Merge ktlim@zizzer:/bk/newmem
[gem5.git] / src / arch / x86 / isa / specialize.isa
1 // -*- mode:c++ -*-
2
3 // Copyright (c) 2007 The Hewlett-Packard Development Company
4 // All rights reserved.
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40 // and (ii) such Derivatives of the software include the above copyright
41 // notice to acknowledge the contribution from this software where
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43 //
44 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
45 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
46 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
47 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
48 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
49 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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55 //
56 // Authors: Gabe Black
57
58 ////////////////////////////////////////////////////////////////////
59 //
60 // Code to "specialize" a microcode sequence to use a particular
61 // variety of operands
62 //
63
64 let {{
65 # This code builds up a decode block which decodes based on switchval.
66 # vals is a dict which matches case values with what should be decoded to.
67 # builder is called on the exploded contents of "vals" values to generate
68 # whatever code should be used.
69 def doSplitDecode(name, Name, builder, switchVal, vals, default = None):
70 header_output = ''
71 decoder_output = ''
72 decode_block = 'switch(%s) {\n' % switchVal
73 exec_output = ''
74 for (val, todo) in vals.items():
75 (new_header_output,
76 new_decoder_output,
77 new_decode_block,
78 new_exec_output) = builder(name, Name, *todo)
79 header_output += new_header_output
80 decoder_output += new_decoder_output
81 decode_block += '\tcase %s: %s\n' % (val, new_decode_block)
82 exec_output += new_exec_output
83 if default:
84 (new_header_output,
85 new_decoder_output,
86 new_decode_block,
87 new_exec_output) = builder(name, Name, *default)
88 header_output += new_header_output
89 decoder_output += new_decoder_output
90 decode_block += '\tdefault: %s\n' % new_decode_block
91 exec_output += new_exec_output
92 decode_block += '}\n'
93 return (header_output, decoder_output, decode_block, exec_output)
94 }};
95
96 let {{
97 class OpType(object):
98 parser = re.compile(r"(?P<tag>[A-Z][A-Z]*)(?P<size>[a-z][a-z]*)|(r(?P<reg>[A-Za-z0-9][A-Za-z0-9]*))")
99 def __init__(self, opTypeString):
100 match = OpType.parser.search(opTypeString)
101 if match == None:
102 raise Exception, "Problem parsing operand type %s" % opTypeString
103 self.reg = match.group("reg")
104 self.tag = match.group("tag")
105 self.size = match.group("size")
106
107 # This function specializes the given piece of code to use a particular
108 # set of argument types described by "opTypes". These are "implemented"
109 # in reverse order.
110 def specializeInst(name, Name, code, opTypes):
111 opNum = len(opTypes) - 1
112 while len(opTypes):
113 # print "Building a composite op with tags", opTypes
114 # print "And code", code
115 opNum = len(opTypes) - 1
116 # A regular expression to find the operand placeholders we're
117 # interested in.
118 opRe = re.compile("\\^(?P<operandNum>%d)(?=[^0-9]|$)" % opNum)
119
120 # Parse the operand type strign we're working with
121 opType = OpType(opTypes[opNum])
122
123 if opType.reg:
124 #Figure out what to do with fixed register operands
125 if opType.reg in ("Ax", "Bx", "Cx", "Dx"):
126 code = opRe.sub("%%{INTREG_R%s}" % opType.reg.upper(), code)
127 elif opType.reg == "Al":
128 # We need a way to specify register width
129 code = opRe.sub("%{INTREG_RAX}", code)
130 else:
131 print "Didn't know how to encode fixed register %s!" % opType.reg
132 elif opType.tag == None or opType.size == None:
133 raise Exception, "Problem parsing operand tag: %s" % opType.tag
134 elif opType.tag in ("C", "D", "G", "P", "S", "T", "V"):
135 # Use the "reg" field of the ModRM byte to select the register
136 code = opRe.sub("%{(uint8_t)MODRM_REG}", code)
137 elif opType.tag in ("E", "Q", "W"):
138 # This might refer to memory or to a register. We need to
139 # divide it up farther.
140 regCode = opRe.sub("%{(uint8_t)MODRM_RM}", code)
141 regTypes = copy.copy(opTypes)
142 regTypes.pop(-1)
143 # This needs to refer to memory, but we'll fill in the details
144 # later. It needs to take into account unaligned memory
145 # addresses.
146 memCode = opRe.sub("%0", code)
147 memTypes = copy.copy(opTypes)
148 memTypes.pop(-1)
149 return doSplitDecode(name, Name, specializeInst, "MODRM_MOD",
150 {"3" : (regCode, regTypes)}, (memCode, memTypes))
151 elif opType.tag in ("I", "J"):
152 # Immediates are already in the instruction, so don't leave in
153 # those parameters
154 code = opRe.sub("${IMMEDIATE}", code)
155 elif opType.tag == "M":
156 # This needs to refer to memory, but we'll fill in the details
157 # later. It needs to take into account unaligned memory
158 # addresses.
159 code = opRe.sub("%0", code)
160 elif opType.tag in ("PR", "R", "VR"):
161 # There should probably be a check here to verify that mod
162 # is equal to 11b
163 code = opRe.sub("%{(uint8_t)MODRM_RM}", code)
164 else:
165 raise Exception, "Unrecognized tag %s." % opType.tag
166 opTypes.pop(-1)
167
168 # At this point, we've built up "code" to have all the necessary extra
169 # instructions needed to implement whatever types of operands were
170 # specified. Now we'll assemble it it into a StaticInst.
171 return assembleMicro(name, Name, code)
172 }};