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31 #include "arch/x86/isa.hh"
32 #include "arch/x86/tlb.hh"
33 #include "cpu/base.hh"
34 #include "cpu/thread_context.hh"
35 #include "sim/serialize.hh"
41 ISA::updateHandyM5Reg(Efer efer
, CR0 cr0
,
42 SegAttr csAttr
, SegAttr ssAttr
, RFLAGS rflags
)
46 m5reg
.mode
= LongMode
;
48 m5reg
.submode
= SixtyFourBitMode
;
50 m5reg
.submode
= CompatabilityMode
;
52 m5reg
.mode
= LegacyMode
;
55 m5reg
.submode
= Virtual8086Mode
;
57 m5reg
.submode
= ProtectedMode
;
59 m5reg
.submode
= RealMode
;
62 m5reg
.cpl
= csAttr
.dpl
;
63 m5reg
.paging
= cr0
.pg
;
66 // Compute the default and alternate operand size.
67 if (m5reg
.submode
== SixtyFourBitMode
|| csAttr
.defaultSize
) {
75 // Compute the default and alternate address size.
76 if (m5reg
.submode
== SixtyFourBitMode
) {
79 } else if (csAttr
.defaultSize
) {
87 // Compute the stack size
88 if (m5reg
.submode
== SixtyFourBitMode
) {
90 } else if (ssAttr
.defaultSize
) {
96 regVal
[MISCREG_M5_REG
] = m5reg
;
102 // Blank everything. 0 might not be an appropriate value for some things,
103 // but it is for most.
104 memset(regVal
, 0, NumMiscRegs
* sizeof(MiscReg
));
105 regVal
[MISCREG_DR6
] = (mask(8) << 4) | (mask(16) << 16);
106 regVal
[MISCREG_DR7
] = 1 << 10;
110 ISA::readMiscRegNoEffect(int miscReg
)
112 // Make sure we're not dealing with an illegal control register.
113 // Instructions should filter out these indexes, and nothing else should
114 // attempt to read them directly.
115 assert( miscReg
!= MISCREG_CR1
&&
116 !(miscReg
> MISCREG_CR4
&&
117 miscReg
< MISCREG_CR8
) &&
118 !(miscReg
> MISCREG_CR8
&&
119 miscReg
<= MISCREG_CR15
));
121 return regVal
[miscReg
];
125 ISA::readMiscReg(int miscReg
, ThreadContext
* tc
)
127 if (miscReg
== MISCREG_TSC
) {
128 return regVal
[MISCREG_TSC
] + tc
->getCpuPtr()->curCycle();
130 return readMiscRegNoEffect(miscReg
);
134 ISA::setMiscRegNoEffect(int miscReg
, MiscReg val
)
136 // Make sure we're not dealing with an illegal control register.
137 // Instructions should filter out these indexes, and nothing else should
138 // attempt to write to them directly.
139 assert( miscReg
!= MISCREG_CR1
&&
140 !(miscReg
> MISCREG_CR4
&&
141 miscReg
< MISCREG_CR8
) &&
142 !(miscReg
> MISCREG_CR8
&&
143 miscReg
<= MISCREG_CR15
));
144 regVal
[miscReg
] = val
;
148 ISA::setMiscReg(int miscReg
, MiscReg val
, ThreadContext
* tc
)
150 MiscReg newVal
= val
;
155 CR0 toggled
= regVal
[miscReg
] ^ val
;
157 Efer efer
= regVal
[MISCREG_EFER
];
158 if (toggled
.pg
&& efer
.lme
) {
160 //Turning on long mode
162 regVal
[MISCREG_EFER
] = efer
;
164 //Turning off long mode
166 regVal
[MISCREG_EFER
] = efer
;
170 tc
->getITBPtr()->invalidateAll();
171 tc
->getDTBPtr()->invalidateAll();
173 //This must always be 1.
176 updateHandyM5Reg(regVal
[MISCREG_EFER
],
178 regVal
[MISCREG_CS_ATTR
],
179 regVal
[MISCREG_SS_ATTR
],
180 regVal
[MISCREG_RFLAGS
]);
186 tc
->getITBPtr()->invalidateNonGlobal();
187 tc
->getDTBPtr()->invalidateNonGlobal();
191 CR4 toggled
= regVal
[miscReg
] ^ val
;
192 if (toggled
.pae
|| toggled
.pse
|| toggled
.pge
) {
193 tc
->getITBPtr()->invalidateAll();
194 tc
->getDTBPtr()->invalidateAll();
200 case MISCREG_CS_ATTR
:
202 SegAttr toggled
= regVal
[miscReg
] ^ val
;
203 SegAttr newCSAttr
= val
;
204 if (toggled
.longMode
) {
205 if (newCSAttr
.longMode
) {
206 regVal
[MISCREG_ES_EFF_BASE
] = 0;
207 regVal
[MISCREG_CS_EFF_BASE
] = 0;
208 regVal
[MISCREG_SS_EFF_BASE
] = 0;
209 regVal
[MISCREG_DS_EFF_BASE
] = 0;
211 regVal
[MISCREG_ES_EFF_BASE
] = regVal
[MISCREG_ES_BASE
];
212 regVal
[MISCREG_CS_EFF_BASE
] = regVal
[MISCREG_CS_BASE
];
213 regVal
[MISCREG_SS_EFF_BASE
] = regVal
[MISCREG_SS_BASE
];
214 regVal
[MISCREG_DS_EFF_BASE
] = regVal
[MISCREG_DS_BASE
];
217 updateHandyM5Reg(regVal
[MISCREG_EFER
],
220 regVal
[MISCREG_SS_ATTR
],
221 regVal
[MISCREG_RFLAGS
]);
224 case MISCREG_SS_ATTR
:
225 updateHandyM5Reg(regVal
[MISCREG_EFER
],
227 regVal
[MISCREG_CS_ATTR
],
229 regVal
[MISCREG_RFLAGS
]);
231 // These segments always actually use their bases, or in other words
232 // their effective bases must stay equal to their actual bases.
233 case MISCREG_FS_BASE
:
234 case MISCREG_GS_BASE
:
235 case MISCREG_HS_BASE
:
236 case MISCREG_TSL_BASE
:
237 case MISCREG_TSG_BASE
:
238 case MISCREG_TR_BASE
:
239 case MISCREG_IDTR_BASE
:
240 regVal
[MISCREG_SEG_EFF_BASE(miscReg
- MISCREG_SEG_BASE_BASE
)] = val
;
242 // These segments ignore their bases in 64 bit mode.
243 // their effective bases must stay equal to their actual bases.
244 case MISCREG_ES_BASE
:
245 case MISCREG_CS_BASE
:
246 case MISCREG_SS_BASE
:
247 case MISCREG_DS_BASE
:
249 Efer efer
= regVal
[MISCREG_EFER
];
250 SegAttr csAttr
= regVal
[MISCREG_CS_ATTR
];
251 if (!efer
.lma
|| !csAttr
.longMode
) // Check for non 64 bit mode.
252 regVal
[MISCREG_SEG_EFF_BASE(miscReg
-
253 MISCREG_SEG_BASE_BASE
)] = val
;
257 regVal
[MISCREG_TSC
] = val
- tc
->getCpuPtr()->curCycle();
263 /* These should eventually set up breakpoints. */
266 miscReg
= MISCREG_DR6
;
267 /* Fall through to have the same effects as DR6. */
270 DR6 dr6
= regVal
[MISCREG_DR6
];
283 miscReg
= MISCREG_DR7
;
284 /* Fall through to have the same effects as DR7. */
287 DR7 dr7
= regVal
[MISCREG_DR7
];
291 if (dr7
.l0
|| dr7
.g0
) {
292 panic("Debug register breakpoints not implemented.\n");
294 /* Disable breakpoint 0. */
298 if (dr7
.l1
|| dr7
.g1
) {
299 panic("Debug register breakpoints not implemented.\n");
301 /* Disable breakpoint 1. */
305 if (dr7
.l2
|| dr7
.g2
) {
306 panic("Debug register breakpoints not implemented.\n");
308 /* Disable breakpoint 2. */
312 if (dr7
.l3
|| dr7
.g3
) {
313 panic("Debug register breakpoints not implemented.\n");
315 /* Disable breakpoint 3. */
318 dr7
.rw0
= newDR7
.rw0
;
319 dr7
.len0
= newDR7
.len0
;
320 dr7
.rw1
= newDR7
.rw1
;
321 dr7
.len1
= newDR7
.len1
;
322 dr7
.rw2
= newDR7
.rw2
;
323 dr7
.len2
= newDR7
.len2
;
324 dr7
.rw3
= newDR7
.rw3
;
325 dr7
.len3
= newDR7
.len3
;
329 // Writing anything to the m5reg with side effects makes it update
330 // based on the current values of the relevant registers. The actual
331 // value written is discarded.
332 updateHandyM5Reg(regVal
[MISCREG_EFER
],
334 regVal
[MISCREG_CS_ATTR
],
335 regVal
[MISCREG_SS_ATTR
],
336 regVal
[MISCREG_RFLAGS
]);
341 setMiscRegNoEffect(miscReg
, newVal
);
345 ISA::serialize(EventManager
*em
, std::ostream
& os
)
347 SERIALIZE_ARRAY(regVal
, NumMiscRegs
);
351 ISA::unserialize(EventManager
*em
, Checkpoint
* cp
,
352 const std::string
& section
)
354 UNSERIALIZE_ARRAY(regVal
, NumMiscRegs
);
355 updateHandyM5Reg(regVal
[MISCREG_EFER
],
357 regVal
[MISCREG_CS_ATTR
],
358 regVal
[MISCREG_SS_ATTR
],
359 regVal
[MISCREG_RFLAGS
]);