2 * Copyright (c) 2009 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "arch/x86/isa.hh"
33 #include "arch/x86/decoder.hh"
34 #include "arch/x86/tlb.hh"
35 #include "cpu/base.hh"
36 #include "cpu/thread_context.hh"
37 #include "params/X86ISA.hh"
38 #include "sim/serialize.hh"
44 ISA::updateHandyM5Reg(Efer efer
, CR0 cr0
,
45 SegAttr csAttr
, SegAttr ssAttr
, RFLAGS rflags
,
50 m5reg
.mode
= LongMode
;
52 m5reg
.submode
= SixtyFourBitMode
;
54 m5reg
.submode
= CompatabilityMode
;
56 m5reg
.mode
= LegacyMode
;
59 m5reg
.submode
= Virtual8086Mode
;
61 m5reg
.submode
= ProtectedMode
;
63 m5reg
.submode
= RealMode
;
66 m5reg
.cpl
= csAttr
.dpl
;
67 m5reg
.paging
= cr0
.pg
;
70 // Compute the default and alternate operand size.
71 if (m5reg
.submode
== SixtyFourBitMode
|| csAttr
.defaultSize
) {
79 // Compute the default and alternate address size.
80 if (m5reg
.submode
== SixtyFourBitMode
) {
83 } else if (csAttr
.defaultSize
) {
91 // Compute the stack size
92 if (m5reg
.submode
== SixtyFourBitMode
) {
94 } else if (ssAttr
.defaultSize
) {
100 regVal
[MISCREG_M5_REG
] = m5reg
;
102 tc
->getDecoderPtr()->setM5Reg(m5reg
);
108 // Blank everything. 0 might not be an appropriate value for some things,
109 // but it is for most.
110 memset(regVal
, 0, NumMiscRegs
* sizeof(RegVal
));
112 // If some state should be non-zero after a reset, set those values here.
113 regVal
[MISCREG_CR0
] = 0x0000000060000010ULL
;
115 regVal
[MISCREG_MTRRCAP
] = 0x0508;
117 regVal
[MISCREG_MCG_CAP
] = 0x104;
119 regVal
[MISCREG_PAT
] = 0x0007040600070406ULL
;
121 regVal
[MISCREG_SYSCFG
] = 0x20601;
123 regVal
[MISCREG_TOP_MEM
] = 0x4000000;
125 regVal
[MISCREG_DR6
] = (mask(8) << 4) | (mask(16) << 16);
126 regVal
[MISCREG_DR7
] = 1 << 10;
128 LocalApicBase lApicBase
= 0;
129 lApicBase
.base
= 0xFEE00000 >> 12;
130 lApicBase
.enable
= 1;
131 // The "bsp" bit will be set when this register is read, since then we'll
132 // have a ThreadContext to check the contextId from.
133 regVal
[MISCREG_APIC_BASE
] = lApicBase
;
145 return dynamic_cast<const Params
*>(_params
);
149 ISA::readMiscRegNoEffect(int miscReg
) const
151 // Make sure we're not dealing with an illegal control register.
152 // Instructions should filter out these indexes, and nothing else should
153 // attempt to read them directly.
154 assert(isValidMiscReg(miscReg
));
156 return regVal
[miscReg
];
160 ISA::readMiscReg(int miscReg
, ThreadContext
* tc
)
162 if (miscReg
== MISCREG_TSC
) {
163 return regVal
[MISCREG_TSC
] + tc
->getCpuPtr()->curCycle();
166 if (miscReg
== MISCREG_FSW
) {
167 RegVal fsw
= regVal
[MISCREG_FSW
];
168 RegVal top
= regVal
[MISCREG_X87_TOP
];
169 return insertBits(fsw
, 13, 11, top
);
172 if (miscReg
== MISCREG_APIC_BASE
) {
173 LocalApicBase base
= regVal
[MISCREG_APIC_BASE
];
174 base
.bsp
= (tc
->contextId() == 0);
178 return readMiscRegNoEffect(miscReg
);
182 ISA::setMiscRegNoEffect(int miscReg
, RegVal val
)
184 // Make sure we're not dealing with an illegal control register.
185 // Instructions should filter out these indexes, and nothing else should
186 // attempt to write to them directly.
187 assert(isValidMiscReg(miscReg
));
189 HandyM5Reg m5Reg
= regVal
[MISCREG_M5_REG
];
192 case MISCREG_X87_TOP
:
208 if (m5Reg
.submode
!= SixtyFourBitMode
)
213 if (m5Reg
.submode
!= SixtyFourBitMode
)
220 regVal
[miscReg
] = val
& mask(reg_width
);
224 ISA::setMiscReg(int miscReg
, RegVal val
, ThreadContext
* tc
)
231 CR0 toggled
= regVal
[miscReg
] ^ val
;
233 Efer efer
= regVal
[MISCREG_EFER
];
234 if (toggled
.pg
&& efer
.lme
) {
236 //Turning on long mode
238 regVal
[MISCREG_EFER
] = efer
;
240 //Turning off long mode
242 regVal
[MISCREG_EFER
] = efer
;
246 dynamic_cast<TLB
*>(tc
->getITBPtr())->flushAll();
247 dynamic_cast<TLB
*>(tc
->getDTBPtr())->flushAll();
249 //This must always be 1.
252 updateHandyM5Reg(regVal
[MISCREG_EFER
],
254 regVal
[MISCREG_CS_ATTR
],
255 regVal
[MISCREG_SS_ATTR
],
256 regVal
[MISCREG_RFLAGS
],
263 dynamic_cast<TLB
*>(tc
->getITBPtr())->flushNonGlobal();
264 dynamic_cast<TLB
*>(tc
->getDTBPtr())->flushNonGlobal();
268 CR4 toggled
= regVal
[miscReg
] ^ val
;
269 if (toggled
.pae
|| toggled
.pse
|| toggled
.pge
) {
270 dynamic_cast<TLB
*>(tc
->getITBPtr())->flushAll();
271 dynamic_cast<TLB
*>(tc
->getDTBPtr())->flushAll();
277 case MISCREG_CS_ATTR
:
279 SegAttr toggled
= regVal
[miscReg
] ^ val
;
280 SegAttr newCSAttr
= val
;
281 if (toggled
.longMode
) {
282 if (newCSAttr
.longMode
) {
283 regVal
[MISCREG_ES_EFF_BASE
] = 0;
284 regVal
[MISCREG_CS_EFF_BASE
] = 0;
285 regVal
[MISCREG_SS_EFF_BASE
] = 0;
286 regVal
[MISCREG_DS_EFF_BASE
] = 0;
288 regVal
[MISCREG_ES_EFF_BASE
] = regVal
[MISCREG_ES_BASE
];
289 regVal
[MISCREG_CS_EFF_BASE
] = regVal
[MISCREG_CS_BASE
];
290 regVal
[MISCREG_SS_EFF_BASE
] = regVal
[MISCREG_SS_BASE
];
291 regVal
[MISCREG_DS_EFF_BASE
] = regVal
[MISCREG_DS_BASE
];
294 updateHandyM5Reg(regVal
[MISCREG_EFER
],
297 regVal
[MISCREG_SS_ATTR
],
298 regVal
[MISCREG_RFLAGS
],
302 case MISCREG_SS_ATTR
:
303 updateHandyM5Reg(regVal
[MISCREG_EFER
],
305 regVal
[MISCREG_CS_ATTR
],
307 regVal
[MISCREG_RFLAGS
],
310 // These segments always actually use their bases, or in other words
311 // their effective bases must stay equal to their actual bases.
312 case MISCREG_FS_BASE
:
313 case MISCREG_GS_BASE
:
314 case MISCREG_HS_BASE
:
315 case MISCREG_TSL_BASE
:
316 case MISCREG_TSG_BASE
:
317 case MISCREG_TR_BASE
:
318 case MISCREG_IDTR_BASE
:
319 regVal
[MISCREG_SEG_EFF_BASE(miscReg
- MISCREG_SEG_BASE_BASE
)] = val
;
321 // These segments ignore their bases in 64 bit mode.
322 // their effective bases must stay equal to their actual bases.
323 case MISCREG_ES_BASE
:
324 case MISCREG_CS_BASE
:
325 case MISCREG_SS_BASE
:
326 case MISCREG_DS_BASE
:
328 Efer efer
= regVal
[MISCREG_EFER
];
329 SegAttr csAttr
= regVal
[MISCREG_CS_ATTR
];
330 if (!efer
.lma
|| !csAttr
.longMode
) // Check for non 64 bit mode.
331 regVal
[MISCREG_SEG_EFF_BASE(miscReg
-
332 MISCREG_SEG_BASE_BASE
)] = val
;
336 regVal
[MISCREG_TSC
] = val
- tc
->getCpuPtr()->curCycle();
342 /* These should eventually set up breakpoints. */
345 miscReg
= MISCREG_DR6
;
349 DR6 dr6
= regVal
[MISCREG_DR6
];
362 miscReg
= MISCREG_DR7
;
366 DR7 dr7
= regVal
[MISCREG_DR7
];
370 if (dr7
.l0
|| dr7
.g0
) {
371 panic("Debug register breakpoints not implemented.\n");
373 /* Disable breakpoint 0. */
377 if (dr7
.l1
|| dr7
.g1
) {
378 panic("Debug register breakpoints not implemented.\n");
380 /* Disable breakpoint 1. */
384 if (dr7
.l2
|| dr7
.g2
) {
385 panic("Debug register breakpoints not implemented.\n");
387 /* Disable breakpoint 2. */
391 if (dr7
.l3
|| dr7
.g3
) {
392 panic("Debug register breakpoints not implemented.\n");
394 /* Disable breakpoint 3. */
397 dr7
.rw0
= newDR7
.rw0
;
398 dr7
.len0
= newDR7
.len0
;
399 dr7
.rw1
= newDR7
.rw1
;
400 dr7
.len1
= newDR7
.len1
;
401 dr7
.rw2
= newDR7
.rw2
;
402 dr7
.len2
= newDR7
.len2
;
403 dr7
.rw3
= newDR7
.rw3
;
404 dr7
.len3
= newDR7
.len3
;
408 // Writing anything to the m5reg with side effects makes it update
409 // based on the current values of the relevant registers. The actual
410 // value written is discarded.
411 updateHandyM5Reg(regVal
[MISCREG_EFER
],
413 regVal
[MISCREG_CS_ATTR
],
414 regVal
[MISCREG_SS_ATTR
],
415 regVal
[MISCREG_RFLAGS
],
421 setMiscRegNoEffect(miscReg
, newVal
);
425 ISA::serialize(CheckpointOut
&cp
) const
427 SERIALIZE_ARRAY(regVal
, NumMiscRegs
);
431 ISA::unserialize(CheckpointIn
&cp
)
433 UNSERIALIZE_ARRAY(regVal
, NumMiscRegs
);
434 updateHandyM5Reg(regVal
[MISCREG_EFER
],
436 regVal
[MISCREG_CS_ATTR
],
437 regVal
[MISCREG_SS_ATTR
],
438 regVal
[MISCREG_RFLAGS
],
443 ISA::startup(ThreadContext
*tc
)
445 tc
->getDecoderPtr()->setM5Reg(regVal
[MISCREG_M5_REG
]);
451 X86ISAParams::create()
453 return new X86ISA::ISA(this);