src/arch/x86/isa.cc

   1 /*
   2  * Copyright (c) 2009 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #include "arch/x86/isa.hh"
  32
  33 #include "arch/x86/decoder.hh"
  34 #include "arch/x86/tlb.hh"
  35 #include "cpu/base.hh"
  36 #include "cpu/thread_context.hh"
  37 #include "params/X86ISA.hh"
  38 #include "sim/serialize.hh"
  39
  40 namespace X86ISA
  41 {
  42
  43 void
  44 ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
  45                       SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
  46                       ThreadContext *tc)
  47 {
  48     HandyM5Reg m5reg = 0;
  49     if (efer.lma) {
  50         m5reg.mode = LongMode;
  51         if (csAttr.longMode)
  52             m5reg.submode = SixtyFourBitMode;
  53         else
  54             m5reg.submode = CompatabilityMode;
  55     } else {
  56         m5reg.mode = LegacyMode;
  57         if (cr0.pe) {
  58             if (rflags.vm)
  59                 m5reg.submode = Virtual8086Mode;
  60             else
  61                 m5reg.submode = ProtectedMode;
  62         } else {
  63             m5reg.submode = RealMode;
  64         }
  65     }
  66     m5reg.cpl = csAttr.dpl;
  67     m5reg.paging = cr0.pg;
  68     m5reg.prot = cr0.pe;
  69
  70     // Compute the default and alternate operand size.
  71     if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) {
  72         m5reg.defOp = 2;
  73         m5reg.altOp = 1;
  74     } else {
  75         m5reg.defOp = 1;
  76         m5reg.altOp = 2;
  77     }
  78
  79     // Compute the default and alternate address size.
  80     if (m5reg.submode == SixtyFourBitMode) {
  81         m5reg.defAddr = 3;
  82         m5reg.altAddr = 2;
  83     } else if (csAttr.defaultSize) {
  84         m5reg.defAddr = 2;
  85         m5reg.altAddr = 1;
  86     } else {
  87         m5reg.defAddr = 1;
  88         m5reg.altAddr = 2;
  89     }
  90
  91     // Compute the stack size
  92     if (m5reg.submode == SixtyFourBitMode) {
  93         m5reg.stack = 3;
  94     } else if (ssAttr.defaultSize) {
  95         m5reg.stack = 2;
  96     } else {
  97         m5reg.stack = 1;
  98     }
  99
 100     regVal[MISCREG_M5_REG] = m5reg;
 101     if (tc)
 102         tc->getDecoderPtr()->setM5Reg(m5reg);
 103 }
 104
 105 void
 106 ISA::clear()
 107 {
 108     // Blank everything. 0 might not be an appropriate value for some things,
 109     // but it is for most.
 110     memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
 111
 112     // If some state should be non-zero after a reset, set those values here.
 113     regVal[MISCREG_CR0] = 0x0000000060000010ULL;
 114
 115     regVal[MISCREG_MTRRCAP] = 0x0508;
 116
 117     regVal[MISCREG_MCG_CAP] = 0x104;
 118
 119     regVal[MISCREG_PAT] = 0x0007040600070406ULL;
 120
 121     regVal[MISCREG_SYSCFG] = 0x20601;
 122
 123     regVal[MISCREG_TOP_MEM] = 0x4000000;
 124
 125     regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
 126     regVal[MISCREG_DR7] = 1 << 10;
 127
 128     LocalApicBase lApicBase = 0;
 129     lApicBase.base = 0xFEE00000 >> 12;
 130     lApicBase.enable = 1;
 131     // The "bsp" bit will be set when this register is read, since then we'll
 132     // have a ThreadContext to check the contextId from.
 133     regVal[MISCREG_APIC_BASE] = lApicBase;
 134 }
 135
 136 ISA::ISA(Params *p)
 137     : SimObject(p)
 138 {
 139     clear();
 140 }
 141
 142 const X86ISAParams *
 143 ISA::params() const
 144 {
 145     return dynamic_cast<const Params *>(_params);
 146 }
 147
 148 RegVal
 149 ISA::readMiscRegNoEffect(int miscReg) const
 150 {
 151     // Make sure we're not dealing with an illegal control register.
 152     // Instructions should filter out these indexes, and nothing else should
 153     // attempt to read them directly.
 154     assert(isValidMiscReg(miscReg));
 155
 156     return regVal[miscReg];
 157 }
 158
 159 RegVal
 160 ISA::readMiscReg(int miscReg, ThreadContext * tc)
 161 {
 162     if (miscReg == MISCREG_TSC) {
 163         return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
 164     }
 165
 166     if (miscReg == MISCREG_FSW) {
 167         RegVal fsw = regVal[MISCREG_FSW];
 168         RegVal top = regVal[MISCREG_X87_TOP];
 169         return insertBits(fsw, 13, 11, top);
 170     }
 171
 172     if (miscReg == MISCREG_APIC_BASE) {
 173         LocalApicBase base = regVal[MISCREG_APIC_BASE];
 174         base.bsp = (tc->contextId() == 0);
 175         return base;
 176     }
 177
 178     return readMiscRegNoEffect(miscReg);
 179 }
 180
 181 void
 182 ISA::setMiscRegNoEffect(int miscReg, RegVal val)
 183 {
 184     // Make sure we're not dealing with an illegal control register.
 185     // Instructions should filter out these indexes, and nothing else should
 186     // attempt to write to them directly.
 187     assert(isValidMiscReg(miscReg));
 188
 189     HandyM5Reg m5Reg = regVal[MISCREG_M5_REG];
 190     int reg_width = 64;
 191     switch (miscReg) {
 192       case MISCREG_X87_TOP:
 193         reg_width = 3;
 194         break;
 195       case MISCREG_FTW:
 196         reg_width = 8;
 197         break;
 198       case MISCREG_FSW:
 199       case MISCREG_FCW:
 200       case MISCREG_FOP:
 201         reg_width = 16;
 202         break;
 203       case MISCREG_MXCSR:
 204         reg_width = 32;
 205         break;
 206       case MISCREG_FISEG:
 207       case MISCREG_FOSEG:
 208         if (m5Reg.submode != SixtyFourBitMode)
 209             reg_width = 16;
 210         break;
 211       case MISCREG_FIOFF:
 212       case MISCREG_FOOFF:
 213         if (m5Reg.submode != SixtyFourBitMode)
 214             reg_width = 32;
 215         break;
 216       default:
 217         break;
 218     }
 219
 220     regVal[miscReg] = val & mask(reg_width);
 221 }
 222
 223 void
 224 ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
 225 {
 226     RegVal newVal = val;
 227     switch(miscReg)
 228     {
 229       case MISCREG_CR0:
 230         {
 231             CR0 toggled = regVal[miscReg] ^ val;
 232             CR0 newCR0 = val;
 233             Efer efer = regVal[MISCREG_EFER];
 234             if (toggled.pg && efer.lme) {
 235                 if (newCR0.pg) {
 236                     //Turning on long mode
 237                     efer.lma = 1;
 238                     regVal[MISCREG_EFER] = efer;
 239                 } else {
 240                     //Turning off long mode
 241                     efer.lma = 0;
 242                     regVal[MISCREG_EFER] = efer;
 243                 }
 244             }
 245             if (toggled.pg) {
 246                 dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
 247                 dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
 248             }
 249             //This must always be 1.
 250             newCR0.et = 1;
 251             newVal = newCR0;
 252             updateHandyM5Reg(regVal[MISCREG_EFER],
 253                              newCR0,
 254                              regVal[MISCREG_CS_ATTR],
 255                              regVal[MISCREG_SS_ATTR],
 256                              regVal[MISCREG_RFLAGS],
 257                              tc);
 258         }
 259         break;
 260       case MISCREG_CR2:
 261         break;
 262       case MISCREG_CR3:
 263         dynamic_cast<TLB *>(tc->getITBPtr())->flushNonGlobal();
 264         dynamic_cast<TLB *>(tc->getDTBPtr())->flushNonGlobal();
 265         break;
 266       case MISCREG_CR4:
 267         {
 268             CR4 toggled = regVal[miscReg] ^ val;
 269             if (toggled.pae || toggled.pse || toggled.pge) {
 270                 dynamic_cast<TLB *>(tc->getITBPtr())->flushAll();
 271                 dynamic_cast<TLB *>(tc->getDTBPtr())->flushAll();
 272             }
 273         }
 274         break;
 275       case MISCREG_CR8:
 276         break;
 277       case MISCREG_CS_ATTR:
 278         {
 279             SegAttr toggled = regVal[miscReg] ^ val;
 280             SegAttr newCSAttr = val;
 281             if (toggled.longMode) {
 282                 if (newCSAttr.longMode) {
 283                     regVal[MISCREG_ES_EFF_BASE] = 0;
 284                     regVal[MISCREG_CS_EFF_BASE] = 0;
 285                     regVal[MISCREG_SS_EFF_BASE] = 0;
 286                     regVal[MISCREG_DS_EFF_BASE] = 0;
 287                 } else {
 288                     regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
 289                     regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
 290                     regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
 291                     regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
 292                 }
 293             }
 294             updateHandyM5Reg(regVal[MISCREG_EFER],
 295                              regVal[MISCREG_CR0],
 296                              newCSAttr,
 297                              regVal[MISCREG_SS_ATTR],
 298                              regVal[MISCREG_RFLAGS],
 299                              tc);
 300         }
 301         break;
 302       case MISCREG_SS_ATTR:
 303         updateHandyM5Reg(regVal[MISCREG_EFER],
 304                          regVal[MISCREG_CR0],
 305                          regVal[MISCREG_CS_ATTR],
 306                          val,
 307                          regVal[MISCREG_RFLAGS],
 308                          tc);
 309         break;
 310       // These segments always actually use their bases, or in other words
 311       // their effective bases must stay equal to their actual bases.
 312       case MISCREG_FS_BASE:
 313       case MISCREG_GS_BASE:
 314       case MISCREG_HS_BASE:
 315       case MISCREG_TSL_BASE:
 316       case MISCREG_TSG_BASE:
 317       case MISCREG_TR_BASE:
 318       case MISCREG_IDTR_BASE:
 319         regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
 320         break;
 321       // These segments ignore their bases in 64 bit mode.
 322       // their effective bases must stay equal to their actual bases.
 323       case MISCREG_ES_BASE:
 324       case MISCREG_CS_BASE:
 325       case MISCREG_SS_BASE:
 326       case MISCREG_DS_BASE:
 327         {
 328             Efer efer = regVal[MISCREG_EFER];
 329             SegAttr csAttr = regVal[MISCREG_CS_ATTR];
 330             if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
 331                 regVal[MISCREG_SEG_EFF_BASE(miscReg -
 332                         MISCREG_SEG_BASE_BASE)] = val;
 333         }
 334         break;
 335       case MISCREG_TSC:
 336         regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
 337         return;
 338       case MISCREG_DR0:
 339       case MISCREG_DR1:
 340       case MISCREG_DR2:
 341       case MISCREG_DR3:
 342         /* These should eventually set up breakpoints. */
 343         break;
 344       case MISCREG_DR4:
 345         miscReg = MISCREG_DR6;
 346         M5_FALLTHROUGH;
 347       case MISCREG_DR6:
 348         {
 349             DR6 dr6 = regVal[MISCREG_DR6];
 350             DR6 newDR6 = val;
 351             dr6.b0 = newDR6.b0;
 352             dr6.b1 = newDR6.b1;
 353             dr6.b2 = newDR6.b2;
 354             dr6.b3 = newDR6.b3;
 355             dr6.bd = newDR6.bd;
 356             dr6.bs = newDR6.bs;
 357             dr6.bt = newDR6.bt;
 358             newVal = dr6;
 359         }
 360         break;
 361       case MISCREG_DR5:
 362         miscReg = MISCREG_DR7;
 363         M5_FALLTHROUGH;
 364       case MISCREG_DR7:
 365         {
 366             DR7 dr7 = regVal[MISCREG_DR7];
 367             DR7 newDR7 = val;
 368             dr7.l0 = newDR7.l0;
 369             dr7.g0 = newDR7.g0;
 370             if (dr7.l0 || dr7.g0) {
 371                 panic("Debug register breakpoints not implemented.\n");
 372             } else {
 373                 /* Disable breakpoint 0. */
 374             }
 375             dr7.l1 = newDR7.l1;
 376             dr7.g1 = newDR7.g1;
 377             if (dr7.l1 || dr7.g1) {
 378                 panic("Debug register breakpoints not implemented.\n");
 379             } else {
 380                 /* Disable breakpoint 1. */
 381             }
 382             dr7.l2 = newDR7.l2;
 383             dr7.g2 = newDR7.g2;
 384             if (dr7.l2 || dr7.g2) {
 385                 panic("Debug register breakpoints not implemented.\n");
 386             } else {
 387                 /* Disable breakpoint 2. */
 388             }
 389             dr7.l3 = newDR7.l3;
 390             dr7.g3 = newDR7.g3;
 391             if (dr7.l3 || dr7.g3) {
 392                 panic("Debug register breakpoints not implemented.\n");
 393             } else {
 394                 /* Disable breakpoint 3. */
 395             }
 396             dr7.gd = newDR7.gd;
 397             dr7.rw0 = newDR7.rw0;
 398             dr7.len0 = newDR7.len0;
 399             dr7.rw1 = newDR7.rw1;
 400             dr7.len1 = newDR7.len1;
 401             dr7.rw2 = newDR7.rw2;
 402             dr7.len2 = newDR7.len2;
 403             dr7.rw3 = newDR7.rw3;
 404             dr7.len3 = newDR7.len3;
 405         }
 406         break;
 407       case MISCREG_M5_REG:
 408         // Writing anything to the m5reg with side effects makes it update
 409         // based on the current values of the relevant registers. The actual
 410         // value written is discarded.
 411         updateHandyM5Reg(regVal[MISCREG_EFER],
 412                          regVal[MISCREG_CR0],
 413                          regVal[MISCREG_CS_ATTR],
 414                          regVal[MISCREG_SS_ATTR],
 415                          regVal[MISCREG_RFLAGS],
 416                          tc);
 417         return;
 418       default:
 419         break;
 420     }
 421     setMiscRegNoEffect(miscReg, newVal);
 422 }
 423
 424 void
 425 ISA::serialize(CheckpointOut &cp) const
 426 {
 427     SERIALIZE_ARRAY(regVal, NumMiscRegs);
 428 }
 429
 430 void
 431 ISA::unserialize(CheckpointIn &cp)
 432 {
 433     UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
 434     updateHandyM5Reg(regVal[MISCREG_EFER],
 435                      regVal[MISCREG_CR0],
 436                      regVal[MISCREG_CS_ATTR],
 437                      regVal[MISCREG_SS_ATTR],
 438                      regVal[MISCREG_RFLAGS],
 439                      NULL);
 440 }
 441
 442 void
 443 ISA::startup(ThreadContext *tc)
 444 {
 445     tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]);
 446 }
 447
 448 }
 449
 450 X86ISA::ISA *
 451 X86ISAParams::create()
 452 {
 453     return new X86ISA::ISA(this);
 454 }