2 * Copyright (c) 2009 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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31 #include "arch/x86/decoder.hh"
32 #include "arch/x86/isa.hh"
33 #include "arch/x86/tlb.hh"
34 #include "cpu/base.hh"
35 #include "cpu/thread_context.hh"
36 #include "params/X86ISA.hh"
37 #include "sim/serialize.hh"
43 ISA::updateHandyM5Reg(Efer efer
, CR0 cr0
,
44 SegAttr csAttr
, SegAttr ssAttr
, RFLAGS rflags
,
49 m5reg
.mode
= LongMode
;
51 m5reg
.submode
= SixtyFourBitMode
;
53 m5reg
.submode
= CompatabilityMode
;
55 m5reg
.mode
= LegacyMode
;
58 m5reg
.submode
= Virtual8086Mode
;
60 m5reg
.submode
= ProtectedMode
;
62 m5reg
.submode
= RealMode
;
65 m5reg
.cpl
= csAttr
.dpl
;
66 m5reg
.paging
= cr0
.pg
;
69 // Compute the default and alternate operand size.
70 if (m5reg
.submode
== SixtyFourBitMode
|| csAttr
.defaultSize
) {
78 // Compute the default and alternate address size.
79 if (m5reg
.submode
== SixtyFourBitMode
) {
82 } else if (csAttr
.defaultSize
) {
90 // Compute the stack size
91 if (m5reg
.submode
== SixtyFourBitMode
) {
93 } else if (ssAttr
.defaultSize
) {
99 regVal
[MISCREG_M5_REG
] = m5reg
;
101 tc
->getDecoderPtr()->setM5Reg(m5reg
);
107 // Blank everything. 0 might not be an appropriate value for some things,
108 // but it is for most.
109 memset(regVal
, 0, NumMiscRegs
* sizeof(MiscReg
));
110 regVal
[MISCREG_DR6
] = (mask(8) << 4) | (mask(16) << 16);
111 regVal
[MISCREG_DR7
] = 1 << 10;
123 return dynamic_cast<const Params
*>(_params
);
127 ISA::readMiscRegNoEffect(int miscReg
) const
129 // Make sure we're not dealing with an illegal control register.
130 // Instructions should filter out these indexes, and nothing else should
131 // attempt to read them directly.
132 assert(isValidMiscReg(miscReg
));
134 return regVal
[miscReg
];
138 ISA::readMiscReg(int miscReg
, ThreadContext
* tc
)
140 if (miscReg
== MISCREG_TSC
) {
141 return regVal
[MISCREG_TSC
] + tc
->getCpuPtr()->curCycle();
144 if (miscReg
== MISCREG_FSW
) {
145 MiscReg fsw
= regVal
[MISCREG_FSW
];
146 MiscReg top
= regVal
[MISCREG_X87_TOP
];
147 return (fsw
& (~(7ULL << 11))) + (top
<< 11);
150 return readMiscRegNoEffect(miscReg
);
154 ISA::setMiscRegNoEffect(int miscReg
, MiscReg val
)
156 // Make sure we're not dealing with an illegal control register.
157 // Instructions should filter out these indexes, and nothing else should
158 // attempt to write to them directly.
159 assert(isValidMiscReg(miscReg
));
161 HandyM5Reg m5Reg
= readMiscRegNoEffect(MISCREG_M5_REG
);
164 val
&= (1ULL << 16) - 1;
165 regVal
[miscReg
] = val
;
166 miscReg
= MISCREG_X87_TOP
;
168 case MISCREG_X87_TOP
:
169 val
&= (1ULL << 3) - 1;
172 val
&= (1ULL << 8) - 1;
176 val
&= (1ULL << 16) - 1;
179 val
&= (1ULL << 32) - 1;
183 if (m5Reg
.submode
!= SixtyFourBitMode
)
184 val
&= (1ULL << 16) - 1;
188 if (m5Reg
.submode
!= SixtyFourBitMode
)
189 val
&= (1ULL << 32) - 1;
195 regVal
[miscReg
] = val
;
199 ISA::setMiscReg(int miscReg
, MiscReg val
, ThreadContext
* tc
)
201 MiscReg newVal
= val
;
206 CR0 toggled
= regVal
[miscReg
] ^ val
;
208 Efer efer
= regVal
[MISCREG_EFER
];
209 if (toggled
.pg
&& efer
.lme
) {
211 //Turning on long mode
213 regVal
[MISCREG_EFER
] = efer
;
215 //Turning off long mode
217 regVal
[MISCREG_EFER
] = efer
;
221 tc
->getITBPtr()->flushAll();
222 tc
->getDTBPtr()->flushAll();
224 //This must always be 1.
227 updateHandyM5Reg(regVal
[MISCREG_EFER
],
229 regVal
[MISCREG_CS_ATTR
],
230 regVal
[MISCREG_SS_ATTR
],
231 regVal
[MISCREG_RFLAGS
],
238 tc
->getITBPtr()->flushNonGlobal();
239 tc
->getDTBPtr()->flushNonGlobal();
243 CR4 toggled
= regVal
[miscReg
] ^ val
;
244 if (toggled
.pae
|| toggled
.pse
|| toggled
.pge
) {
245 tc
->getITBPtr()->flushAll();
246 tc
->getDTBPtr()->flushAll();
252 case MISCREG_CS_ATTR
:
254 SegAttr toggled
= regVal
[miscReg
] ^ val
;
255 SegAttr newCSAttr
= val
;
256 if (toggled
.longMode
) {
257 if (newCSAttr
.longMode
) {
258 regVal
[MISCREG_ES_EFF_BASE
] = 0;
259 regVal
[MISCREG_CS_EFF_BASE
] = 0;
260 regVal
[MISCREG_SS_EFF_BASE
] = 0;
261 regVal
[MISCREG_DS_EFF_BASE
] = 0;
263 regVal
[MISCREG_ES_EFF_BASE
] = regVal
[MISCREG_ES_BASE
];
264 regVal
[MISCREG_CS_EFF_BASE
] = regVal
[MISCREG_CS_BASE
];
265 regVal
[MISCREG_SS_EFF_BASE
] = regVal
[MISCREG_SS_BASE
];
266 regVal
[MISCREG_DS_EFF_BASE
] = regVal
[MISCREG_DS_BASE
];
269 updateHandyM5Reg(regVal
[MISCREG_EFER
],
272 regVal
[MISCREG_SS_ATTR
],
273 regVal
[MISCREG_RFLAGS
],
277 case MISCREG_SS_ATTR
:
278 updateHandyM5Reg(regVal
[MISCREG_EFER
],
280 regVal
[MISCREG_CS_ATTR
],
282 regVal
[MISCREG_RFLAGS
],
285 // These segments always actually use their bases, or in other words
286 // their effective bases must stay equal to their actual bases.
287 case MISCREG_FS_BASE
:
288 case MISCREG_GS_BASE
:
289 case MISCREG_HS_BASE
:
290 case MISCREG_TSL_BASE
:
291 case MISCREG_TSG_BASE
:
292 case MISCREG_TR_BASE
:
293 case MISCREG_IDTR_BASE
:
294 regVal
[MISCREG_SEG_EFF_BASE(miscReg
- MISCREG_SEG_BASE_BASE
)] = val
;
296 // These segments ignore their bases in 64 bit mode.
297 // their effective bases must stay equal to their actual bases.
298 case MISCREG_ES_BASE
:
299 case MISCREG_CS_BASE
:
300 case MISCREG_SS_BASE
:
301 case MISCREG_DS_BASE
:
303 Efer efer
= regVal
[MISCREG_EFER
];
304 SegAttr csAttr
= regVal
[MISCREG_CS_ATTR
];
305 if (!efer
.lma
|| !csAttr
.longMode
) // Check for non 64 bit mode.
306 regVal
[MISCREG_SEG_EFF_BASE(miscReg
-
307 MISCREG_SEG_BASE_BASE
)] = val
;
311 regVal
[MISCREG_TSC
] = val
- tc
->getCpuPtr()->curCycle();
317 /* These should eventually set up breakpoints. */
320 miscReg
= MISCREG_DR6
;
321 /* Fall through to have the same effects as DR6. */
324 DR6 dr6
= regVal
[MISCREG_DR6
];
337 miscReg
= MISCREG_DR7
;
338 /* Fall through to have the same effects as DR7. */
341 DR7 dr7
= regVal
[MISCREG_DR7
];
345 if (dr7
.l0
|| dr7
.g0
) {
346 panic("Debug register breakpoints not implemented.\n");
348 /* Disable breakpoint 0. */
352 if (dr7
.l1
|| dr7
.g1
) {
353 panic("Debug register breakpoints not implemented.\n");
355 /* Disable breakpoint 1. */
359 if (dr7
.l2
|| dr7
.g2
) {
360 panic("Debug register breakpoints not implemented.\n");
362 /* Disable breakpoint 2. */
366 if (dr7
.l3
|| dr7
.g3
) {
367 panic("Debug register breakpoints not implemented.\n");
369 /* Disable breakpoint 3. */
372 dr7
.rw0
= newDR7
.rw0
;
373 dr7
.len0
= newDR7
.len0
;
374 dr7
.rw1
= newDR7
.rw1
;
375 dr7
.len1
= newDR7
.len1
;
376 dr7
.rw2
= newDR7
.rw2
;
377 dr7
.len2
= newDR7
.len2
;
378 dr7
.rw3
= newDR7
.rw3
;
379 dr7
.len3
= newDR7
.len3
;
383 // Writing anything to the m5reg with side effects makes it update
384 // based on the current values of the relevant registers. The actual
385 // value written is discarded.
386 updateHandyM5Reg(regVal
[MISCREG_EFER
],
388 regVal
[MISCREG_CS_ATTR
],
389 regVal
[MISCREG_SS_ATTR
],
390 regVal
[MISCREG_RFLAGS
],
396 setMiscRegNoEffect(miscReg
, newVal
);
400 ISA::serialize(CheckpointOut
&cp
) const
402 SERIALIZE_ARRAY(regVal
, NumMiscRegs
);
406 ISA::unserialize(CheckpointIn
&cp
)
408 UNSERIALIZE_ARRAY(regVal
, NumMiscRegs
);
409 updateHandyM5Reg(regVal
[MISCREG_EFER
],
411 regVal
[MISCREG_CS_ATTR
],
412 regVal
[MISCREG_SS_ATTR
],
413 regVal
[MISCREG_RFLAGS
],
418 ISA::startup(ThreadContext
*tc
)
420 tc
->getDecoderPtr()->setM5Reg(regVal
[MISCREG_M5_REG
]);
426 X86ISAParams::create()
428 return new X86ISA::ISA(this);