2 * Copyright (c) 2009 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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31 #include "arch/x86/isa.hh"
33 #include "arch/x86/decoder.hh"
34 #include "arch/x86/tlb.hh"
35 #include "cpu/base.hh"
36 #include "cpu/thread_context.hh"
37 #include "params/X86ISA.hh"
38 #include "sim/serialize.hh"
44 ISA::updateHandyM5Reg(Efer efer
, CR0 cr0
,
45 SegAttr csAttr
, SegAttr ssAttr
, RFLAGS rflags
,
50 m5reg
.mode
= LongMode
;
52 m5reg
.submode
= SixtyFourBitMode
;
54 m5reg
.submode
= CompatabilityMode
;
56 m5reg
.mode
= LegacyMode
;
59 m5reg
.submode
= Virtual8086Mode
;
61 m5reg
.submode
= ProtectedMode
;
63 m5reg
.submode
= RealMode
;
66 m5reg
.cpl
= csAttr
.dpl
;
67 m5reg
.paging
= cr0
.pg
;
70 // Compute the default and alternate operand size.
71 if (m5reg
.submode
== SixtyFourBitMode
|| csAttr
.defaultSize
) {
79 // Compute the default and alternate address size.
80 if (m5reg
.submode
== SixtyFourBitMode
) {
83 } else if (csAttr
.defaultSize
) {
91 // Compute the stack size
92 if (m5reg
.submode
== SixtyFourBitMode
) {
94 } else if (ssAttr
.defaultSize
) {
100 regVal
[MISCREG_M5_REG
] = m5reg
;
102 tc
->getDecoderPtr()->setM5Reg(m5reg
);
108 // Blank everything. 0 might not be an appropriate value for some things,
109 // but it is for most.
110 memset(regVal
, 0, NumMiscRegs
* sizeof(MiscReg
));
111 regVal
[MISCREG_DR6
] = (mask(8) << 4) | (mask(16) << 16);
112 regVal
[MISCREG_DR7
] = 1 << 10;
124 return dynamic_cast<const Params
*>(_params
);
128 ISA::readMiscRegNoEffect(int miscReg
) const
130 // Make sure we're not dealing with an illegal control register.
131 // Instructions should filter out these indexes, and nothing else should
132 // attempt to read them directly.
133 assert(isValidMiscReg(miscReg
));
135 return regVal
[miscReg
];
139 ISA::readMiscReg(int miscReg
, ThreadContext
* tc
)
141 if (miscReg
== MISCREG_TSC
) {
142 return regVal
[MISCREG_TSC
] + tc
->getCpuPtr()->curCycle();
145 if (miscReg
== MISCREG_FSW
) {
146 MiscReg fsw
= regVal
[MISCREG_FSW
];
147 MiscReg top
= regVal
[MISCREG_X87_TOP
];
148 return insertBits(fsw
, 11, 13, top
);
151 return readMiscRegNoEffect(miscReg
);
155 ISA::setMiscRegNoEffect(int miscReg
, MiscReg val
)
157 // Make sure we're not dealing with an illegal control register.
158 // Instructions should filter out these indexes, and nothing else should
159 // attempt to write to them directly.
160 assert(isValidMiscReg(miscReg
));
162 HandyM5Reg m5Reg
= regVal
[MISCREG_M5_REG
];
165 case MISCREG_X87_TOP
:
181 if (m5Reg
.submode
!= SixtyFourBitMode
)
186 if (m5Reg
.submode
!= SixtyFourBitMode
)
193 regVal
[miscReg
] = val
& mask(reg_width
);
197 ISA::setMiscReg(int miscReg
, MiscReg val
, ThreadContext
* tc
)
199 MiscReg newVal
= val
;
204 CR0 toggled
= regVal
[miscReg
] ^ val
;
206 Efer efer
= regVal
[MISCREG_EFER
];
207 if (toggled
.pg
&& efer
.lme
) {
209 //Turning on long mode
211 regVal
[MISCREG_EFER
] = efer
;
213 //Turning off long mode
215 regVal
[MISCREG_EFER
] = efer
;
219 tc
->getITBPtr()->flushAll();
220 tc
->getDTBPtr()->flushAll();
222 //This must always be 1.
225 updateHandyM5Reg(regVal
[MISCREG_EFER
],
227 regVal
[MISCREG_CS_ATTR
],
228 regVal
[MISCREG_SS_ATTR
],
229 regVal
[MISCREG_RFLAGS
],
236 tc
->getITBPtr()->flushNonGlobal();
237 tc
->getDTBPtr()->flushNonGlobal();
241 CR4 toggled
= regVal
[miscReg
] ^ val
;
242 if (toggled
.pae
|| toggled
.pse
|| toggled
.pge
) {
243 tc
->getITBPtr()->flushAll();
244 tc
->getDTBPtr()->flushAll();
250 case MISCREG_CS_ATTR
:
252 SegAttr toggled
= regVal
[miscReg
] ^ val
;
253 SegAttr newCSAttr
= val
;
254 if (toggled
.longMode
) {
255 if (newCSAttr
.longMode
) {
256 regVal
[MISCREG_ES_EFF_BASE
] = 0;
257 regVal
[MISCREG_CS_EFF_BASE
] = 0;
258 regVal
[MISCREG_SS_EFF_BASE
] = 0;
259 regVal
[MISCREG_DS_EFF_BASE
] = 0;
261 regVal
[MISCREG_ES_EFF_BASE
] = regVal
[MISCREG_ES_BASE
];
262 regVal
[MISCREG_CS_EFF_BASE
] = regVal
[MISCREG_CS_BASE
];
263 regVal
[MISCREG_SS_EFF_BASE
] = regVal
[MISCREG_SS_BASE
];
264 regVal
[MISCREG_DS_EFF_BASE
] = regVal
[MISCREG_DS_BASE
];
267 updateHandyM5Reg(regVal
[MISCREG_EFER
],
270 regVal
[MISCREG_SS_ATTR
],
271 regVal
[MISCREG_RFLAGS
],
275 case MISCREG_SS_ATTR
:
276 updateHandyM5Reg(regVal
[MISCREG_EFER
],
278 regVal
[MISCREG_CS_ATTR
],
280 regVal
[MISCREG_RFLAGS
],
283 // These segments always actually use their bases, or in other words
284 // their effective bases must stay equal to their actual bases.
285 case MISCREG_FS_BASE
:
286 case MISCREG_GS_BASE
:
287 case MISCREG_HS_BASE
:
288 case MISCREG_TSL_BASE
:
289 case MISCREG_TSG_BASE
:
290 case MISCREG_TR_BASE
:
291 case MISCREG_IDTR_BASE
:
292 regVal
[MISCREG_SEG_EFF_BASE(miscReg
- MISCREG_SEG_BASE_BASE
)] = val
;
294 // These segments ignore their bases in 64 bit mode.
295 // their effective bases must stay equal to their actual bases.
296 case MISCREG_ES_BASE
:
297 case MISCREG_CS_BASE
:
298 case MISCREG_SS_BASE
:
299 case MISCREG_DS_BASE
:
301 Efer efer
= regVal
[MISCREG_EFER
];
302 SegAttr csAttr
= regVal
[MISCREG_CS_ATTR
];
303 if (!efer
.lma
|| !csAttr
.longMode
) // Check for non 64 bit mode.
304 regVal
[MISCREG_SEG_EFF_BASE(miscReg
-
305 MISCREG_SEG_BASE_BASE
)] = val
;
309 regVal
[MISCREG_TSC
] = val
- tc
->getCpuPtr()->curCycle();
315 /* These should eventually set up breakpoints. */
318 miscReg
= MISCREG_DR6
;
322 DR6 dr6
= regVal
[MISCREG_DR6
];
335 miscReg
= MISCREG_DR7
;
339 DR7 dr7
= regVal
[MISCREG_DR7
];
343 if (dr7
.l0
|| dr7
.g0
) {
344 panic("Debug register breakpoints not implemented.\n");
346 /* Disable breakpoint 0. */
350 if (dr7
.l1
|| dr7
.g1
) {
351 panic("Debug register breakpoints not implemented.\n");
353 /* Disable breakpoint 1. */
357 if (dr7
.l2
|| dr7
.g2
) {
358 panic("Debug register breakpoints not implemented.\n");
360 /* Disable breakpoint 2. */
364 if (dr7
.l3
|| dr7
.g3
) {
365 panic("Debug register breakpoints not implemented.\n");
367 /* Disable breakpoint 3. */
370 dr7
.rw0
= newDR7
.rw0
;
371 dr7
.len0
= newDR7
.len0
;
372 dr7
.rw1
= newDR7
.rw1
;
373 dr7
.len1
= newDR7
.len1
;
374 dr7
.rw2
= newDR7
.rw2
;
375 dr7
.len2
= newDR7
.len2
;
376 dr7
.rw3
= newDR7
.rw3
;
377 dr7
.len3
= newDR7
.len3
;
381 // Writing anything to the m5reg with side effects makes it update
382 // based on the current values of the relevant registers. The actual
383 // value written is discarded.
384 updateHandyM5Reg(regVal
[MISCREG_EFER
],
386 regVal
[MISCREG_CS_ATTR
],
387 regVal
[MISCREG_SS_ATTR
],
388 regVal
[MISCREG_RFLAGS
],
394 setMiscRegNoEffect(miscReg
, newVal
);
398 ISA::serialize(CheckpointOut
&cp
) const
400 SERIALIZE_ARRAY(regVal
, NumMiscRegs
);
404 ISA::unserialize(CheckpointIn
&cp
)
406 UNSERIALIZE_ARRAY(regVal
, NumMiscRegs
);
407 updateHandyM5Reg(regVal
[MISCREG_EFER
],
409 regVal
[MISCREG_CS_ATTR
],
410 regVal
[MISCREG_SS_ATTR
],
411 regVal
[MISCREG_RFLAGS
],
416 ISA::startup(ThreadContext
*tc
)
418 tc
->getDecoderPtr()->setM5Reg(regVal
[MISCREG_M5_REG
]);
424 X86ISAParams::create()
426 return new X86ISA::ISA(this);