2 * Copyright (c) 2009 The Regents of The University of Michigan
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31 #include "arch/x86/decoder.hh"
32 #include "arch/x86/isa.hh"
33 #include "arch/x86/tlb.hh"
34 #include "cpu/base.hh"
35 #include "cpu/thread_context.hh"
36 #include "params/X86ISA.hh"
37 #include "sim/serialize.hh"
43 ISA::updateHandyM5Reg(Efer efer
, CR0 cr0
,
44 SegAttr csAttr
, SegAttr ssAttr
, RFLAGS rflags
,
49 m5reg
.mode
= LongMode
;
51 m5reg
.submode
= SixtyFourBitMode
;
53 m5reg
.submode
= CompatabilityMode
;
55 m5reg
.mode
= LegacyMode
;
58 m5reg
.submode
= Virtual8086Mode
;
60 m5reg
.submode
= ProtectedMode
;
62 m5reg
.submode
= RealMode
;
65 m5reg
.cpl
= csAttr
.dpl
;
66 m5reg
.paging
= cr0
.pg
;
69 // Compute the default and alternate operand size.
70 if (m5reg
.submode
== SixtyFourBitMode
|| csAttr
.defaultSize
) {
78 // Compute the default and alternate address size.
79 if (m5reg
.submode
== SixtyFourBitMode
) {
82 } else if (csAttr
.defaultSize
) {
90 // Compute the stack size
91 if (m5reg
.submode
== SixtyFourBitMode
) {
93 } else if (ssAttr
.defaultSize
) {
99 regVal
[MISCREG_M5_REG
] = m5reg
;
101 tc
->getDecoderPtr()->setM5Reg(m5reg
);
107 // Blank everything. 0 might not be an appropriate value for some things,
108 // but it is for most.
109 memset(regVal
, 0, NumMiscRegs
* sizeof(MiscReg
));
110 regVal
[MISCREG_DR6
] = (mask(8) << 4) | (mask(16) << 16);
111 regVal
[MISCREG_DR7
] = 1 << 10;
123 return dynamic_cast<const Params
*>(_params
);
127 ISA::readMiscRegNoEffect(int miscReg
) const
129 // Make sure we're not dealing with an illegal control register.
130 // Instructions should filter out these indexes, and nothing else should
131 // attempt to read them directly.
132 assert(miscReg
>= MISCREG_CR0
&&
133 miscReg
< NUM_MISCREGS
&&
134 miscReg
!= MISCREG_CR1
&&
135 !(miscReg
> MISCREG_CR4
&&
136 miscReg
< MISCREG_CR8
) &&
137 !(miscReg
> MISCREG_CR8
&&
138 miscReg
<= MISCREG_CR15
));
140 return regVal
[miscReg
];
144 ISA::readMiscReg(int miscReg
, ThreadContext
* tc
)
146 if (miscReg
== MISCREG_TSC
) {
147 return regVal
[MISCREG_TSC
] + tc
->getCpuPtr()->curCycle();
150 if (miscReg
== MISCREG_FSW
) {
151 MiscReg fsw
= regVal
[MISCREG_FSW
];
152 MiscReg top
= regVal
[MISCREG_X87_TOP
];
153 return (fsw
& (~(7ULL << 11))) + (top
<< 11);
156 return readMiscRegNoEffect(miscReg
);
160 ISA::setMiscRegNoEffect(int miscReg
, MiscReg val
)
162 // Make sure we're not dealing with an illegal control register.
163 // Instructions should filter out these indexes, and nothing else should
164 // attempt to write to them directly.
165 assert(miscReg
>= MISCREG_CR0
&&
166 miscReg
< NUM_MISCREGS
&&
167 miscReg
!= MISCREG_CR1
&&
168 !(miscReg
> MISCREG_CR4
&&
169 miscReg
< MISCREG_CR8
) &&
170 !(miscReg
> MISCREG_CR8
&&
171 miscReg
<= MISCREG_CR15
));
173 HandyM5Reg m5Reg
= readMiscRegNoEffect(MISCREG_M5_REG
);
176 val
&= (1ULL << 16) - 1;
177 regVal
[miscReg
] = val
;
178 miscReg
= MISCREG_X87_TOP
;
180 case MISCREG_X87_TOP
:
181 val
&= (1ULL << 3) - 1;
184 val
&= (1ULL << 8) - 1;
188 val
&= (1ULL << 16) - 1;
191 val
&= (1ULL << 32) - 1;
195 if (m5Reg
.submode
!= SixtyFourBitMode
)
196 val
&= (1ULL << 16) - 1;
200 if (m5Reg
.submode
!= SixtyFourBitMode
)
201 val
&= (1ULL << 32) - 1;
207 regVal
[miscReg
] = val
;
211 ISA::setMiscReg(int miscReg
, MiscReg val
, ThreadContext
* tc
)
213 MiscReg newVal
= val
;
218 CR0 toggled
= regVal
[miscReg
] ^ val
;
220 Efer efer
= regVal
[MISCREG_EFER
];
221 if (toggled
.pg
&& efer
.lme
) {
223 //Turning on long mode
225 regVal
[MISCREG_EFER
] = efer
;
227 //Turning off long mode
229 regVal
[MISCREG_EFER
] = efer
;
233 tc
->getITBPtr()->flushAll();
234 tc
->getDTBPtr()->flushAll();
236 //This must always be 1.
239 updateHandyM5Reg(regVal
[MISCREG_EFER
],
241 regVal
[MISCREG_CS_ATTR
],
242 regVal
[MISCREG_SS_ATTR
],
243 regVal
[MISCREG_RFLAGS
],
250 tc
->getITBPtr()->flushNonGlobal();
251 tc
->getDTBPtr()->flushNonGlobal();
255 CR4 toggled
= regVal
[miscReg
] ^ val
;
256 if (toggled
.pae
|| toggled
.pse
|| toggled
.pge
) {
257 tc
->getITBPtr()->flushAll();
258 tc
->getDTBPtr()->flushAll();
264 case MISCREG_CS_ATTR
:
266 SegAttr toggled
= regVal
[miscReg
] ^ val
;
267 SegAttr newCSAttr
= val
;
268 if (toggled
.longMode
) {
269 if (newCSAttr
.longMode
) {
270 regVal
[MISCREG_ES_EFF_BASE
] = 0;
271 regVal
[MISCREG_CS_EFF_BASE
] = 0;
272 regVal
[MISCREG_SS_EFF_BASE
] = 0;
273 regVal
[MISCREG_DS_EFF_BASE
] = 0;
275 regVal
[MISCREG_ES_EFF_BASE
] = regVal
[MISCREG_ES_BASE
];
276 regVal
[MISCREG_CS_EFF_BASE
] = regVal
[MISCREG_CS_BASE
];
277 regVal
[MISCREG_SS_EFF_BASE
] = regVal
[MISCREG_SS_BASE
];
278 regVal
[MISCREG_DS_EFF_BASE
] = regVal
[MISCREG_DS_BASE
];
281 updateHandyM5Reg(regVal
[MISCREG_EFER
],
284 regVal
[MISCREG_SS_ATTR
],
285 regVal
[MISCREG_RFLAGS
],
289 case MISCREG_SS_ATTR
:
290 updateHandyM5Reg(regVal
[MISCREG_EFER
],
292 regVal
[MISCREG_CS_ATTR
],
294 regVal
[MISCREG_RFLAGS
],
297 // These segments always actually use their bases, or in other words
298 // their effective bases must stay equal to their actual bases.
299 case MISCREG_FS_BASE
:
300 case MISCREG_GS_BASE
:
301 case MISCREG_HS_BASE
:
302 case MISCREG_TSL_BASE
:
303 case MISCREG_TSG_BASE
:
304 case MISCREG_TR_BASE
:
305 case MISCREG_IDTR_BASE
:
306 regVal
[MISCREG_SEG_EFF_BASE(miscReg
- MISCREG_SEG_BASE_BASE
)] = val
;
308 // These segments ignore their bases in 64 bit mode.
309 // their effective bases must stay equal to their actual bases.
310 case MISCREG_ES_BASE
:
311 case MISCREG_CS_BASE
:
312 case MISCREG_SS_BASE
:
313 case MISCREG_DS_BASE
:
315 Efer efer
= regVal
[MISCREG_EFER
];
316 SegAttr csAttr
= regVal
[MISCREG_CS_ATTR
];
317 if (!efer
.lma
|| !csAttr
.longMode
) // Check for non 64 bit mode.
318 regVal
[MISCREG_SEG_EFF_BASE(miscReg
-
319 MISCREG_SEG_BASE_BASE
)] = val
;
323 regVal
[MISCREG_TSC
] = val
- tc
->getCpuPtr()->curCycle();
329 /* These should eventually set up breakpoints. */
332 miscReg
= MISCREG_DR6
;
333 /* Fall through to have the same effects as DR6. */
336 DR6 dr6
= regVal
[MISCREG_DR6
];
349 miscReg
= MISCREG_DR7
;
350 /* Fall through to have the same effects as DR7. */
353 DR7 dr7
= regVal
[MISCREG_DR7
];
357 if (dr7
.l0
|| dr7
.g0
) {
358 panic("Debug register breakpoints not implemented.\n");
360 /* Disable breakpoint 0. */
364 if (dr7
.l1
|| dr7
.g1
) {
365 panic("Debug register breakpoints not implemented.\n");
367 /* Disable breakpoint 1. */
371 if (dr7
.l2
|| dr7
.g2
) {
372 panic("Debug register breakpoints not implemented.\n");
374 /* Disable breakpoint 2. */
378 if (dr7
.l3
|| dr7
.g3
) {
379 panic("Debug register breakpoints not implemented.\n");
381 /* Disable breakpoint 3. */
384 dr7
.rw0
= newDR7
.rw0
;
385 dr7
.len0
= newDR7
.len0
;
386 dr7
.rw1
= newDR7
.rw1
;
387 dr7
.len1
= newDR7
.len1
;
388 dr7
.rw2
= newDR7
.rw2
;
389 dr7
.len2
= newDR7
.len2
;
390 dr7
.rw3
= newDR7
.rw3
;
391 dr7
.len3
= newDR7
.len3
;
395 // Writing anything to the m5reg with side effects makes it update
396 // based on the current values of the relevant registers. The actual
397 // value written is discarded.
398 updateHandyM5Reg(regVal
[MISCREG_EFER
],
400 regVal
[MISCREG_CS_ATTR
],
401 regVal
[MISCREG_SS_ATTR
],
402 regVal
[MISCREG_RFLAGS
],
408 setMiscRegNoEffect(miscReg
, newVal
);
412 ISA::serialize(CheckpointOut
&cp
) const
414 SERIALIZE_ARRAY(regVal
, NumMiscRegs
);
418 ISA::unserialize(CheckpointIn
&cp
)
420 UNSERIALIZE_ARRAY(regVal
, NumMiscRegs
);
421 updateHandyM5Reg(regVal
[MISCREG_EFER
],
423 regVal
[MISCREG_CS_ATTR
],
424 regVal
[MISCREG_SS_ATTR
],
425 regVal
[MISCREG_RFLAGS
],
430 ISA::startup(ThreadContext
*tc
)
432 tc
->getDecoderPtr()->setM5Reg(regVal
[MISCREG_M5_REG
]);
438 X86ISAParams::create()
440 return new X86ISA::ISA(this);