2 * Copyright (c) 2009 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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31 #include "arch/x86/isa.hh"
33 #include "arch/x86/decoder.hh"
34 #include "arch/x86/tlb.hh"
35 #include "cpu/base.hh"
36 #include "cpu/thread_context.hh"
37 #include "params/X86ISA.hh"
38 #include "sim/serialize.hh"
44 ISA::updateHandyM5Reg(Efer efer
, CR0 cr0
,
45 SegAttr csAttr
, SegAttr ssAttr
, RFLAGS rflags
,
50 m5reg
.mode
= LongMode
;
52 m5reg
.submode
= SixtyFourBitMode
;
54 m5reg
.submode
= CompatabilityMode
;
56 m5reg
.mode
= LegacyMode
;
59 m5reg
.submode
= Virtual8086Mode
;
61 m5reg
.submode
= ProtectedMode
;
63 m5reg
.submode
= RealMode
;
66 m5reg
.cpl
= csAttr
.dpl
;
67 m5reg
.paging
= cr0
.pg
;
70 // Compute the default and alternate operand size.
71 if (m5reg
.submode
== SixtyFourBitMode
|| csAttr
.defaultSize
) {
79 // Compute the default and alternate address size.
80 if (m5reg
.submode
== SixtyFourBitMode
) {
83 } else if (csAttr
.defaultSize
) {
91 // Compute the stack size
92 if (m5reg
.submode
== SixtyFourBitMode
) {
94 } else if (ssAttr
.defaultSize
) {
100 regVal
[MISCREG_M5_REG
] = m5reg
;
102 tc
->getDecoderPtr()->setM5Reg(m5reg
);
108 // Blank everything. 0 might not be an appropriate value for some things,
109 // but it is for most.
110 memset(regVal
, 0, NumMiscRegs
* sizeof(MiscReg
));
111 regVal
[MISCREG_DR6
] = (mask(8) << 4) | (mask(16) << 16);
112 regVal
[MISCREG_DR7
] = 1 << 10;
124 return dynamic_cast<const Params
*>(_params
);
128 ISA::readMiscRegNoEffect(int miscReg
) const
130 // Make sure we're not dealing with an illegal control register.
131 // Instructions should filter out these indexes, and nothing else should
132 // attempt to read them directly.
133 assert(isValidMiscReg(miscReg
));
135 return regVal
[miscReg
];
139 ISA::readMiscReg(int miscReg
, ThreadContext
* tc
)
141 if (miscReg
== MISCREG_TSC
) {
142 return regVal
[MISCREG_TSC
] + tc
->getCpuPtr()->curCycle();
145 if (miscReg
== MISCREG_FSW
) {
146 MiscReg fsw
= regVal
[MISCREG_FSW
];
147 MiscReg top
= regVal
[MISCREG_X87_TOP
];
148 return (fsw
& (~(7ULL << 11))) + (top
<< 11);
151 return readMiscRegNoEffect(miscReg
);
155 ISA::setMiscRegNoEffect(int miscReg
, MiscReg val
)
157 // Make sure we're not dealing with an illegal control register.
158 // Instructions should filter out these indexes, and nothing else should
159 // attempt to write to them directly.
160 assert(isValidMiscReg(miscReg
));
162 HandyM5Reg m5Reg
= readMiscRegNoEffect(MISCREG_M5_REG
);
165 val
&= (1ULL << 16) - 1;
166 regVal
[miscReg
] = val
;
167 miscReg
= MISCREG_X87_TOP
;
169 case MISCREG_X87_TOP
:
170 val
&= (1ULL << 3) - 1;
173 val
&= (1ULL << 8) - 1;
177 val
&= (1ULL << 16) - 1;
180 val
&= (1ULL << 32) - 1;
184 if (m5Reg
.submode
!= SixtyFourBitMode
)
185 val
&= (1ULL << 16) - 1;
189 if (m5Reg
.submode
!= SixtyFourBitMode
)
190 val
&= (1ULL << 32) - 1;
196 regVal
[miscReg
] = val
;
200 ISA::setMiscReg(int miscReg
, MiscReg val
, ThreadContext
* tc
)
202 MiscReg newVal
= val
;
207 CR0 toggled
= regVal
[miscReg
] ^ val
;
209 Efer efer
= regVal
[MISCREG_EFER
];
210 if (toggled
.pg
&& efer
.lme
) {
212 //Turning on long mode
214 regVal
[MISCREG_EFER
] = efer
;
216 //Turning off long mode
218 regVal
[MISCREG_EFER
] = efer
;
222 tc
->getITBPtr()->flushAll();
223 tc
->getDTBPtr()->flushAll();
225 //This must always be 1.
228 updateHandyM5Reg(regVal
[MISCREG_EFER
],
230 regVal
[MISCREG_CS_ATTR
],
231 regVal
[MISCREG_SS_ATTR
],
232 regVal
[MISCREG_RFLAGS
],
239 tc
->getITBPtr()->flushNonGlobal();
240 tc
->getDTBPtr()->flushNonGlobal();
244 CR4 toggled
= regVal
[miscReg
] ^ val
;
245 if (toggled
.pae
|| toggled
.pse
|| toggled
.pge
) {
246 tc
->getITBPtr()->flushAll();
247 tc
->getDTBPtr()->flushAll();
253 case MISCREG_CS_ATTR
:
255 SegAttr toggled
= regVal
[miscReg
] ^ val
;
256 SegAttr newCSAttr
= val
;
257 if (toggled
.longMode
) {
258 if (newCSAttr
.longMode
) {
259 regVal
[MISCREG_ES_EFF_BASE
] = 0;
260 regVal
[MISCREG_CS_EFF_BASE
] = 0;
261 regVal
[MISCREG_SS_EFF_BASE
] = 0;
262 regVal
[MISCREG_DS_EFF_BASE
] = 0;
264 regVal
[MISCREG_ES_EFF_BASE
] = regVal
[MISCREG_ES_BASE
];
265 regVal
[MISCREG_CS_EFF_BASE
] = regVal
[MISCREG_CS_BASE
];
266 regVal
[MISCREG_SS_EFF_BASE
] = regVal
[MISCREG_SS_BASE
];
267 regVal
[MISCREG_DS_EFF_BASE
] = regVal
[MISCREG_DS_BASE
];
270 updateHandyM5Reg(regVal
[MISCREG_EFER
],
273 regVal
[MISCREG_SS_ATTR
],
274 regVal
[MISCREG_RFLAGS
],
278 case MISCREG_SS_ATTR
:
279 updateHandyM5Reg(regVal
[MISCREG_EFER
],
281 regVal
[MISCREG_CS_ATTR
],
283 regVal
[MISCREG_RFLAGS
],
286 // These segments always actually use their bases, or in other words
287 // their effective bases must stay equal to their actual bases.
288 case MISCREG_FS_BASE
:
289 case MISCREG_GS_BASE
:
290 case MISCREG_HS_BASE
:
291 case MISCREG_TSL_BASE
:
292 case MISCREG_TSG_BASE
:
293 case MISCREG_TR_BASE
:
294 case MISCREG_IDTR_BASE
:
295 regVal
[MISCREG_SEG_EFF_BASE(miscReg
- MISCREG_SEG_BASE_BASE
)] = val
;
297 // These segments ignore their bases in 64 bit mode.
298 // their effective bases must stay equal to their actual bases.
299 case MISCREG_ES_BASE
:
300 case MISCREG_CS_BASE
:
301 case MISCREG_SS_BASE
:
302 case MISCREG_DS_BASE
:
304 Efer efer
= regVal
[MISCREG_EFER
];
305 SegAttr csAttr
= regVal
[MISCREG_CS_ATTR
];
306 if (!efer
.lma
|| !csAttr
.longMode
) // Check for non 64 bit mode.
307 regVal
[MISCREG_SEG_EFF_BASE(miscReg
-
308 MISCREG_SEG_BASE_BASE
)] = val
;
312 regVal
[MISCREG_TSC
] = val
- tc
->getCpuPtr()->curCycle();
318 /* These should eventually set up breakpoints. */
321 miscReg
= MISCREG_DR6
;
322 /* Fall through to have the same effects as DR6. */
325 DR6 dr6
= regVal
[MISCREG_DR6
];
338 miscReg
= MISCREG_DR7
;
339 /* Fall through to have the same effects as DR7. */
342 DR7 dr7
= regVal
[MISCREG_DR7
];
346 if (dr7
.l0
|| dr7
.g0
) {
347 panic("Debug register breakpoints not implemented.\n");
349 /* Disable breakpoint 0. */
353 if (dr7
.l1
|| dr7
.g1
) {
354 panic("Debug register breakpoints not implemented.\n");
356 /* Disable breakpoint 1. */
360 if (dr7
.l2
|| dr7
.g2
) {
361 panic("Debug register breakpoints not implemented.\n");
363 /* Disable breakpoint 2. */
367 if (dr7
.l3
|| dr7
.g3
) {
368 panic("Debug register breakpoints not implemented.\n");
370 /* Disable breakpoint 3. */
373 dr7
.rw0
= newDR7
.rw0
;
374 dr7
.len0
= newDR7
.len0
;
375 dr7
.rw1
= newDR7
.rw1
;
376 dr7
.len1
= newDR7
.len1
;
377 dr7
.rw2
= newDR7
.rw2
;
378 dr7
.len2
= newDR7
.len2
;
379 dr7
.rw3
= newDR7
.rw3
;
380 dr7
.len3
= newDR7
.len3
;
384 // Writing anything to the m5reg with side effects makes it update
385 // based on the current values of the relevant registers. The actual
386 // value written is discarded.
387 updateHandyM5Reg(regVal
[MISCREG_EFER
],
389 regVal
[MISCREG_CS_ATTR
],
390 regVal
[MISCREG_SS_ATTR
],
391 regVal
[MISCREG_RFLAGS
],
397 setMiscRegNoEffect(miscReg
, newVal
);
401 ISA::serialize(CheckpointOut
&cp
) const
403 SERIALIZE_ARRAY(regVal
, NumMiscRegs
);
407 ISA::unserialize(CheckpointIn
&cp
)
409 UNSERIALIZE_ARRAY(regVal
, NumMiscRegs
);
410 updateHandyM5Reg(regVal
[MISCREG_EFER
],
412 regVal
[MISCREG_CS_ATTR
],
413 regVal
[MISCREG_SS_ATTR
],
414 regVal
[MISCREG_RFLAGS
],
419 ISA::startup(ThreadContext
*tc
)
421 tc
->getDecoderPtr()->setM5Reg(regVal
[MISCREG_M5_REG
]);
427 X86ISAParams::create()
429 return new X86ISA::ISA(this);