2 * Copyright (c) 2009 The Regents of The University of Michigan
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31 #include "arch/x86/decoder.hh"
32 #include "arch/x86/isa.hh"
33 #include "arch/x86/tlb.hh"
34 #include "cpu/base.hh"
35 #include "cpu/thread_context.hh"
36 #include "params/X86ISA.hh"
37 #include "sim/serialize.hh"
43 ISA::updateHandyM5Reg(Efer efer
, CR0 cr0
,
44 SegAttr csAttr
, SegAttr ssAttr
, RFLAGS rflags
,
49 m5reg
.mode
= LongMode
;
51 m5reg
.submode
= SixtyFourBitMode
;
53 m5reg
.submode
= CompatabilityMode
;
55 m5reg
.mode
= LegacyMode
;
58 m5reg
.submode
= Virtual8086Mode
;
60 m5reg
.submode
= ProtectedMode
;
62 m5reg
.submode
= RealMode
;
65 m5reg
.cpl
= csAttr
.dpl
;
66 m5reg
.paging
= cr0
.pg
;
69 // Compute the default and alternate operand size.
70 if (m5reg
.submode
== SixtyFourBitMode
|| csAttr
.defaultSize
) {
78 // Compute the default and alternate address size.
79 if (m5reg
.submode
== SixtyFourBitMode
) {
82 } else if (csAttr
.defaultSize
) {
90 // Compute the stack size
91 if (m5reg
.submode
== SixtyFourBitMode
) {
93 } else if (ssAttr
.defaultSize
) {
99 regVal
[MISCREG_M5_REG
] = m5reg
;
101 tc
->getDecoderPtr()->setM5Reg(m5reg
);
107 // Blank everything. 0 might not be an appropriate value for some things,
108 // but it is for most.
109 memset(regVal
, 0, NumMiscRegs
* sizeof(MiscReg
));
110 regVal
[MISCREG_DR6
] = (mask(8) << 4) | (mask(16) << 16);
111 regVal
[MISCREG_DR7
] = 1 << 10;
123 return dynamic_cast<const Params
*>(_params
);
127 ISA::readMiscRegNoEffect(int miscReg
)
129 // Make sure we're not dealing with an illegal control register.
130 // Instructions should filter out these indexes, and nothing else should
131 // attempt to read them directly.
132 assert( miscReg
!= MISCREG_CR1
&&
133 !(miscReg
> MISCREG_CR4
&&
134 miscReg
< MISCREG_CR8
) &&
135 !(miscReg
> MISCREG_CR8
&&
136 miscReg
<= MISCREG_CR15
));
138 return regVal
[miscReg
];
142 ISA::readMiscReg(int miscReg
, ThreadContext
* tc
)
144 if (miscReg
== MISCREG_TSC
) {
145 return regVal
[MISCREG_TSC
] + tc
->getCpuPtr()->curCycle();
148 if (miscReg
== MISCREG_FSW
) {
149 MiscReg fsw
= regVal
[MISCREG_FSW
];
150 MiscReg top
= regVal
[MISCREG_X87_TOP
];
151 return (fsw
& (~(7ULL << 11))) + (top
<< 11);
154 return readMiscRegNoEffect(miscReg
);
158 ISA::setMiscRegNoEffect(int miscReg
, MiscReg val
)
160 // Make sure we're not dealing with an illegal control register.
161 // Instructions should filter out these indexes, and nothing else should
162 // attempt to write to them directly.
163 assert( miscReg
!= MISCREG_CR1
&&
164 !(miscReg
> MISCREG_CR4
&&
165 miscReg
< MISCREG_CR8
) &&
166 !(miscReg
> MISCREG_CR8
&&
167 miscReg
<= MISCREG_CR15
));
168 regVal
[miscReg
] = val
;
172 ISA::setMiscReg(int miscReg
, MiscReg val
, ThreadContext
* tc
)
174 MiscReg newVal
= val
;
179 CR0 toggled
= regVal
[miscReg
] ^ val
;
181 Efer efer
= regVal
[MISCREG_EFER
];
182 if (toggled
.pg
&& efer
.lme
) {
184 //Turning on long mode
186 regVal
[MISCREG_EFER
] = efer
;
188 //Turning off long mode
190 regVal
[MISCREG_EFER
] = efer
;
194 tc
->getITBPtr()->flushAll();
195 tc
->getDTBPtr()->flushAll();
197 //This must always be 1.
200 updateHandyM5Reg(regVal
[MISCREG_EFER
],
202 regVal
[MISCREG_CS_ATTR
],
203 regVal
[MISCREG_SS_ATTR
],
204 regVal
[MISCREG_RFLAGS
],
211 tc
->getITBPtr()->flushNonGlobal();
212 tc
->getDTBPtr()->flushNonGlobal();
216 CR4 toggled
= regVal
[miscReg
] ^ val
;
217 if (toggled
.pae
|| toggled
.pse
|| toggled
.pge
) {
218 tc
->getITBPtr()->flushAll();
219 tc
->getDTBPtr()->flushAll();
225 case MISCREG_CS_ATTR
:
227 SegAttr toggled
= regVal
[miscReg
] ^ val
;
228 SegAttr newCSAttr
= val
;
229 if (toggled
.longMode
) {
230 if (newCSAttr
.longMode
) {
231 regVal
[MISCREG_ES_EFF_BASE
] = 0;
232 regVal
[MISCREG_CS_EFF_BASE
] = 0;
233 regVal
[MISCREG_SS_EFF_BASE
] = 0;
234 regVal
[MISCREG_DS_EFF_BASE
] = 0;
236 regVal
[MISCREG_ES_EFF_BASE
] = regVal
[MISCREG_ES_BASE
];
237 regVal
[MISCREG_CS_EFF_BASE
] = regVal
[MISCREG_CS_BASE
];
238 regVal
[MISCREG_SS_EFF_BASE
] = regVal
[MISCREG_SS_BASE
];
239 regVal
[MISCREG_DS_EFF_BASE
] = regVal
[MISCREG_DS_BASE
];
242 updateHandyM5Reg(regVal
[MISCREG_EFER
],
245 regVal
[MISCREG_SS_ATTR
],
246 regVal
[MISCREG_RFLAGS
],
250 case MISCREG_SS_ATTR
:
251 updateHandyM5Reg(regVal
[MISCREG_EFER
],
253 regVal
[MISCREG_CS_ATTR
],
255 regVal
[MISCREG_RFLAGS
],
258 // These segments always actually use their bases, or in other words
259 // their effective bases must stay equal to their actual bases.
260 case MISCREG_FS_BASE
:
261 case MISCREG_GS_BASE
:
262 case MISCREG_HS_BASE
:
263 case MISCREG_TSL_BASE
:
264 case MISCREG_TSG_BASE
:
265 case MISCREG_TR_BASE
:
266 case MISCREG_IDTR_BASE
:
267 regVal
[MISCREG_SEG_EFF_BASE(miscReg
- MISCREG_SEG_BASE_BASE
)] = val
;
269 // These segments ignore their bases in 64 bit mode.
270 // their effective bases must stay equal to their actual bases.
271 case MISCREG_ES_BASE
:
272 case MISCREG_CS_BASE
:
273 case MISCREG_SS_BASE
:
274 case MISCREG_DS_BASE
:
276 Efer efer
= regVal
[MISCREG_EFER
];
277 SegAttr csAttr
= regVal
[MISCREG_CS_ATTR
];
278 if (!efer
.lma
|| !csAttr
.longMode
) // Check for non 64 bit mode.
279 regVal
[MISCREG_SEG_EFF_BASE(miscReg
-
280 MISCREG_SEG_BASE_BASE
)] = val
;
284 regVal
[MISCREG_TSC
] = val
- tc
->getCpuPtr()->curCycle();
290 /* These should eventually set up breakpoints. */
293 miscReg
= MISCREG_DR6
;
294 /* Fall through to have the same effects as DR6. */
297 DR6 dr6
= regVal
[MISCREG_DR6
];
310 miscReg
= MISCREG_DR7
;
311 /* Fall through to have the same effects as DR7. */
314 DR7 dr7
= regVal
[MISCREG_DR7
];
318 if (dr7
.l0
|| dr7
.g0
) {
319 panic("Debug register breakpoints not implemented.\n");
321 /* Disable breakpoint 0. */
325 if (dr7
.l1
|| dr7
.g1
) {
326 panic("Debug register breakpoints not implemented.\n");
328 /* Disable breakpoint 1. */
332 if (dr7
.l2
|| dr7
.g2
) {
333 panic("Debug register breakpoints not implemented.\n");
335 /* Disable breakpoint 2. */
339 if (dr7
.l3
|| dr7
.g3
) {
340 panic("Debug register breakpoints not implemented.\n");
342 /* Disable breakpoint 3. */
345 dr7
.rw0
= newDR7
.rw0
;
346 dr7
.len0
= newDR7
.len0
;
347 dr7
.rw1
= newDR7
.rw1
;
348 dr7
.len1
= newDR7
.len1
;
349 dr7
.rw2
= newDR7
.rw2
;
350 dr7
.len2
= newDR7
.len2
;
351 dr7
.rw3
= newDR7
.rw3
;
352 dr7
.len3
= newDR7
.len3
;
356 // Writing anything to the m5reg with side effects makes it update
357 // based on the current values of the relevant registers. The actual
358 // value written is discarded.
359 updateHandyM5Reg(regVal
[MISCREG_EFER
],
361 regVal
[MISCREG_CS_ATTR
],
362 regVal
[MISCREG_SS_ATTR
],
363 regVal
[MISCREG_RFLAGS
],
369 setMiscRegNoEffect(miscReg
, newVal
);
373 ISA::serialize(EventManager
*em
, std::ostream
& os
)
375 SERIALIZE_ARRAY(regVal
, NumMiscRegs
);
379 ISA::unserialize(EventManager
*em
, Checkpoint
* cp
,
380 const std::string
& section
)
382 UNSERIALIZE_ARRAY(regVal
, NumMiscRegs
);
383 updateHandyM5Reg(regVal
[MISCREG_EFER
],
385 regVal
[MISCREG_CS_ATTR
],
386 regVal
[MISCREG_SS_ATTR
],
387 regVal
[MISCREG_RFLAGS
],
394 X86ISAParams::create()
396 return new X86ISA::ISA(this);