2 * Copyright (c) 2009 The Regents of The University of Michigan
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31 #include "arch/x86/floatregs.hh"
32 #include "arch/x86/isa.hh"
33 #include "arch/x86/tlb.hh"
34 #include "cpu/base.hh"
35 #include "cpu/thread_context.hh"
36 #include "sim/serialize.hh"
42 ISA::updateHandyM5Reg(Efer efer
, CR0 cr0
,
43 SegAttr csAttr
, SegAttr ssAttr
, RFLAGS rflags
)
47 m5reg
.mode
= LongMode
;
49 m5reg
.submode
= SixtyFourBitMode
;
51 m5reg
.submode
= CompatabilityMode
;
53 m5reg
.mode
= LegacyMode
;
56 m5reg
.submode
= Virtual8086Mode
;
58 m5reg
.submode
= ProtectedMode
;
60 m5reg
.submode
= RealMode
;
63 m5reg
.cpl
= csAttr
.dpl
;
64 m5reg
.paging
= cr0
.pg
;
67 // Compute the default and alternate operand size.
68 if (m5reg
.submode
== SixtyFourBitMode
|| csAttr
.defaultSize
) {
76 // Compute the default and alternate address size.
77 if (m5reg
.submode
== SixtyFourBitMode
) {
80 } else if (csAttr
.defaultSize
) {
88 // Compute the stack size
89 if (m5reg
.submode
== SixtyFourBitMode
) {
91 } else if (ssAttr
.defaultSize
) {
97 regVal
[MISCREG_M5_REG
] = m5reg
;
103 // Blank everything. 0 might not be an appropriate value for some things,
104 // but it is for most.
105 memset(regVal
, 0, NumMiscRegs
* sizeof(MiscReg
));
106 regVal
[MISCREG_DR6
] = (mask(8) << 4) | (mask(16) << 16);
107 regVal
[MISCREG_DR7
] = 1 << 10;
111 ISA::readMiscRegNoEffect(int miscReg
)
113 // Make sure we're not dealing with an illegal control register.
114 // Instructions should filter out these indexes, and nothing else should
115 // attempt to read them directly.
116 assert( miscReg
!= MISCREG_CR1
&&
117 !(miscReg
> MISCREG_CR4
&&
118 miscReg
< MISCREG_CR8
) &&
119 !(miscReg
> MISCREG_CR8
&&
120 miscReg
<= MISCREG_CR15
));
122 return regVal
[miscReg
];
126 ISA::readMiscReg(int miscReg
, ThreadContext
* tc
)
128 if (miscReg
== MISCREG_TSC
) {
129 return regVal
[MISCREG_TSC
] + tc
->getCpuPtr()->curCycle();
131 return readMiscRegNoEffect(miscReg
);
135 ISA::setMiscRegNoEffect(int miscReg
, MiscReg val
)
137 // Make sure we're not dealing with an illegal control register.
138 // Instructions should filter out these indexes, and nothing else should
139 // attempt to write to them directly.
140 assert( miscReg
!= MISCREG_CR1
&&
141 !(miscReg
> MISCREG_CR4
&&
142 miscReg
< MISCREG_CR8
) &&
143 !(miscReg
> MISCREG_CR8
&&
144 miscReg
<= MISCREG_CR15
));
145 regVal
[miscReg
] = val
;
149 ISA::setMiscReg(int miscReg
, MiscReg val
, ThreadContext
* tc
)
151 MiscReg newVal
= val
;
156 CR0 toggled
= regVal
[miscReg
] ^ val
;
158 Efer efer
= regVal
[MISCREG_EFER
];
159 if (toggled
.pg
&& efer
.lme
) {
161 //Turning on long mode
163 regVal
[MISCREG_EFER
] = efer
;
165 //Turning off long mode
167 regVal
[MISCREG_EFER
] = efer
;
171 tc
->getITBPtr()->invalidateAll();
172 tc
->getDTBPtr()->invalidateAll();
174 //This must always be 1.
177 updateHandyM5Reg(regVal
[MISCREG_EFER
],
179 regVal
[MISCREG_CS_ATTR
],
180 regVal
[MISCREG_SS_ATTR
],
181 regVal
[MISCREG_RFLAGS
]);
187 tc
->getITBPtr()->invalidateNonGlobal();
188 tc
->getDTBPtr()->invalidateNonGlobal();
192 CR4 toggled
= regVal
[miscReg
] ^ val
;
193 if (toggled
.pae
|| toggled
.pse
|| toggled
.pge
) {
194 tc
->getITBPtr()->invalidateAll();
195 tc
->getDTBPtr()->invalidateAll();
201 case MISCREG_CS_ATTR
:
203 SegAttr toggled
= regVal
[miscReg
] ^ val
;
204 SegAttr newCSAttr
= val
;
205 if (toggled
.longMode
) {
206 if (newCSAttr
.longMode
) {
207 regVal
[MISCREG_ES_EFF_BASE
] = 0;
208 regVal
[MISCREG_CS_EFF_BASE
] = 0;
209 regVal
[MISCREG_SS_EFF_BASE
] = 0;
210 regVal
[MISCREG_DS_EFF_BASE
] = 0;
212 regVal
[MISCREG_ES_EFF_BASE
] = regVal
[MISCREG_ES_BASE
];
213 regVal
[MISCREG_CS_EFF_BASE
] = regVal
[MISCREG_CS_BASE
];
214 regVal
[MISCREG_SS_EFF_BASE
] = regVal
[MISCREG_SS_BASE
];
215 regVal
[MISCREG_DS_EFF_BASE
] = regVal
[MISCREG_DS_BASE
];
218 updateHandyM5Reg(regVal
[MISCREG_EFER
],
221 regVal
[MISCREG_SS_ATTR
],
222 regVal
[MISCREG_RFLAGS
]);
225 case MISCREG_SS_ATTR
:
226 updateHandyM5Reg(regVal
[MISCREG_EFER
],
228 regVal
[MISCREG_CS_ATTR
],
230 regVal
[MISCREG_RFLAGS
]);
232 // These segments always actually use their bases, or in other words
233 // their effective bases must stay equal to their actual bases.
234 case MISCREG_FS_BASE
:
235 case MISCREG_GS_BASE
:
236 case MISCREG_HS_BASE
:
237 case MISCREG_TSL_BASE
:
238 case MISCREG_TSG_BASE
:
239 case MISCREG_TR_BASE
:
240 case MISCREG_IDTR_BASE
:
241 regVal
[MISCREG_SEG_EFF_BASE(miscReg
- MISCREG_SEG_BASE_BASE
)] = val
;
243 // These segments ignore their bases in 64 bit mode.
244 // their effective bases must stay equal to their actual bases.
245 case MISCREG_ES_BASE
:
246 case MISCREG_CS_BASE
:
247 case MISCREG_SS_BASE
:
248 case MISCREG_DS_BASE
:
250 Efer efer
= regVal
[MISCREG_EFER
];
251 SegAttr csAttr
= regVal
[MISCREG_CS_ATTR
];
252 if (!efer
.lma
|| !csAttr
.longMode
) // Check for non 64 bit mode.
253 regVal
[MISCREG_SEG_EFF_BASE(miscReg
-
254 MISCREG_SEG_BASE_BASE
)] = val
;
258 regVal
[MISCREG_TSC
] = val
- tc
->getCpuPtr()->curCycle();
264 /* These should eventually set up breakpoints. */
267 miscReg
= MISCREG_DR6
;
268 /* Fall through to have the same effects as DR6. */
271 DR6 dr6
= regVal
[MISCREG_DR6
];
284 miscReg
= MISCREG_DR7
;
285 /* Fall through to have the same effects as DR7. */
288 DR7 dr7
= regVal
[MISCREG_DR7
];
292 if (dr7
.l0
|| dr7
.g0
) {
293 panic("Debug register breakpoints not implemented.\n");
295 /* Disable breakpoint 0. */
299 if (dr7
.l1
|| dr7
.g1
) {
300 panic("Debug register breakpoints not implemented.\n");
302 /* Disable breakpoint 1. */
306 if (dr7
.l2
|| dr7
.g2
) {
307 panic("Debug register breakpoints not implemented.\n");
309 /* Disable breakpoint 2. */
313 if (dr7
.l3
|| dr7
.g3
) {
314 panic("Debug register breakpoints not implemented.\n");
316 /* Disable breakpoint 3. */
319 dr7
.rw0
= newDR7
.rw0
;
320 dr7
.len0
= newDR7
.len0
;
321 dr7
.rw1
= newDR7
.rw1
;
322 dr7
.len1
= newDR7
.len1
;
323 dr7
.rw2
= newDR7
.rw2
;
324 dr7
.len2
= newDR7
.len2
;
325 dr7
.rw3
= newDR7
.rw3
;
326 dr7
.len3
= newDR7
.len3
;
330 // Writing anything to the m5reg with side effects makes it update
331 // based on the current values of the relevant registers. The actual
332 // value written is discarded.
333 updateHandyM5Reg(regVal
[MISCREG_EFER
],
335 regVal
[MISCREG_CS_ATTR
],
336 regVal
[MISCREG_SS_ATTR
],
337 regVal
[MISCREG_RFLAGS
]);
342 setMiscRegNoEffect(miscReg
, newVal
);
346 ISA::serialize(EventManager
*em
, std::ostream
& os
)
348 SERIALIZE_ARRAY(regVal
, NumMiscRegs
);
352 ISA::unserialize(EventManager
*em
, Checkpoint
* cp
,
353 const std::string
& section
)
355 UNSERIALIZE_ARRAY(regVal
, NumMiscRegs
);
359 ISA::flattenIntIndex(int reg
)
361 //If we need to fold over the index to match byte semantics, do that.
362 //Otherwise, just strip off any extra bits and pass it through.
364 return (reg
& (~(1 << 6) - 0x4));
366 return (reg
& ~(1 << 6));
370 ISA::flattenFloatIndex(int reg
)
372 if (reg
>= NUM_FLOATREGS
) {
373 int top
= readMiscRegNoEffect(MISCREG_X87_TOP
);
374 reg
= FLOATREG_STACK(reg
- NUM_FLOATREGS
, top
);