src/arch/x86/isa.hh

   1 /*
   2  * Copyright (c) 2009 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_X86_ISA_HH__
  32 #define __ARCH_X86_ISA_HH__
  33
  34 #include <iostream>
  35 #include <string>
  36
  37 #include "arch/x86/regs/float.hh"
  38 #include "arch/x86/regs/misc.hh"
  39 #include "arch/x86/registers.hh"
  40 #include "base/types.hh"
  41 #include "cpu/reg_class.hh"
  42 #include "sim/sim_object.hh"
  43
  44 class Checkpoint;
  45 class EventManager;
  46 class ThreadContext;
  47 struct X86ISAParams;
  48
  49 namespace X86ISA
  50 {
  51     class ISA : public SimObject
  52     {
  53       protected:
  54         MiscReg regVal[NUM_MISCREGS];
  55         void updateHandyM5Reg(Efer efer, CR0 cr0,
  56                 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
  57                 ThreadContext *tc);
  58
  59       public:
  60         typedef X86ISAParams Params;
  61
  62         void clear();
  63
  64         ISA(Params *p);
  65         const Params *params() const;
  66
  67         MiscReg readMiscRegNoEffect(int miscReg) const;
  68         MiscReg readMiscReg(int miscReg, ThreadContext *tc);
  69
  70         void setMiscRegNoEffect(int miscReg, MiscReg val);
  71         void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
  72
  73         RegId
  74         flattenRegId(const RegId& regId) const
  75         {
  76             switch (regId.classValue()) {
  77               case IntRegClass:
  78                 return RegId(IntRegClass, flattenIntIndex(regId.index()));
  79               case FloatRegClass:
  80                 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
  81               case CCRegClass:
  82                 return RegId(CCRegClass, flattenCCIndex(regId.index()));
  83               case MiscRegClass:
  84                 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
  85             }
  86             return regId;
  87         }
  88
  89         int
  90         flattenIntIndex(int reg) const
  91         {
  92             return reg & ~IntFoldBit;
  93         }
  94
  95         int
  96         flattenFloatIndex(int reg) const
  97         {
  98             if (reg >= NUM_FLOATREGS) {
  99                 reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
 100                                      regVal[MISCREG_X87_TOP]);
 101             }
 102             return reg;
 103         }
 104
 105         int
 106         flattenCCIndex(int reg) const
 107         {
 108             return reg;
 109         }
 110
 111         int
 112         flattenMiscIndex(int reg) const
 113         {
 114             return reg;
 115         }
 116
 117         void serialize(CheckpointOut &cp) const override;
 118         void unserialize(CheckpointIn &cp) override;
 119
 120         void startup(ThreadContext *tc);
 121
 122         /// Explicitly import the otherwise hidden startup
 123         using SimObject::startup;
 124
 125     };
 126 }
 127
 128 #endif