src/arch/x86/isa.hh

   1 /*
   2  * Copyright (c) 2009 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_X86_ISA_HH__
  30 #define __ARCH_X86_ISA_HH__
  31
  32 #include <iostream>
  33 #include <string>
  34
  35 #include "arch/generic/isa.hh"
  36 #include "arch/x86/registers.hh"
  37 #include "arch/x86/regs/float.hh"
  38 #include "arch/x86/regs/misc.hh"
  39 #include "base/types.hh"
  40 #include "cpu/reg_class.hh"
  41 #include "sim/sim_object.hh"
  42
  43 class Checkpoint;
  44 class EventManager;
  45 class ThreadContext;
  46 struct X86ISAParams;
  47
  48 namespace X86ISA
  49 {
  50     class ISA : public BaseISA
  51     {
  52       protected:
  53         RegVal regVal[NUM_MISCREGS];
  54         void updateHandyM5Reg(Efer efer, CR0 cr0,
  55                 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags,
  56                 ThreadContext *tc);
  57         void clear();
  58
  59       public:
  60         typedef X86ISAParams Params;
  61
  62         void clear(ThreadContext *tc) { clear(); }
  63
  64         ISA(Params *p);
  65         const Params *params() const;
  66
  67         RegVal readMiscRegNoEffect(int miscReg) const;
  68         RegVal readMiscReg(int miscReg, ThreadContext *tc);
  69
  70         void setMiscRegNoEffect(int miscReg, RegVal val);
  71         void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
  72
  73         RegId
  74         flattenRegId(const RegId& regId) const
  75         {
  76             switch (regId.classValue()) {
  77               case IntRegClass:
  78                 return RegId(IntRegClass, flattenIntIndex(regId.index()));
  79               case FloatRegClass:
  80                 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
  81               case CCRegClass:
  82                 return RegId(CCRegClass, flattenCCIndex(regId.index()));
  83               case MiscRegClass:
  84                 return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
  85               default:
  86                 break;
  87             }
  88             return regId;
  89         }
  90
  91         int
  92         flattenIntIndex(int reg) const
  93         {
  94             return reg & ~IntFoldBit;
  95         }
  96
  97         int
  98         flattenFloatIndex(int reg) const
  99         {
 100             if (reg >= NUM_FLOATREGS) {
 101                 reg = FLOATREG_STACK(reg - NUM_FLOATREGS,
 102                                      regVal[MISCREG_X87_TOP]);
 103             }
 104             return reg;
 105         }
 106
 107         int
 108         flattenVecIndex(int reg) const
 109         {
 110             return reg;
 111         }
 112
 113         int
 114         flattenVecElemIndex(int reg) const
 115         {
 116             return reg;
 117         }
 118
 119         int
 120         flattenVecPredIndex(int reg) const
 121         {
 122             return reg;
 123         }
 124
 125         int
 126         flattenCCIndex(int reg) const
 127         {
 128             return reg;
 129         }
 130
 131         int
 132         flattenMiscIndex(int reg) const
 133         {
 134             return reg;
 135         }
 136
 137         void serialize(CheckpointOut &cp) const override;
 138         void unserialize(CheckpointIn &cp) override;
 139
 140         void startup(ThreadContext *tc);
 141
 142         /// Explicitly import the otherwise hidden startup
 143         using BaseISA::startup;
 144
 145     };
 146 }
 147
 148 #endif