src/arch/x86/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2006, 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 /*
  32  * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
  33  * All rights reserved.
  34  *
  35  * Redistribution and use of this software in source and binary forms,
  36  * with or without modification, are permitted provided that the
  37  * following conditions are met:
  38  *
  39  * The software must be used only for Non-Commercial Use which means any
  40  * use which is NOT directed to receiving any direct monetary
  41  * compensation for, or commercial advantage from such use.  Illustrative
  42  * examples of non-commercial use are academic research, personal study,
  43  * teaching, education and corporate research & development.
  44  * Illustrative examples of commercial use are distributing products for
  45  * commercial advantage and providing services using the software for
  46  * commercial advantage.
  47  *
  48  * If you wish to use this software or functionality therein that may be
  49  * covered by patents for commercial use, please contact:
  50  *     Director of Intellectual Property Licensing
  51  *     Office of Strategy and Technology
  52  *     Hewlett-Packard Company
  53  *     1501 Page Mill Road
  54  *     Palo Alto, California  94304
  55  *
  56  * Redistributions of source code must retain the above copyright notice,
  57  * this list of conditions and the following disclaimer.  Redistributions
  58  * in binary form must reproduce the above copyright notice, this list of
  59  * conditions and the following disclaimer in the documentation and/or
  60  * other materials provided with the distribution.  Neither the name of
  61  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  62  * contributors may be used to endorse or promote products derived from
  63  * this software without specific prior written permission.  No right of
  64  * sublicense is granted herewith.  Derivatives of the software and
  65  * output created using the software may be prepared, but only for
  66  * Non-Commercial Uses.  Derivatives of the software may be shared with
  67  * others provided: (i) the others agree to abide by the list of
  68  * conditions herein which includes the Non-Commercial Use restrictions;
  69  * and (ii) such Derivatives of the software include the above copyright
  70  * notice to acknowledge the contribution from this software where
  71  * applicable, this list of conditions and the disclaimer below.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  74  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  75  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  76  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  77  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  78  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  79  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  80  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  81  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  82  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  83  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  84  *
  85  * Authors: Gabe Black
  86  */
  87
  88 #include "arch/x86/miscregfile.hh"
  89 #include "arch/x86/tlb.hh"
  90 #include "cpu/base.hh"
  91 #include "cpu/thread_context.hh"
  92 #include "sim/serialize.hh"
  93
  94 using namespace X86ISA;
  95 using namespace std;
  96
  97 class Checkpoint;
  98
  99 //These functions map register indices to names
 100 string X86ISA::getMiscRegName(RegIndex index)
 101 {
 102     panic("No misc registers in x86 yet!\n");
 103 }
 104
 105 void MiscRegFile::clear()
 106 {
 107     // Blank everything. 0 might not be an appropriate value for some things.
 108     memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
 109 }
 110
 111 MiscReg MiscRegFile::readRegNoEffect(MiscRegIndex miscReg)
 112 {
 113     // Make sure we're not dealing with an illegal control register.
 114     // Instructions should filter out these indexes, and nothing else should
 115     // attempt to read them directly.
 116     assert( miscReg != MISCREG_CR1 &&
 117             !(miscReg > MISCREG_CR4 &&
 118               miscReg < MISCREG_CR8) &&
 119             !(miscReg > MISCREG_CR8 &&
 120               miscReg <= MISCREG_CR15));
 121
 122     return regVal[miscReg];
 123 }
 124
 125 MiscReg MiscRegFile::readReg(MiscRegIndex miscReg, ThreadContext * tc)
 126 {
 127     if (miscReg == MISCREG_TSC) {
 128         return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
 129     }
 130     return readRegNoEffect(miscReg);
 131 }
 132
 133 void MiscRegFile::setRegNoEffect(MiscRegIndex miscReg, const MiscReg &val)
 134 {
 135     // Make sure we're not dealing with an illegal control register.
 136     // Instructions should filter out these indexes, and nothing else should
 137     // attempt to write to them directly.
 138     assert( miscReg != MISCREG_CR1 &&
 139             !(miscReg > MISCREG_CR4 &&
 140               miscReg < MISCREG_CR8) &&
 141             !(miscReg > MISCREG_CR8 &&
 142               miscReg <= MISCREG_CR15));
 143     regVal[miscReg] = val;
 144 }
 145
 146 void MiscRegFile::setReg(MiscRegIndex miscReg,
 147         const MiscReg &val, ThreadContext * tc)
 148 {
 149     MiscReg newVal = val;
 150     switch(miscReg)
 151     {
 152       case MISCREG_CR0:
 153         {
 154             CR0 toggled = regVal[miscReg] ^ val;
 155             CR0 newCR0 = val;
 156             Efer efer = regVal[MISCREG_EFER];
 157             HandyM5Reg m5reg = regVal[MISCREG_M5_REG];
 158             if (toggled.pg && efer.lme) {
 159                 if (newCR0.pg) {
 160                     //Turning on long mode
 161                     efer.lma = 1;
 162                     m5reg.mode = LongMode;
 163                     regVal[MISCREG_EFER] = efer;
 164                 } else {
 165                     //Turning off long mode
 166                     efer.lma = 0;
 167                     m5reg.mode = LegacyMode;
 168                     regVal[MISCREG_EFER] = efer;
 169                 }
 170             }
 171             // Figure out what submode we're in.
 172             if (m5reg.mode == LongMode) {
 173                 SegAttr csAttr = regVal[MISCREG_CS_ATTR];
 174                 if (csAttr.longMode)
 175                     m5reg.submode = SixtyFourBitMode;
 176                 else
 177                     m5reg.submode = CompatabilityMode;
 178             } else {
 179                 if (newCR0.pe) {
 180                     RFLAGS rflags = regVal[MISCREG_RFLAGS];
 181                     if (rflags.vm)
 182                         m5reg.submode = Virtual8086Mode;
 183                     else
 184                         m5reg.submode = ProtectedMode;
 185                 } else {
 186                     m5reg.submode = RealMode;
 187                 }
 188             }
 189             regVal[MISCREG_M5_REG] = m5reg;
 190             if (toggled.pg) {
 191                 tc->getITBPtr()->invalidateAll();
 192                 tc->getDTBPtr()->invalidateAll();
 193             }
 194             //This must always be 1.
 195             newCR0.et = 1;
 196             newVal = newCR0;
 197         }
 198         break;
 199       case MISCREG_CR2:
 200         break;
 201       case MISCREG_CR3:
 202         tc->getITBPtr()->invalidateNonGlobal();
 203         tc->getDTBPtr()->invalidateNonGlobal();
 204         break;
 205       case MISCREG_CR4:
 206         {
 207             CR4 toggled = regVal[miscReg] ^ val;
 208             if (toggled.pae || toggled.pse || toggled.pge) {
 209                 tc->getITBPtr()->invalidateAll();
 210                 tc->getDTBPtr()->invalidateAll();
 211             }
 212         }
 213         break;
 214       case MISCREG_CR8:
 215         break;
 216       case MISCREG_CS_ATTR:
 217         {
 218             SegAttr toggled = regVal[miscReg] ^ val;
 219             SegAttr newCSAttr = val;
 220             HandyM5Reg m5reg = regVal[MISCREG_M5_REG];
 221             if (toggled.longMode) {
 222                 if (newCSAttr.longMode) {
 223                     if (m5reg.mode == LongMode)
 224                         m5reg.submode = SixtyFourBitMode;
 225                     regVal[MISCREG_ES_EFF_BASE] = 0;
 226                     regVal[MISCREG_CS_EFF_BASE] = 0;
 227                     regVal[MISCREG_SS_EFF_BASE] = 0;
 228                     regVal[MISCREG_DS_EFF_BASE] = 0;
 229                 } else {
 230                     if (m5reg.mode == LongMode)
 231                         m5reg.submode = CompatabilityMode;
 232                     regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
 233                     regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
 234                     regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
 235                     regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
 236                 }
 237             }
 238             m5reg.cpl = newCSAttr.dpl;
 239             regVal[MISCREG_M5_REG] = m5reg;
 240         }
 241         break;
 242       // These segments always actually use their bases, or in other words
 243       // their effective bases must stay equal to their actual bases.
 244       case MISCREG_FS_BASE:
 245       case MISCREG_GS_BASE:
 246       case MISCREG_HS_BASE:
 247       case MISCREG_TSL_BASE:
 248       case MISCREG_TSG_BASE:
 249       case MISCREG_TR_BASE:
 250       case MISCREG_IDTR_BASE:
 251         regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
 252         break;
 253       // These segments ignore their bases in 64 bit mode.
 254       // their effective bases must stay equal to their actual bases.
 255       case MISCREG_ES_BASE:
 256       case MISCREG_CS_BASE:
 257       case MISCREG_SS_BASE:
 258       case MISCREG_DS_BASE:
 259         {
 260             Efer efer = regVal[MISCREG_EFER];
 261             SegAttr csAttr = regVal[MISCREG_CS_ATTR];
 262             if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
 263                 regVal[MISCREG_SEG_EFF_BASE(miscReg -
 264                         MISCREG_SEG_BASE_BASE)] = val;
 265         }
 266         break;
 267       case MISCREG_TSC:
 268         regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
 269         return;
 270       default:
 271         break;
 272     }
 273     setRegNoEffect(miscReg, newVal);
 274 }
 275
 276 void MiscRegFile::serialize(std::ostream & os)
 277 {
 278     SERIALIZE_ARRAY(regVal, NumMiscRegs);
 279 }
 280
 281 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 282 {
 283     UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
 284 }