src/arch/x86/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2006, 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 /*
  32  * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
  33  * All rights reserved.
  34  *
  35  * Redistribution and use of this software in source and binary forms,
  36  * with or without modification, are permitted provided that the
  37  * following conditions are met:
  38  *
  39  * The software must be used only for Non-Commercial Use which means any
  40  * use which is NOT directed to receiving any direct monetary
  41  * compensation for, or commercial advantage from such use.  Illustrative
  42  * examples of non-commercial use are academic research, personal study,
  43  * teaching, education and corporate research & development.
  44  * Illustrative examples of commercial use are distributing products for
  45  * commercial advantage and providing services using the software for
  46  * commercial advantage.
  47  *
  48  * If you wish to use this software or functionality therein that may be
  49  * covered by patents for commercial use, please contact:
  50  *     Director of Intellectual Property Licensing
  51  *     Office of Strategy and Technology
  52  *     Hewlett-Packard Company
  53  *     1501 Page Mill Road
  54  *     Palo Alto, California  94304
  55  *
  56  * Redistributions of source code must retain the above copyright notice,
  57  * this list of conditions and the following disclaimer.  Redistributions
  58  * in binary form must reproduce the above copyright notice, this list of
  59  * conditions and the following disclaimer in the documentation and/or
  60  * other materials provided with the distribution.  Neither the name of
  61  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  62  * contributors may be used to endorse or promote products derived from
  63  * this software without specific prior written permission.  No right of
  64  * sublicense is granted herewith.  Derivatives of the software and
  65  * output created using the software may be prepared, but only for
  66  * Non-Commercial Uses.  Derivatives of the software may be shared with
  67  * others provided: (i) the others agree to abide by the list of
  68  * conditions herein which includes the Non-Commercial Use restrictions;
  69  * and (ii) such Derivatives of the software include the above copyright
  70  * notice to acknowledge the contribution from this software where
  71  * applicable, this list of conditions and the disclaimer below.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  74  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  75  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  76  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  77  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  78  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  79  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  80  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  81  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  82  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  83  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  84  *
  85  * Authors: Gabe Black
  86  */
  87
  88 #include "arch/x86/miscregfile.hh"
  89 #include "arch/x86/tlb.hh"
  90 #include "cpu/base.hh"
  91 #include "cpu/thread_context.hh"
  92 #include "sim/serialize.hh"
  93
  94 using namespace X86ISA;
  95 using namespace std;
  96
  97 class Checkpoint;
  98
  99 //These functions map register indices to names
 100 string X86ISA::getMiscRegName(RegIndex index)
 101 {
 102     panic("No misc registers in x86 yet!\n");
 103 }
 104
 105 void MiscRegFile::clear()
 106 {
 107     // Blank everything. 0 might not be an appropriate value for some things.
 108     memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
 109     //Set the local apic DFR to the flat model.
 110     regVal[MISCREG_APIC_DESTINATION_FORMAT] = (MiscReg)(-1);
 111 }
 112
 113 MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 114 {
 115     // Make sure we're not dealing with an illegal control register.
 116     // Instructions should filter out these indexes, and nothing else should
 117     // attempt to read them directly.
 118     assert( miscReg != MISCREG_CR1 &&
 119             !(miscReg > MISCREG_CR4 &&
 120               miscReg < MISCREG_CR8) &&
 121             !(miscReg > MISCREG_CR8 &&
 122               miscReg <= MISCREG_CR15));
 123
 124     return regVal[miscReg];
 125 }
 126
 127 MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
 128 {
 129     if (miscReg >= MISCREG_APIC_START && miscReg <= MISCREG_APIC_END) {
 130         if (miscReg >= MISCREG_APIC_IN_SERVICE(0) &&
 131                 miscReg <= MISCREG_APIC_IN_SERVICE(15)) {
 132             panic("Local APIC In-Service registers are unimplemented.\n");
 133         }
 134         if (miscReg >= MISCREG_APIC_TRIGGER_MODE(0) &&
 135                 miscReg <= MISCREG_APIC_TRIGGER_MODE(15)) {
 136             panic("Local APIC Trigger Mode registers are unimplemented.\n");
 137         }
 138         if (miscReg >= MISCREG_APIC_INTERRUPT_REQUEST(0) &&
 139                 miscReg <= MISCREG_APIC_INTERRUPT_REQUEST(15)) {
 140             panic("Local APIC Interrupt Request registers "
 141                     "are unimplemented.\n");
 142         }
 143         switch (miscReg) {
 144           case MISCREG_APIC_TASK_PRIORITY:
 145             panic("Local APIC Task Priority register unimplemented.\n");
 146             break;
 147           case MISCREG_APIC_ARBITRATION_PRIORITY:
 148             panic("Local APIC Arbitration Priority register unimplemented.\n");
 149             break;
 150           case MISCREG_APIC_PROCESSOR_PRIORITY:
 151             panic("Local APIC Processor Priority register unimplemented.\n");
 152             break;
 153           case MISCREG_APIC_EOI:
 154             panic("Local APIC EOI register unimplemented.\n");
 155             break;
 156           case MISCREG_APIC_ERROR_STATUS:
 157             regVal[MISCREG_APIC_INTERNAL_STATE] &= ~ULL(0x1);
 158             break;
 159           case MISCREG_APIC_INTERRUPT_COMMAND_LOW:
 160             panic("Local APIC Interrupt Command low"
 161                     " register unimplemented.\n");
 162             break;
 163           case MISCREG_APIC_INTERRUPT_COMMAND_HIGH:
 164             panic("Local APIC Interrupt Command high"
 165                     " register unimplemented.\n");
 166             break;
 167           case MISCREG_APIC_INITIAL_COUNT:
 168             panic("Local APIC Initial Count register unimplemented.\n");
 169             break;
 170           case MISCREG_APIC_CURRENT_COUNT:
 171             panic("Local APIC Current Count register unimplemented.\n");
 172             break;
 173           case MISCREG_APIC_DIVIDE_COUNT:
 174             panic("Local APIC Divide Count register unimplemented.\n");
 175             break;
 176         }
 177     }
 178     switch (miscReg) {
 179       case MISCREG_TSC:
 180         return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle();
 181     }
 182     return readRegNoEffect(miscReg);
 183 }
 184
 185 void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
 186 {
 187     // Make sure we're not dealing with an illegal control register.
 188     // Instructions should filter out these indexes, and nothing else should
 189     // attempt to write to them directly.
 190     assert( miscReg != MISCREG_CR1 &&
 191             !(miscReg > MISCREG_CR4 &&
 192               miscReg < MISCREG_CR8) &&
 193             !(miscReg > MISCREG_CR8 &&
 194               miscReg <= MISCREG_CR15));
 195     regVal[miscReg] = val;
 196 }
 197
 198 void MiscRegFile::setReg(int miscReg,
 199         const MiscReg &val, ThreadContext * tc)
 200 {
 201     MiscReg newVal = val;
 202     if (miscReg >= MISCREG_APIC_START && miscReg <= MISCREG_APIC_END) {
 203         if (miscReg >= MISCREG_APIC_IN_SERVICE(0) &&
 204                 miscReg <= MISCREG_APIC_IN_SERVICE(15)) {
 205             panic("Local APIC In-Service registers are unimplemented.\n");
 206         }
 207         if (miscReg >= MISCREG_APIC_TRIGGER_MODE(0) &&
 208                 miscReg <= MISCREG_APIC_TRIGGER_MODE(15)) {
 209             panic("Local APIC Trigger Mode registers are unimplemented.\n");
 210         }
 211         if (miscReg >= MISCREG_APIC_INTERRUPT_REQUEST(0) &&
 212                 miscReg <= MISCREG_APIC_INTERRUPT_REQUEST(15)) {
 213             panic("Local APIC Interrupt Request registers "
 214                     "are unimplemented.\n");
 215         }
 216         switch (miscReg) {
 217           case MISCREG_APIC_ID:
 218             newVal = val & 0xFF;
 219             break;
 220           case MISCREG_APIC_VERSION:
 221             // The Local APIC Version register is read only.
 222             return;
 223           case MISCREG_APIC_TASK_PRIORITY:
 224             panic("Local APIC Task Priority register unimplemented.\n");
 225             break;
 226           case MISCREG_APIC_ARBITRATION_PRIORITY:
 227             panic("Local APIC Arbitration Priority register unimplemented.\n");
 228             break;
 229           case MISCREG_APIC_PROCESSOR_PRIORITY:
 230             panic("Local APIC Processor Priority register unimplemented.\n");
 231             break;
 232           case MISCREG_APIC_EOI:
 233             panic("Local APIC EOI register unimplemented.\n");
 234             break;
 235           case MISCREG_APIC_LOGICAL_DESTINATION:
 236             newVal = val & 0xFF000000;
 237             break;
 238           case MISCREG_APIC_DESTINATION_FORMAT:
 239             newVal = val | 0x0FFFFFFF;
 240             break;
 241           case MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR:
 242             regVal[MISCREG_APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
 243             regVal[MISCREG_APIC_INTERNAL_STATE] |= val & (1 << 8);
 244             if (val & (1 << 9))
 245                 warn("Focus processor checking not implemented.\n");
 246             break;
 247           case MISCREG_APIC_ERROR_STATUS:
 248             {
 249                 if (regVal[MISCREG_APIC_INTERNAL_STATE] & 0x1) {
 250                     regVal[MISCREG_APIC_INTERNAL_STATE] &= ~ULL(0x1);
 251                     newVal = 0;
 252                 } else {
 253                     regVal[MISCREG_APIC_INTERNAL_STATE] |= ULL(0x1);
 254                     return;
 255                 }
 256
 257             }
 258             break;
 259           case MISCREG_APIC_INTERRUPT_COMMAND_LOW:
 260             panic("Local APIC Interrupt Command low"
 261                     " register unimplemented.\n");
 262             break;
 263           case MISCREG_APIC_INTERRUPT_COMMAND_HIGH:
 264             panic("Local APIC Interrupt Command high"
 265                     " register unimplemented.\n");
 266             break;
 267           case MISCREG_APIC_LVT_TIMER:
 268           case MISCREG_APIC_LVT_THERMAL_SENSOR:
 269           case MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
 270           case MISCREG_APIC_LVT_LINT0:
 271           case MISCREG_APIC_LVT_LINT1:
 272           case MISCREG_APIC_LVT_ERROR:
 273             {
 274                 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
 275                 newVal = (val & ~readOnlyMask) |
 276                          (regVal[miscReg] & readOnlyMask);
 277             }
 278             break;
 279           case MISCREG_APIC_INITIAL_COUNT:
 280             panic("Local APIC Initial Count register unimplemented.\n");
 281             break;
 282           case MISCREG_APIC_CURRENT_COUNT:
 283             panic("Local APIC Current Count register unimplemented.\n");
 284             break;
 285           case MISCREG_APIC_DIVIDE_COUNT:
 286             panic("Local APIC Divide Count register unimplemented.\n");
 287             break;
 288         }
 289         setRegNoEffect(miscReg, newVal);
 290         return;
 291     }
 292     switch(miscReg)
 293     {
 294       case MISCREG_CR0:
 295         {
 296             CR0 toggled = regVal[miscReg] ^ val;
 297             CR0 newCR0 = val;
 298             Efer efer = regVal[MISCREG_EFER];
 299             HandyM5Reg m5reg = regVal[MISCREG_M5_REG];
 300             if (toggled.pg && efer.lme) {
 301                 if (newCR0.pg) {
 302                     //Turning on long mode
 303                     efer.lma = 1;
 304                     m5reg.mode = LongMode;
 305                     regVal[MISCREG_EFER] = efer;
 306                 } else {
 307                     //Turning off long mode
 308                     efer.lma = 0;
 309                     m5reg.mode = LegacyMode;
 310                     regVal[MISCREG_EFER] = efer;
 311                 }
 312             }
 313             // Figure out what submode we're in.
 314             if (m5reg.mode == LongMode) {
 315                 SegAttr csAttr = regVal[MISCREG_CS_ATTR];
 316                 if (csAttr.longMode)
 317                     m5reg.submode = SixtyFourBitMode;
 318                 else
 319                     m5reg.submode = CompatabilityMode;
 320             } else {
 321                 if (newCR0.pe) {
 322                     RFLAGS rflags = regVal[MISCREG_RFLAGS];
 323                     if (rflags.vm)
 324                         m5reg.submode = Virtual8086Mode;
 325                     else
 326                         m5reg.submode = ProtectedMode;
 327                 } else {
 328                     m5reg.submode = RealMode;
 329                 }
 330             }
 331             regVal[MISCREG_M5_REG] = m5reg;
 332             if (toggled.pg) {
 333                 tc->getITBPtr()->invalidateAll();
 334                 tc->getDTBPtr()->invalidateAll();
 335             }
 336             //This must always be 1.
 337             newCR0.et = 1;
 338             newVal = newCR0;
 339         }
 340         break;
 341       case MISCREG_CR2:
 342         break;
 343       case MISCREG_CR3:
 344         tc->getITBPtr()->invalidateNonGlobal();
 345         tc->getDTBPtr()->invalidateNonGlobal();
 346         break;
 347       case MISCREG_CR4:
 348         {
 349             CR4 toggled = regVal[miscReg] ^ val;
 350             if (toggled.pae || toggled.pse || toggled.pge) {
 351                 tc->getITBPtr()->invalidateAll();
 352                 tc->getDTBPtr()->invalidateAll();
 353             }
 354         }
 355         break;
 356       case MISCREG_CR8:
 357         break;
 358       case MISCREG_CS_ATTR:
 359         {
 360             SegAttr toggled = regVal[miscReg] ^ val;
 361             SegAttr newCSAttr = val;
 362             HandyM5Reg m5reg = regVal[MISCREG_M5_REG];
 363             if (toggled.longMode) {
 364                 if (newCSAttr.longMode) {
 365                     if (m5reg.mode == LongMode)
 366                         m5reg.submode = SixtyFourBitMode;
 367                     regVal[MISCREG_ES_EFF_BASE] = 0;
 368                     regVal[MISCREG_CS_EFF_BASE] = 0;
 369                     regVal[MISCREG_SS_EFF_BASE] = 0;
 370                     regVal[MISCREG_DS_EFF_BASE] = 0;
 371                 } else {
 372                     if (m5reg.mode == LongMode)
 373                         m5reg.submode = CompatabilityMode;
 374                     regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
 375                     regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
 376                     regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
 377                     regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
 378                 }
 379             }
 380             m5reg.cpl = newCSAttr.dpl;
 381             regVal[MISCREG_M5_REG] = m5reg;
 382         }
 383         break;
 384       // These segments always actually use their bases, or in other words
 385       // their effective bases must stay equal to their actual bases.
 386       case MISCREG_FS_BASE:
 387       case MISCREG_GS_BASE:
 388       case MISCREG_HS_BASE:
 389       case MISCREG_TSL_BASE:
 390       case MISCREG_TSG_BASE:
 391       case MISCREG_TR_BASE:
 392       case MISCREG_IDTR_BASE:
 393         regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
 394         break;
 395       // These segments ignore their bases in 64 bit mode.
 396       // their effective bases must stay equal to their actual bases.
 397       case MISCREG_ES_BASE:
 398       case MISCREG_CS_BASE:
 399       case MISCREG_SS_BASE:
 400       case MISCREG_DS_BASE:
 401         {
 402             Efer efer = regVal[MISCREG_EFER];
 403             SegAttr csAttr = regVal[MISCREG_CS_ATTR];
 404             if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
 405                 regVal[MISCREG_SEG_EFF_BASE(miscReg -
 406                         MISCREG_SEG_BASE_BASE)] = val;
 407         }
 408         break;
 409       case MISCREG_TSC:
 410         regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle();
 411         return;
 412     }
 413     setRegNoEffect(miscReg, newVal);
 414 }
 415
 416 void MiscRegFile::serialize(std::ostream & os)
 417 {
 418     SERIALIZE_ARRAY(regVal, NumMiscRegs);
 419 }
 420
 421 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 422 {
 423     UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
 424 }