src/arch/x86/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2006, 2008 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 /*
  32  * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
  33  * All rights reserved.
  34  *
  35  * Redistribution and use of this software in source and binary forms,
  36  * with or without modification, are permitted provided that the
  37  * following conditions are met:
  38  *
  39  * The software must be used only for Non-Commercial Use which means any
  40  * use which is NOT directed to receiving any direct monetary
  41  * compensation for, or commercial advantage from such use.  Illustrative
  42  * examples of non-commercial use are academic research, personal study,
  43  * teaching, education and corporate research & development.
  44  * Illustrative examples of commercial use are distributing products for
  45  * commercial advantage and providing services using the software for
  46  * commercial advantage.
  47  *
  48  * If you wish to use this software or functionality therein that may be
  49  * covered by patents for commercial use, please contact:
  50  *     Director of Intellectual Property Licensing
  51  *     Office of Strategy and Technology
  52  *     Hewlett-Packard Company
  53  *     1501 Page Mill Road
  54  *     Palo Alto, California  94304
  55  *
  56  * Redistributions of source code must retain the above copyright notice,
  57  * this list of conditions and the following disclaimer.  Redistributions
  58  * in binary form must reproduce the above copyright notice, this list of
  59  * conditions and the following disclaimer in the documentation and/or
  60  * other materials provided with the distribution.  Neither the name of
  61  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  62  * contributors may be used to endorse or promote products derived from
  63  * this software without specific prior written permission.  No right of
  64  * sublicense is granted herewith.  Derivatives of the software and
  65  * output created using the software may be prepared, but only for
  66  * Non-Commercial Uses.  Derivatives of the software may be shared with
  67  * others provided: (i) the others agree to abide by the list of
  68  * conditions herein which includes the Non-Commercial Use restrictions;
  69  * and (ii) such Derivatives of the software include the above copyright
  70  * notice to acknowledge the contribution from this software where
  71  * applicable, this list of conditions and the disclaimer below.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  74  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  75  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  76  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  77  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  78  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  79  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  80  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  81  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  82  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  83  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  84  *
  85  * Authors: Gabe Black
  86  */
  87
  88 #include "arch/x86/miscregfile.hh"
  89 #include "arch/x86/tlb.hh"
  90 #include "cpu/thread_context.hh"
  91 #include "sim/serialize.hh"
  92
  93 using namespace X86ISA;
  94 using namespace std;
  95
  96 class Checkpoint;
  97
  98 //These functions map register indices to names
  99 string X86ISA::getMiscRegName(RegIndex index)
 100 {
 101     panic("No misc registers in x86 yet!\n");
 102 }
 103
 104 void MiscRegFile::clear()
 105 {
 106     // Blank everything. 0 might not be an appropriate value for some things.
 107     memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
 108 }
 109
 110 MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 111 {
 112     // Make sure we're not dealing with an illegal control register.
 113     // Instructions should filter out these indexes, and nothing else should
 114     // attempt to read them directly.
 115     assert( miscReg != MISCREG_CR1 &&
 116             !(miscReg > MISCREG_CR4 &&
 117               miscReg < MISCREG_CR8) &&
 118             !(miscReg > MISCREG_CR8 &&
 119               miscReg <= MISCREG_CR15));
 120
 121     return regVal[miscReg];
 122 }
 123
 124 MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
 125 {
 126     if (miscReg >= MISCREG_APIC_START && miscReg <= MISCREG_APIC_END) {
 127         if (miscReg >= MISCREG_APIC_IN_SERVICE(0) &&
 128                 miscReg <= MISCREG_APIC_IN_SERVICE(15)) {
 129             panic("Local APIC In-Service registers are unimplemented.\n");
 130         }
 131         if (miscReg >= MISCREG_APIC_TRIGGER_MODE(0) &&
 132                 miscReg <= MISCREG_APIC_TRIGGER_MODE(15)) {
 133             panic("Local APIC Trigger Mode registers are unimplemented.\n");
 134         }
 135         if (miscReg >= MISCREG_APIC_INTERRUPT_REQUEST(0) &&
 136                 miscReg <= MISCREG_APIC_INTERRUPT_REQUEST(15)) {
 137             panic("Local APIC Interrupt Request registers "
 138                     "are unimplemented.\n");
 139         }
 140         switch (miscReg) {
 141           case MISCREG_APIC_TASK_PRIORITY:
 142             panic("Local APIC Task Priority register unimplemented.\n");
 143             break;
 144           case MISCREG_APIC_ARBITRATION_PRIORITY:
 145             panic("Local APIC Arbitration Priority register unimplemented.\n");
 146             break;
 147           case MISCREG_APIC_PROCESSOR_PRIORITY:
 148             panic("Local APIC Processor Priority register unimplemented.\n");
 149             break;
 150           case MISCREG_APIC_EOI:
 151             panic("Local APIC EOI register unimplemented.\n");
 152             break;
 153           case MISCREG_APIC_LOGICAL_DESTINATION:
 154             panic("Local APIC Logical Destination register unimplemented.\n");
 155             break;
 156           case MISCREG_APIC_DESTINATION_FORMAT:
 157             panic("Local APIC Destination Format register unimplemented.\n");
 158             break;
 159           case MISCREG_APIC_ERROR_STATUS:
 160             regVal[MISCREG_APIC_INTERNAL_STATE] &= ~ULL(0x1);
 161             break;
 162           case MISCREG_APIC_INTERRUPT_COMMAND_LOW:
 163             panic("Local APIC Interrupt Command low"
 164                     " register unimplemented.\n");
 165             break;
 166           case MISCREG_APIC_INTERRUPT_COMMAND_HIGH:
 167             panic("Local APIC Interrupt Command high"
 168                     " register unimplemented.\n");
 169             break;
 170           case MISCREG_APIC_INITIAL_COUNT:
 171             panic("Local APIC Initial Count register unimplemented.\n");
 172             break;
 173           case MISCREG_APIC_CURRENT_COUNT:
 174             panic("Local APIC Current Count register unimplemented.\n");
 175             break;
 176           case MISCREG_APIC_DIVIDE_COUNT:
 177             panic("Local APIC Divide Count register unimplemented.\n");
 178             break;
 179         }
 180     }
 181     return readRegNoEffect(miscReg);
 182 }
 183
 184 void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
 185 {
 186     // Make sure we're not dealing with an illegal control register.
 187     // Instructions should filter out these indexes, and nothing else should
 188     // attempt to write to them directly.
 189     assert( miscReg != MISCREG_CR1 &&
 190             !(miscReg > MISCREG_CR4 &&
 191               miscReg < MISCREG_CR8) &&
 192             !(miscReg > MISCREG_CR8 &&
 193               miscReg <= MISCREG_CR15));
 194     regVal[miscReg] = val;
 195 }
 196
 197 void MiscRegFile::setReg(int miscReg,
 198         const MiscReg &val, ThreadContext * tc)
 199 {
 200     MiscReg newVal = val;
 201     if (miscReg >= MISCREG_APIC_START && miscReg <= MISCREG_APIC_END) {
 202         if (miscReg >= MISCREG_APIC_IN_SERVICE(0) &&
 203                 miscReg <= MISCREG_APIC_IN_SERVICE(15)) {
 204             panic("Local APIC In-Service registers are unimplemented.\n");
 205         }
 206         if (miscReg >= MISCREG_APIC_TRIGGER_MODE(0) &&
 207                 miscReg <= MISCREG_APIC_TRIGGER_MODE(15)) {
 208             panic("Local APIC Trigger Mode registers are unimplemented.\n");
 209         }
 210         if (miscReg >= MISCREG_APIC_INTERRUPT_REQUEST(0) &&
 211                 miscReg <= MISCREG_APIC_INTERRUPT_REQUEST(15)) {
 212             panic("Local APIC Interrupt Request registers "
 213                     "are unimplemented.\n");
 214         }
 215         switch (miscReg) {
 216           case MISCREG_APIC_ID:
 217             panic("Local APIC ID register unimplemented.\n");
 218             break;
 219           case MISCREG_APIC_VERSION:
 220             panic("Local APIC Version register is read only.\n");
 221             break;
 222           case MISCREG_APIC_TASK_PRIORITY:
 223             panic("Local APIC Task Priority register unimplemented.\n");
 224             break;
 225           case MISCREG_APIC_ARBITRATION_PRIORITY:
 226             panic("Local APIC Arbitration Priority register unimplemented.\n");
 227             break;
 228           case MISCREG_APIC_PROCESSOR_PRIORITY:
 229             panic("Local APIC Processor Priority register unimplemented.\n");
 230             break;
 231           case MISCREG_APIC_EOI:
 232             panic("Local APIC EOI register unimplemented.\n");
 233             break;
 234           case MISCREG_APIC_LOGICAL_DESTINATION:
 235             panic("Local APIC Logical Destination register unimplemented.\n");
 236             break;
 237           case MISCREG_APIC_DESTINATION_FORMAT:
 238             panic("Local APIC Destination Format register unimplemented.\n");
 239             break;
 240           case MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR:
 241             regVal[MISCREG_APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
 242             regVal[MISCREG_APIC_INTERNAL_STATE] |= val & (1 << 8);
 243             if (val & (1 << 9))
 244                 warn("Focus processor checking not implemented.\n");
 245             break;
 246           case MISCREG_APIC_ERROR_STATUS:
 247             {
 248                 if (regVal[MISCREG_APIC_INTERNAL_STATE] & 0x1) {
 249                     regVal[MISCREG_APIC_INTERNAL_STATE] &= ~ULL(0x1);
 250                     newVal = 0;
 251                 } else {
 252                     regVal[MISCREG_APIC_INTERNAL_STATE] |= ULL(0x1);
 253                     return;
 254                 }
 255
 256             }
 257             break;
 258           case MISCREG_APIC_INTERRUPT_COMMAND_LOW:
 259             panic("Local APIC Interrupt Command low"
 260                     " register unimplemented.\n");
 261             break;
 262           case MISCREG_APIC_INTERRUPT_COMMAND_HIGH:
 263             panic("Local APIC Interrupt Command high"
 264                     " register unimplemented.\n");
 265             break;
 266           case MISCREG_APIC_LVT_TIMER:
 267           case MISCREG_APIC_LVT_THERMAL_SENSOR:
 268           case MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
 269           case MISCREG_APIC_LVT_LINT0:
 270           case MISCREG_APIC_LVT_LINT1:
 271           case MISCREG_APIC_LVT_ERROR:
 272             {
 273                 uint64_t readOnlyMask = (1 << 12) | (1 << 14);
 274                 newVal = (val & ~readOnlyMask) |
 275                          (regVal[miscReg] & readOnlyMask);
 276             }
 277             break;
 278           case MISCREG_APIC_INITIAL_COUNT:
 279             panic("Local APIC Initial Count register unimplemented.\n");
 280             break;
 281           case MISCREG_APIC_CURRENT_COUNT:
 282             panic("Local APIC Current Count register unimplemented.\n");
 283             break;
 284           case MISCREG_APIC_DIVIDE_COUNT:
 285             panic("Local APIC Divide Count register unimplemented.\n");
 286             break;
 287         }
 288         setRegNoEffect(miscReg, newVal);
 289         return;
 290     }
 291     switch(miscReg)
 292     {
 293       case MISCREG_CR0:
 294         {
 295             CR0 toggled = regVal[miscReg] ^ val;
 296             CR0 newCR0 = val;
 297             Efer efer = regVal[MISCREG_EFER];
 298             if (toggled.pg && efer.lme) {
 299                 if (newCR0.pg) {
 300                     //Turning on long mode
 301                     efer.lma = 1;
 302                     regVal[MISCREG_EFER] = efer;
 303                 } else {
 304                     //Turning off long mode
 305                     efer.lma = 0;
 306                     regVal[MISCREG_EFER] = efer;
 307                 }
 308             }
 309             if (toggled.pg) {
 310                 tc->getITBPtr()->invalidateAll();
 311                 tc->getDTBPtr()->invalidateAll();
 312             }
 313             //This must always be 1.
 314             newCR0.et = 1;
 315             newVal = newCR0;
 316         }
 317         break;
 318       case MISCREG_CR2:
 319         break;
 320       case MISCREG_CR3:
 321         tc->getITBPtr()->invalidateNonGlobal();
 322         tc->getDTBPtr()->invalidateNonGlobal();
 323         break;
 324       case MISCREG_CR4:
 325         {
 326             CR4 toggled = regVal[miscReg] ^ val;
 327             if (toggled.pae || toggled.pse || toggled.pge) {
 328                 tc->getITBPtr()->invalidateAll();
 329                 tc->getDTBPtr()->invalidateAll();
 330             }
 331         }
 332         break;
 333       case MISCREG_CR8:
 334         break;
 335       case MISCREG_CS_ATTR:
 336         {
 337             SegAttr toggled = regVal[miscReg] ^ val;
 338             SegAttr newCSAttr = val;
 339             if (toggled.longMode) {
 340                 SegAttr newCSAttr = val;
 341                 if (newCSAttr.longMode) {
 342                     regVal[MISCREG_ES_EFF_BASE] = 0;
 343                     regVal[MISCREG_CS_EFF_BASE] = 0;
 344                     regVal[MISCREG_SS_EFF_BASE] = 0;
 345                     regVal[MISCREG_DS_EFF_BASE] = 0;
 346                 } else {
 347                     regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
 348                     regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
 349                     regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
 350                     regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
 351                 }
 352             }
 353         }
 354         break;
 355       // These segments always actually use their bases, or in other words
 356       // their effective bases must stay equal to their actual bases.
 357       case MISCREG_FS_BASE:
 358       case MISCREG_GS_BASE:
 359       case MISCREG_HS_BASE:
 360       case MISCREG_TSL_BASE:
 361       case MISCREG_TSG_BASE:
 362       case MISCREG_TR_BASE:
 363       case MISCREG_IDTR_BASE:
 364         regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val;
 365         break;
 366       // These segments ignore their bases in 64 bit mode.
 367       // their effective bases must stay equal to their actual bases.
 368       case MISCREG_ES_BASE:
 369       case MISCREG_CS_BASE:
 370       case MISCREG_SS_BASE:
 371       case MISCREG_DS_BASE:
 372         {
 373             Efer efer = regVal[MISCREG_EFER];
 374             SegAttr csAttr = regVal[MISCREG_CS_ATTR];
 375             if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
 376                 regVal[MISCREG_SEG_EFF_BASE(miscReg -
 377                         MISCREG_SEG_BASE_BASE)] = val;
 378         }
 379         break;
 380     }
 381     setRegNoEffect(miscReg, newVal);
 382 }
 383
 384 void MiscRegFile::serialize(std::ostream & os)
 385 {
 386     SERIALIZE_ARRAY(regVal, NumMiscRegs);
 387 }
 388
 389 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 390 {
 391     UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
 392 }