src/arch/x86/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 /*
  32  * Copyright (c) 2007 The Hewlett-Packard Development Company
  33  * All rights reserved.
  34  *
  35  * Redistribution and use of this software in source and binary forms,
  36  * with or without modification, are permitted provided that the
  37  * following conditions are met:
  38  *
  39  * The software must be used only for Non-Commercial Use which means any
  40  * use which is NOT directed to receiving any direct monetary
  41  * compensation for, or commercial advantage from such use.  Illustrative
  42  * examples of non-commercial use are academic research, personal study,
  43  * teaching, education and corporate research & development.
  44  * Illustrative examples of commercial use are distributing products for
  45  * commercial advantage and providing services using the software for
  46  * commercial advantage.
  47  *
  48  * If you wish to use this software or functionality therein that may be
  49  * covered by patents for commercial use, please contact:
  50  *     Director of Intellectual Property Licensing
  51  *     Office of Strategy and Technology
  52  *     Hewlett-Packard Company
  53  *     1501 Page Mill Road
  54  *     Palo Alto, California  94304
  55  *
  56  * Redistributions of source code must retain the above copyright notice,
  57  * this list of conditions and the following disclaimer.  Redistributions
  58  * in binary form must reproduce the above copyright notice, this list of
  59  * conditions and the following disclaimer in the documentation and/or
  60  * other materials provided with the distribution.  Neither the name of
  61  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  62  * contributors may be used to endorse or promote products derived from
  63  * this software without specific prior written permission.  No right of
  64  * sublicense is granted herewith.  Derivatives of the software and
  65  * output created using the software may be prepared, but only for
  66  * Non-Commercial Uses.  Derivatives of the software may be shared with
  67  * others provided: (i) the others agree to abide by the list of
  68  * conditions herein which includes the Non-Commercial Use restrictions;
  69  * and (ii) such Derivatives of the software include the above copyright
  70  * notice to acknowledge the contribution from this software where
  71  * applicable, this list of conditions and the disclaimer below.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  74  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  75  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  76  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  77  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  78  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  79  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  80  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  81  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  82  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  83  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  84  *
  85  * Authors: Gabe Black
  86  */
  87
  88 #include "arch/x86/miscregfile.hh"
  89 #include "arch/x86/tlb.hh"
  90 #include "cpu/thread_context.hh"
  91 #include "sim/serialize.hh"
  92
  93 using namespace X86ISA;
  94 using namespace std;
  95
  96 class Checkpoint;
  97
  98 //These functions map register indices to names
  99 string X86ISA::getMiscRegName(RegIndex index)
 100 {
 101     panic("No misc registers in x86 yet!\n");
 102 }
 103
 104 void MiscRegFile::clear()
 105 {
 106     // Blank everything. 0 might not be an appropriate value for some things.
 107     memset(regVal, 0, NumMiscRegs * sizeof(MiscReg));
 108 }
 109
 110 MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 111 {
 112     // Make sure we're not dealing with an illegal control register.
 113     // Instructions should filter out these indexes, and nothing else should
 114     // attempt to read them directly.
 115     assert( miscReg != MISCREG_CR1 &&
 116             !(miscReg > MISCREG_CR4 &&
 117               miscReg < MISCREG_CR8) &&
 118             !(miscReg > MISCREG_CR8 &&
 119               miscReg <= MISCREG_CR15));
 120
 121     return regVal[miscReg];
 122 }
 123
 124 MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
 125 {
 126     return readRegNoEffect(miscReg);
 127 }
 128
 129 void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
 130 {
 131     // Make sure we're not dealing with an illegal control register.
 132     // Instructions should filter out these indexes, and nothing else should
 133     // attempt to write to them directly.
 134     assert( miscReg != MISCREG_CR1 &&
 135             !(miscReg > MISCREG_CR4 &&
 136               miscReg < MISCREG_CR8) &&
 137             !(miscReg > MISCREG_CR8 &&
 138               miscReg <= MISCREG_CR15));
 139     regVal[miscReg] = val;
 140 }
 141
 142 void MiscRegFile::setReg(int miscReg,
 143         const MiscReg &val, ThreadContext * tc)
 144 {
 145     MiscReg newVal = val;
 146     switch(miscReg)
 147     {
 148       case MISCREG_CR0:
 149         {
 150             CR0 toggled = regVal[miscReg] ^ val;
 151             CR0 newCR0 = val;
 152             Efer efer = regVal[MISCREG_EFER];
 153             if (toggled.pg && efer.lme) {
 154                 if (newCR0.pg) {
 155                     //Turning on long mode
 156                     efer.lma = 1;
 157                     regVal[MISCREG_EFER] = efer;
 158                 } else {
 159                     //Turning off long mode
 160                     efer.lma = 0;
 161                     regVal[MISCREG_EFER] = efer;
 162                 }
 163             }
 164             if (toggled.pg) {
 165                 tc->getITBPtr()->invalidateAll();
 166                 tc->getDTBPtr()->invalidateAll();
 167             }
 168             //This must always be 1.
 169             newCR0.et = 1;
 170             newVal = newCR0;
 171         }
 172         break;
 173       case MISCREG_CR2:
 174         break;
 175       case MISCREG_CR3:
 176         tc->getITBPtr()->invalidateNonGlobal();
 177         tc->getDTBPtr()->invalidateNonGlobal();
 178         break;
 179       case MISCREG_CR4:
 180         {
 181             CR4 toggled = regVal[miscReg] ^ val;
 182             if (toggled.pae || toggled.pse || toggled.pge) {
 183                 tc->getITBPtr()->invalidateAll();
 184                 tc->getDTBPtr()->invalidateAll();
 185             }
 186         }
 187         break;
 188       case MISCREG_CR8:
 189         break;
 190       case MISCREG_CS_ATTR:
 191         {
 192             SegAttr toggled = regVal[miscReg] ^ val;
 193             SegAttr newCSAttr = val;
 194             if (toggled.longMode) {
 195                 SegAttr newCSAttr = val;
 196                 if (newCSAttr.longMode) {
 197                     regVal[MISCREG_ES_EFF_BASE] = 0;
 198                     regVal[MISCREG_CS_EFF_BASE] = 0;
 199                     regVal[MISCREG_SS_EFF_BASE] = 0;
 200                     regVal[MISCREG_DS_EFF_BASE] = 0;
 201                 } else {
 202                     regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE];
 203                     regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE];
 204                     regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE];
 205                     regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE];
 206                 }
 207             }
 208         }
 209       // These segments always actually use their bases, or in other words
 210       // their effective bases must stay equal to their actual bases.
 211       case MISCREG_FS:
 212       case MISCREG_GS:
 213       case MISCREG_HS:
 214       case MISCREG_TSL:
 215       case MISCREG_TSG:
 216       case MISCREG_TR:
 217       case MISCREG_IDTR:
 218         regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_SEL_BASE)] = val;
 219         break;
 220       // These segments ignore their bases in 64 bit mode.
 221       // their effective bases must stay equal to their actual bases.
 222       case MISCREG_ES:
 223       case MISCREG_CS:
 224       case MISCREG_SS:
 225       case MISCREG_DS:
 226         {
 227             Efer efer = regVal[MISCREG_EFER];
 228             SegAttr csAttr = regVal[MISCREG_CS_ATTR];
 229             if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode.
 230                 regVal[MISCREG_SEG_EFF_BASE(miscReg -
 231                         MISCREG_SEG_SEL_BASE)] = val;
 232         }
 233         break;
 234     }
 235     setRegNoEffect(miscReg, newVal);
 236 }
 237
 238 void MiscRegFile::serialize(std::ostream & os)
 239 {
 240     SERIALIZE_ARRAY(regVal, NumMiscRegs);
 241 }
 242
 243 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 244 {
 245     UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
 246 }