src/arch/x86/miscregs.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
   7  * following conditions are met:
   8  *
   9  * The software must be used only for Non-Commercial Use which means any
  10  * use which is NOT directed to receiving any direct monetary
  11  * compensation for, or commercial advantage from such use.  Illustrative
  12  * examples of non-commercial use are academic research, personal study,
  13  * teaching, education and corporate research & development.
  14  * Illustrative examples of commercial use are distributing products for
  15  * commercial advantage and providing services using the software for
  16  * commercial advantage.
  17  *
  18  * If you wish to use this software or functionality therein that may be
  19  * covered by patents for commercial use, please contact:
  20  *     Director of Intellectual Property Licensing
  21  *     Office of Strategy and Technology
  22  *     Hewlett-Packard Company
  23  *     1501 Page Mill Road
  24  *     Palo Alto, California  94304
  25  *
  26  * Redistributions of source code must retain the above copyright notice,
  27  * this list of conditions and the following disclaimer.  Redistributions
  28  * in binary form must reproduce the above copyright notice, this list of
  29  * conditions and the following disclaimer in the documentation and/or
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  31  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  32  * contributors may be used to endorse or promote products derived from
  33  * this software without specific prior written permission.  No right of
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  35  * output created using the software may be prepared, but only for
  36  * Non-Commercial Uses.  Derivatives of the software may be shared with
  37  * others provided: (i) the others agree to abide by the list of
  38  * conditions herein which includes the Non-Commercial Use restrictions;
  39  * and (ii) such Derivatives of the software include the above copyright
  40  * notice to acknowledge the contribution from this software where
  41  * applicable, this list of conditions and the disclaimer below.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_MISCREGS_HH__
  59 #define __ARCH_X86_MISCREGS_HH__
  60
  61 #include "arch/x86/x86_traits.hh"
  62 #include "base/bitunion.hh"
  63
  64 namespace X86ISA
  65 {
  66     enum CondFlagBit {
  67         CFBit = 1 << 0,
  68         PFBit = 1 << 2,
  69         ECFBit = 1 << 3,
  70         AFBit = 1 << 4,
  71         EZFBit = 1 << 5,
  72         ZFBit = 1 << 6,
  73         SFBit = 1 << 7,
  74         DFBit = 1 << 10,
  75         OFBit = 1 << 11
  76     };
  77
  78     enum MiscRegIndex
  79     {
  80         // Control registers
  81         // Most of these are invalid.
  82         MISCREG_CR_BASE,
  83         MISCREG_CR0 = MISCREG_CR_BASE,
  84         MISCREG_CR1,
  85         MISCREG_CR2,
  86         MISCREG_CR3,
  87         MISCREG_CR4,
  88         MISCREG_CR5,
  89         MISCREG_CR6,
  90         MISCREG_CR7,
  91         MISCREG_CR8,
  92         MISCREG_CR9,
  93         MISCREG_CR10,
  94         MISCREG_CR11,
  95         MISCREG_CR12,
  96         MISCREG_CR13,
  97         MISCREG_CR14,
  98         MISCREG_CR15,
  99
 100         // Debug registers
 101         MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
 102         MISCREG_DR0 = MISCREG_DR_BASE,
 103         MISCREG_DR1,
 104         MISCREG_DR2,
 105         MISCREG_DR3,
 106         MISCREG_DR4,
 107         MISCREG_DR5,
 108         MISCREG_DR6,
 109         MISCREG_DR7,
 110
 111         // Flags register
 112         MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
 113
 114         // Segment selectors
 115         MISCREG_SEG_SEL_BASE,
 116         MISCREG_ES = MISCREG_SEG_SEL_BASE,
 117         MISCREG_CS,
 118         MISCREG_SS,
 119         MISCREG_DS,
 120         MISCREG_FS,
 121         MISCREG_GS,
 122
 123         // Hidden segment base field
 124         MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
 125         MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
 126         MISCREG_CS_BASE,
 127         MISCREG_SS_BASE,
 128         MISCREG_DS_BASE,
 129         MISCREG_FS_BASE,
 130         MISCREG_GS_BASE,
 131
 132         // Hidden segment limit field
 133         MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
 134         MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
 135         MISCREG_CS_LIMIT,
 136         MISCREG_SS_LIMIT,
 137         MISCREG_DS_LIMIT,
 138         MISCREG_FS_LIMIT,
 139         MISCREG_GS_LIMIT,
 140
 141         // Hidden segment limit attributes
 142         MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
 143         MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
 144         MISCREG_CS_ATTR,
 145         MISCREG_SS_ATTR,
 146         MISCREG_DS_ATTR,
 147         MISCREG_FS_ATTR,
 148         MISCREG_GS_ATTR,
 149
 150         // System segment selectors
 151         MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
 152         MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
 153         MISCREG_TR,
 154
 155         // Hidden system segment base field
 156         MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
 157         MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
 158         MISCREG_TR_BASE,
 159         MISCREG_GDTR_BASE,
 160         MISCREG_IDTR_BASE,
 161
 162         // Hidden system segment limit field
 163         MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
 164         MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
 165         MISCREG_TR_LIMIT,
 166         MISCREG_GDTR_LIMIT,
 167         MISCREG_IDTR_LIMIT,
 168
 169         // Hidden system segment attribute field
 170         MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
 171         MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
 172         MISCREG_TR_ATTR,
 173
 174         //XXX Add "Model-Specific Registers"
 175
 176         NUM_MISCREGS = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments
 177     };
 178
 179     static inline MiscRegIndex
 180     MISCREG_CR(int index)
 181     {
 182         return (MiscRegIndex)(MISCREG_CR_BASE + index);
 183     }
 184
 185     static inline MiscRegIndex
 186     MISCREG_DR(int index)
 187     {
 188         return (MiscRegIndex)(MISCREG_DR_BASE + index);
 189     }
 190
 191     static inline MiscRegIndex
 192     MISCREG_SEG_SEL(int index)
 193     {
 194         return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
 195     }
 196
 197     static inline MiscRegIndex
 198     MISCREG_SEG_BASE(int index)
 199     {
 200         return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
 201     }
 202
 203     static inline MiscRegIndex
 204     MISCREG_SEG_LIMIT(int index)
 205     {
 206         return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
 207     }
 208
 209     static inline MiscRegIndex
 210     MISCREG_SEG_ATTR(int index)
 211     {
 212         return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
 213     }
 214
 215     static inline MiscRegIndex
 216     MISCREG_SYSSEG_SEL(int index)
 217     {
 218         return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
 219     }
 220
 221     static inline MiscRegIndex
 222     MISCREG_SYSSEG_BASE(int index)
 223     {
 224         return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
 225     }
 226
 227     static inline MiscRegIndex
 228     MISCREG_SYSSEG_LIMIT(int index)
 229     {
 230         return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
 231     }
 232
 233     static inline MiscRegIndex
 234     MISCREG_SYSSEG_ATTR(int index)
 235     {
 236         return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
 237     }
 238
 239     /**
 240      * A type to describe the condition code bits of the RFLAGS register,
 241      * plus two flags, EZF and ECF, which are only visible to microcode.
 242      */
 243     BitUnion64(CCFlagBits)
 244         Bitfield<11> OF;
 245         Bitfield<7> SF;
 246         Bitfield<6> ZF;
 247         Bitfield<5> EZF;
 248         Bitfield<4> AF;
 249         Bitfield<3> ECF;
 250         Bitfield<2> PF;
 251         Bitfield<0> CF;
 252     EndBitUnion(CCFlagBits)
 253
 254     /**
 255      * RFLAGS
 256      */
 257     BitUnion64(RFLAGS)
 258         Bitfield<21> ID; // ID Flag
 259         Bitfield<20> VIP; // Virtual Interrupt Pending
 260         Bitfield<19> VIF; // Virtual Interrupt Flag
 261         Bitfield<18> AC; // Alignment Check
 262         Bitfield<17> VM; // Virtual-8086 Mode
 263         Bitfield<16> RF; // Resume Flag
 264         Bitfield<14> NT; // Nested Task
 265         Bitfield<13, 12> IOPL; // I/O Privilege Level
 266         Bitfield<11> OF; // Overflow Flag
 267         Bitfield<10> DF; // Direction Flag
 268         Bitfield<9> IF; // Interrupt Flag
 269         Bitfield<8> TF; // Trap Flag
 270         Bitfield<7> SF; // Sign Flag
 271         Bitfield<6> ZF; // Zero Flag
 272         Bitfield<4> AF; // Auxiliary Flag
 273         Bitfield<2> PF; // Parity Flag
 274         Bitfield<0> CF; // Carry Flag
 275     EndBitUnion(RFLAGS)
 276
 277     /**
 278      * Control registers
 279      */
 280     BitUnion64(CR0)
 281         Bitfield<31> PG; // Paging
 282         Bitfield<30> CD; // Cache Disable
 283         Bitfield<29> NW; // Not Writethrough
 284         Bitfield<18> AM; // Alignment Mask
 285         Bitfield<16> WP; // Write Protect
 286         Bitfield<5> NE; // Numeric Error
 287         Bitfield<4> ET; // Extension Type
 288         Bitfield<3> TS; // Task Switched
 289         Bitfield<2> EM; // Emulation
 290         Bitfield<1> MP; // Monitor Coprocessor
 291         Bitfield<0> PE; // Protection Enabled
 292     EndBitUnion(CR0)
 293
 294     // Page Fault Virtual Address
 295     BitUnion64(CR2)
 296         Bitfield<31, 0> legacy;
 297     EndBitUnion(CR2)
 298
 299     BitUnion64(CR3)
 300         Bitfield<51, 12> longPDTB; // Long Mode Page-Directory-Table
 301                                    // Base Address
 302         Bitfield<31, 12> PDTB; // Non-PAE Addressing Page-Directory-Table
 303                                // Base Address
 304         Bitfield<31, 5> PAEPDTB; // PAE Addressing Page-Directory-Table
 305                                  // Base Address
 306         Bitfield<4> PCD; // Page-Level Cache Disable
 307         Bitfield<3> PWT; // Page-Level Writethrough
 308     EndBitUnion(CR3)
 309
 310     BitUnion64(CR4)
 311         Bitfield<10> OSXMMEXCPT; // Operating System Unmasked
 312                                  // Exception Support
 313         Bitfield<9> OSFXSR; // Operating System FXSave/FSRSTOR Support
 314         Bitfield<8> PCE; // Performance-Monitoring Counter Enable
 315         Bitfield<7> PGE; // Page-Global Enable
 316         Bitfield<6> MCE; // Machine Check Enable
 317         Bitfield<5> PAE; // Physical-Address Extension
 318         Bitfield<4> PSE; // Page Size Extensions
 319         Bitfield<3> DE; // Debugging Extensions
 320         Bitfield<2> TSD; // Time Stamp Disable
 321         Bitfield<1> PVI; // Protected-Mode Virtual Interrupts
 322         Bitfield<0> VME; // Virtual-8086 Mode Extensions
 323     EndBitUnion(CR4)
 324
 325     BitUnion64(CR8)
 326         Bitfield<3, 0> TPR; // Task Priority Register
 327     EndBitUnion(CR4)
 328
 329     /**
 330      * Segment Selector
 331      */
 332     BitUnion64(SegSelector)
 333         Bitfield<15, 3> SI; // Selector Index
 334         Bitfield<2> TI; // Table Indicator
 335         Bitfield<1, 0> RPL; // Requestor Privilege Level
 336     EndBitUnion(SegSelector)
 337
 338     /**
 339      * Segment Descriptors
 340      */
 341
 342     BitUnion64(SegDescriptor)
 343         Bitfield<63, 56> baseHigh;
 344         Bitfield<39, 16> baseLow;
 345         Bitfield<55> G; // Granularity
 346         Bitfield<54> D; // Default Operand Size
 347         Bitfield<54> B; // Default Operand Size
 348         Bitfield<53> L; // Long Attribute Bit
 349         Bitfield<52> AVL; // Available To Software
 350         Bitfield<51, 48> limitHigh;
 351         Bitfield<15, 0> limitLow;
 352         Bitfield<47> P; // Present
 353         Bitfield<46, 45> DPL; // Descriptor Privilege-Level
 354         Bitfield<44> S; // System
 355         SubBitUnion(type, 43, 40)
 356             // Specifies whether this descriptor is for code or data.
 357             Bitfield<43> codeOrData;
 358
 359             // These bit fields are for code segments
 360             Bitfield<42> C; // Conforming
 361             Bitfield<41> R; // Readable
 362
 363             // These bit fields are for data segments
 364             Bitfield<42> E; // Expand-Down
 365             Bitfield<41> W; // Writable
 366
 367             // This is used for both code and data segments.
 368             Bitfield<40> A; // Accessed
 369         EndSubBitUnion(type)
 370     EndBitUnion(SegDescriptor)
 371
 372     BitUnion64(GateDescriptor)
 373         Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
 374         Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
 375         Bitfield<31, 16> selector; // Target Code-Segment Selector
 376         Bitfield<47> P; // Present
 377         Bitfield<46, 45> DPL; // Descriptor Privilege-Level
 378         Bitfield<43, 40> type;
 379         Bitfield<36, 32> count; // Parameter Count
 380     EndBitUnion(GateDescriptor)
 381
 382     /**
 383      * Descriptor-Table Registers
 384      */
 385     BitUnion64(GDTR)
 386     EndBitUnion(GDTR)
 387
 388     BitUnion64(IDTR)
 389     EndBitUnion(IDTR)
 390
 391     BitUnion64(LDTR)
 392     EndBitUnion(LDTR)
 393
 394     /**
 395      * Task Register
 396      */
 397     BitUnion64(TR)
 398     EndBitUnion(TR)
 399 };
 400
 401 #endif // __ARCH_X86_INTREGS_HH__