src/arch/x86/miscregs.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
   7  * following conditions are met:
   8  *
   9  * The software must be used only for Non-Commercial Use which means any
  10  * use which is NOT directed to receiving any direct monetary
  11  * compensation for, or commercial advantage from such use.  Illustrative
  12  * examples of non-commercial use are academic research, personal study,
  13  * teaching, education and corporate research & development.
  14  * Illustrative examples of commercial use are distributing products for
  15  * commercial advantage and providing services using the software for
  16  * commercial advantage.
  17  *
  18  * If you wish to use this software or functionality therein that may be
  19  * covered by patents for commercial use, please contact:
  20  *     Director of Intellectual Property Licensing
  21  *     Office of Strategy and Technology
  22  *     Hewlett-Packard Company
  23  *     1501 Page Mill Road
  24  *     Palo Alto, California  94304
  25  *
  26  * Redistributions of source code must retain the above copyright notice,
  27  * this list of conditions and the following disclaimer.  Redistributions
  28  * in binary form must reproduce the above copyright notice, this list of
  29  * conditions and the following disclaimer in the documentation and/or
  30  * other materials provided with the distribution.  Neither the name of
  31  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  32  * contributors may be used to endorse or promote products derived from
  33  * this software without specific prior written permission.  No right of
  34  * sublicense is granted herewith.  Derivatives of the software and
  35  * output created using the software may be prepared, but only for
  36  * Non-Commercial Uses.  Derivatives of the software may be shared with
  37  * others provided: (i) the others agree to abide by the list of
  38  * conditions herein which includes the Non-Commercial Use restrictions;
  39  * and (ii) such Derivatives of the software include the above copyright
  40  * notice to acknowledge the contribution from this software where
  41  * applicable, this list of conditions and the disclaimer below.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_MISCREGS_HH__
  59 #define __ARCH_X86_MISCREGS_HH__
  60
  61 #include "base/bitunion.hh"
  62
  63 namespace X86ISA
  64 {
  65     enum CondFlagBit {
  66         CFBit = 1 << 0,
  67         PFBit = 1 << 2,
  68         ECFBit = 1 << 3,
  69         AFBit = 1 << 4,
  70         EZFBit = 1 << 5,
  71         ZFBit = 1 << 6,
  72         SFBit = 1 << 7,
  73         OFBit = 1 << 11
  74     };
  75
  76     enum MiscRegIndex
  77     {
  78         // Control registers
  79         // Most of these are invalid.
  80         MISCREG_CR0,
  81         MISCREG_CR1,
  82         MISCREG_CR2,
  83         MISCREG_CR3,
  84         MISCREG_CR4,
  85         MISCREG_CR5,
  86         MISCREG_CR6,
  87         MISCREG_CR7,
  88         MISCREG_CR8,
  89         MISCREG_CR9,
  90         MISCREG_CR10,
  91         MISCREG_CR11,
  92         MISCREG_CR12,
  93         MISCREG_CR13,
  94         MISCREG_CR14,
  95         MISCREG_CR15,
  96
  97         // Debug registers
  98         MISCREG_DR0,
  99         MISCREG_DR1,
 100         MISCREG_DR2,
 101         MISCREG_DR3,
 102         MISCREG_DR4,
 103         MISCREG_DR5,
 104         MISCREG_DR6,
 105         MISCREG_DR7,
 106
 107         // Flags register
 108         MISCREG_RFLAGS,
 109
 110         // Segment selectors
 111         MISCREG_ES,
 112         MISCREG_CS,
 113         MISCREG_SS,
 114         MISCREG_DS,
 115         MISCREG_FS,
 116         MISCREG_GS,
 117
 118         // Hidden segment base field
 119         MISCREG_ES_BASE,
 120         MISCREG_CS_BASE,
 121         MISCREG_SS_BASE,
 122         MISCREG_DS_BASE,
 123         MISCREG_FS_BASE,
 124         MISCREG_GS_BASE,
 125
 126         // Hidden segment limit field
 127         MISCREG_ES_LIMIT,
 128         MISCREG_CS_LIMIT,
 129         MISCREG_SS_LIMIT,
 130         MISCREG_DS_LIMIT,
 131         MISCREG_FS_LIMIT,
 132         MISCREG_GS_LIMIT,
 133
 134         // Hidden segment limit attributes
 135         MISCREG_ES_ATTR,
 136         MISCREG_CS_ATTR,
 137         MISCREG_SS_ATTR,
 138         MISCREG_DS_ATTR,
 139         MISCREG_FS_ATTR,
 140         MISCREG_GS_ATTR,
 141
 142         // System segment selectors
 143         MISCREG_LDTR,
 144         MISCREG_TR,
 145
 146         // Hidden system segment base field
 147         MISCREG_LDTR_BASE,
 148         MISCREG_TR_BASE,
 149         MISCREG_GDTR_BASE,
 150         MISCREG_IDTR_BASE,
 151
 152         // Hidden system segment limit field
 153         MISCREG_LDTR_LIMIT,
 154         MISCREG_TR_LIMIT,
 155         MISCREG_GDTR_LIMIT,
 156         MISCREG_IDTR_LIMIT,
 157
 158         // Hidden system segment attribute field
 159         MISCREG_LDTR_ATTR,
 160         MISCREG_TR_ATTR,
 161
 162         //XXX Add "Model-Specific Registers"
 163
 164         NUM_MISCREGS
 165     };
 166
 167     /**
 168      * A type to describe the condition code bits of the RFLAGS register,
 169      * plus two flags, EZF and ECF, which are only visible to microcode.
 170      */
 171     BitUnion64(CCFlagBits)
 172         Bitfield<11> OF;
 173         Bitfield<7> SF;
 174         Bitfield<6> ZF;
 175         Bitfield<5> EZF;
 176         Bitfield<4> AF;
 177         Bitfield<3> ECF;
 178         Bitfield<2> PF;
 179         Bitfield<0> CF;
 180     EndBitUnion(CCFlagBits)
 181
 182     /**
 183      * RFLAGS
 184      */
 185     BitUnion64(RFLAGS)
 186         Bitfield<21> ID; // ID Flag
 187         Bitfield<20> VIP; // Virtual Interrupt Pending
 188         Bitfield<19> VIF; // Virtual Interrupt Flag
 189         Bitfield<18> AC; // Alignment Check
 190         Bitfield<17> VM; // Virtual-8086 Mode
 191         Bitfield<16> RF; // Resume Flag
 192         Bitfield<14> NT; // Nested Task
 193         Bitfield<13, 12> IOPL; // I/O Privilege Level
 194         Bitfield<11> OF; // Overflow Flag
 195         Bitfield<10> DF; // Direction Flag
 196         Bitfield<9> IF; // Interrupt Flag
 197         Bitfield<8> TF; // Trap Flag
 198         Bitfield<7> SF; // Sign Flag
 199         Bitfield<6> ZF; // Zero Flag
 200         Bitfield<4> AF; // Auxiliary Flag
 201         Bitfield<2> PF; // Parity Flag
 202         Bitfield<0> CF; // Carry Flag
 203     EndBitUnion(RFLAGS)
 204
 205     /**
 206      * Control registers
 207      */
 208     BitUnion64(CR0)
 209         Bitfield<31> PG; // Paging
 210         Bitfield<30> CD; // Cache Disable
 211         Bitfield<29> NW; // Not Writethrough
 212         Bitfield<18> AM; // Alignment Mask
 213         Bitfield<16> WP; // Write Protect
 214         Bitfield<5> NE; // Numeric Error
 215         Bitfield<4> ET; // Extension Type
 216         Bitfield<3> TS; // Task Switched
 217         Bitfield<2> EM; // Emulation
 218         Bitfield<1> MP; // Monitor Coprocessor
 219         Bitfield<0> PE; // Protection Enabled
 220     EndBitUnion(CR0)
 221
 222     // Page Fault Virtual Address
 223     BitUnion64(CR2)
 224         Bitfield<31, 0> legacy;
 225     EndBitUnion(CR2)
 226
 227     BitUnion64(CR3)
 228         Bitfield<51, 12> longPDTB; // Long Mode Page-Directory-Table
 229                                    // Base Address
 230         Bitfield<31, 12> PDTB; // Non-PAE Addressing Page-Directory-Table
 231                                // Base Address
 232         Bitfield<31, 5> PAEPDTB; // PAE Addressing Page-Directory-Table
 233                                  // Base Address
 234         Bitfield<4> PCD; // Page-Level Cache Disable
 235         Bitfield<3> PWT; // Page-Level Writethrough
 236     EndBitUnion(CR3)
 237
 238     BitUnion64(CR4)
 239         Bitfield<10> OSXMMEXCPT; // Operating System Unmasked
 240                                  // Exception Support
 241         Bitfield<9> OSFXSR; // Operating System FXSave/FSRSTOR Support
 242         Bitfield<8> PCE; // Performance-Monitoring Counter Enable
 243         Bitfield<7> PGE; // Page-Global Enable
 244         Bitfield<6> MCE; // Machine Check Enable
 245         Bitfield<5> PAE; // Physical-Address Extension
 246         Bitfield<4> PSE; // Page Size Extensions
 247         Bitfield<3> DE; // Debugging Extensions
 248         Bitfield<2> TSD; // Time Stamp Disable
 249         Bitfield<1> PVI; // Protected-Mode Virtual Interrupts
 250         Bitfield<0> VME; // Virtual-8086 Mode Extensions
 251     EndBitUnion(CR4)
 252
 253     BitUnion64(CR8)
 254         Bitfield<3, 0> TPR; // Task Priority Register
 255     EndBitUnion(CR4)
 256
 257     /**
 258      * Segment Selector
 259      */
 260     BitUnion64(SegSelector)
 261         Bitfield<15, 3> SI; // Selector Index
 262         Bitfield<2> TI; // Table Indicator
 263         Bitfield<1, 0> RPL; // Requestor Privilege Level
 264     EndBitUnion(SegSelector)
 265
 266     /**
 267      * Segment Descriptors
 268      */
 269
 270     BitUnion64(SegDescriptor)
 271         Bitfield<63, 56> baseHigh;
 272         Bitfield<39, 16> baseLow;
 273         Bitfield<55> G; // Granularity
 274         Bitfield<54> D; // Default Operand Size
 275         Bitfield<54> B; // Default Operand Size
 276         Bitfield<53> L; // Long Attribute Bit
 277         Bitfield<52> AVL; // Available To Software
 278         Bitfield<51, 48> limitHigh;
 279         Bitfield<15, 0> limitLow;
 280         Bitfield<47> P; // Present
 281         Bitfield<46, 45> DPL; // Descriptor Privilege-Level
 282         Bitfield<44> S; // System
 283         SubBitUnion(type, 43, 40)
 284             // Specifies whether this descriptor is for code or data.
 285             Bitfield<43> codeOrData;
 286
 287             // These bit fields are for code segments
 288             Bitfield<42> C; // Conforming
 289             Bitfield<41> R; // Readable
 290
 291             // These bit fields are for data segments
 292             Bitfield<42> E; // Expand-Down
 293             Bitfield<41> W; // Writable
 294
 295             // This is used for both code and data segments.
 296             Bitfield<40> A; // Accessed
 297         EndSubBitUnion(type)
 298     EndBitUnion(SegDescriptor)
 299
 300     BitUnion64(GateDescriptor)
 301         Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
 302         Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
 303         Bitfield<31, 16> selector; // Target Code-Segment Selector
 304         Bitfield<47> P; // Present
 305         Bitfield<46, 45> DPL; // Descriptor Privilege-Level
 306         Bitfield<43, 40> type;
 307         Bitfield<36, 32> count; // Parameter Count
 308     EndBitUnion(GateDescriptor)
 309
 310     /**
 311      * Descriptor-Table Registers
 312      */
 313     BitUnion64(GDTR)
 314     EndBitUnion(GDTR)
 315
 316     BitUnion64(IDTR)
 317     EndBitUnion(IDTR)
 318
 319     BitUnion64(LDTR)
 320     EndBitUnion(LDTR)
 321
 322     /**
 323      * Task Register
 324      */
 325     BitUnion64(TR)
 326     EndBitUnion(TR)
 327 };
 328
 329 #endif // __ARCH_X86_INTREGS_HH__