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40 #ifndef __ARCH_X86_MISCREGS_HH__
41 #define __ARCH_X86_MISCREGS_HH__
43 #include "arch/x86/segmentregs.hh"
44 #include "arch/x86/x86_traits.hh"
45 #include "base/bitunion.hh"
47 //These get defined in some system headers (at least termbits.h). That confuses
48 //things here significantly.
82 // Most of these are invalid.
84 MISCREG_CR0 = MISCREG_CR_BASE,
102 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
103 MISCREG_DR0 = MISCREG_DR_BASE,
113 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
115 //Register to keep handy values like the CPU mode in.
119 * Model Specific Registers
121 // Time stamp counter
127 MISCREG_SYSENTER_ESP,
128 MISCREG_SYSENTER_EIP,
134 MISCREG_DEBUG_CTL_MSR,
136 MISCREG_LAST_BRANCH_FROM_IP,
137 MISCREG_LAST_BRANCH_TO_IP,
138 MISCREG_LAST_EXCEPTION_FROM_IP,
139 MISCREG_LAST_EXCEPTION_TO_IP,
141 MISCREG_MTRR_PHYS_BASE_BASE,
142 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
143 MISCREG_MTRR_PHYS_BASE_1,
144 MISCREG_MTRR_PHYS_BASE_2,
145 MISCREG_MTRR_PHYS_BASE_3,
146 MISCREG_MTRR_PHYS_BASE_4,
147 MISCREG_MTRR_PHYS_BASE_5,
148 MISCREG_MTRR_PHYS_BASE_6,
149 MISCREG_MTRR_PHYS_BASE_7,
150 MISCREG_MTRR_PHYS_BASE_END,
152 MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END,
153 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
154 MISCREG_MTRR_PHYS_MASK_1,
155 MISCREG_MTRR_PHYS_MASK_2,
156 MISCREG_MTRR_PHYS_MASK_3,
157 MISCREG_MTRR_PHYS_MASK_4,
158 MISCREG_MTRR_PHYS_MASK_5,
159 MISCREG_MTRR_PHYS_MASK_6,
160 MISCREG_MTRR_PHYS_MASK_7,
161 MISCREG_MTRR_PHYS_MASK_END,
163 MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END,
164 MISCREG_MTRR_FIX_16K_80000,
165 MISCREG_MTRR_FIX_16K_A0000,
166 MISCREG_MTRR_FIX_4K_C0000,
167 MISCREG_MTRR_FIX_4K_C8000,
168 MISCREG_MTRR_FIX_4K_D0000,
169 MISCREG_MTRR_FIX_4K_D8000,
170 MISCREG_MTRR_FIX_4K_E0000,
171 MISCREG_MTRR_FIX_4K_E8000,
172 MISCREG_MTRR_FIX_4K_F0000,
173 MISCREG_MTRR_FIX_4K_F8000,
180 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
190 MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END,
191 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
199 MISCREG_MC_STATUS_END,
201 MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END,
202 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
212 MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END,
213 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
223 // Extended feature enable register
224 MISCREG_EFER = MISCREG_MC_MISC_END,
232 MISCREG_KERNEL_GS_BASE,
236 MISCREG_PERF_EVT_SEL_BASE,
237 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
238 MISCREG_PERF_EVT_SEL1,
239 MISCREG_PERF_EVT_SEL2,
240 MISCREG_PERF_EVT_SEL3,
241 MISCREG_PERF_EVT_SEL_END,
243 MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END,
244 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
245 MISCREG_PERF_EVT_CTR1,
246 MISCREG_PERF_EVT_CTR2,
247 MISCREG_PERF_EVT_CTR3,
248 MISCREG_PERF_EVT_CTR_END,
250 MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END,
252 MISCREG_IORR_BASE_BASE,
253 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
255 MISCREG_IORR_BASE_END,
257 MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END,
258 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
260 MISCREG_IORR_MASK_END,
262 MISCREG_TOP_MEM = MISCREG_IORR_MASK_END,
274 MISCREG_SEG_SEL_BASE,
275 MISCREG_ES = MISCREG_SEG_SEL_BASE,
289 // Hidden segment base field
290 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
291 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
305 // The effective segment base, ie what is actually added to an
306 // address. In 64 bit mode this can be different from the above,
308 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
309 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
316 MISCREG_TSL_EFF_BASE,
317 MISCREG_TSG_EFF_BASE,
321 MISCREG_IDTR_EFF_BASE,
323 // Hidden segment limit field
324 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
325 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
339 // Hidden segment limit attributes
340 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
341 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
355 // Floating point control registers
357 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
370 //XXX Add "Model-Specific Registers"
374 // "Fake" MSRs for internally implemented devices
375 MISCREG_PCI_CONFIG_ADDRESS,
380 static inline MiscRegIndex
381 MISCREG_CR(int index)
383 assert(index >= 0 && index < NumCRegs);
384 return (MiscRegIndex)(MISCREG_CR_BASE + index);
387 static inline MiscRegIndex
388 MISCREG_DR(int index)
390 assert(index >= 0 && index < NumDRegs);
391 return (MiscRegIndex)(MISCREG_DR_BASE + index);
394 static inline MiscRegIndex
395 MISCREG_MTRR_PHYS_BASE(int index)
397 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END -
398 MISCREG_MTRR_PHYS_BASE_BASE));
399 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
402 static inline MiscRegIndex
403 MISCREG_MTRR_PHYS_MASK(int index)
405 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END -
406 MISCREG_MTRR_PHYS_MASK_BASE));
407 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
410 static inline MiscRegIndex
411 MISCREG_MC_CTL(int index)
413 assert(index >= 0 && index < (MISCREG_MC_CTL_END -
414 MISCREG_MC_CTL_BASE));
415 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
418 static inline MiscRegIndex
419 MISCREG_MC_STATUS(int index)
421 assert(index >= 0 && index < (MISCREG_MC_STATUS_END -
422 MISCREG_MC_STATUS_BASE));
423 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
426 static inline MiscRegIndex
427 MISCREG_MC_ADDR(int index)
429 assert(index >= 0 && index < (MISCREG_MC_ADDR_END -
430 MISCREG_MC_ADDR_BASE));
431 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
434 static inline MiscRegIndex
435 MISCREG_MC_MISC(int index)
437 assert(index >= 0 && index < (MISCREG_MC_MISC_END -
438 MISCREG_MC_MISC_BASE));
439 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
442 static inline MiscRegIndex
443 MISCREG_PERF_EVT_SEL(int index)
445 assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END -
446 MISCREG_PERF_EVT_SEL_BASE));
447 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
450 static inline MiscRegIndex
451 MISCREG_PERF_EVT_CTR(int index)
453 assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END -
454 MISCREG_PERF_EVT_CTR_BASE));
455 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
458 static inline MiscRegIndex
459 MISCREG_IORR_BASE(int index)
461 assert(index >= 0 && index < (MISCREG_IORR_BASE_END -
462 MISCREG_IORR_BASE_BASE));
463 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
466 static inline MiscRegIndex
467 MISCREG_IORR_MASK(int index)
469 assert(index >= 0 && index < (MISCREG_IORR_MASK_END -
470 MISCREG_IORR_MASK_BASE));
471 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
474 static inline MiscRegIndex
475 MISCREG_SEG_SEL(int index)
477 assert(index >= 0 && index < NUM_SEGMENTREGS);
478 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
481 static inline MiscRegIndex
482 MISCREG_SEG_BASE(int index)
484 assert(index >= 0 && index < NUM_SEGMENTREGS);
485 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
488 static inline MiscRegIndex
489 MISCREG_SEG_EFF_BASE(int index)
491 assert(index >= 0 && index < NUM_SEGMENTREGS);
492 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
495 static inline MiscRegIndex
496 MISCREG_SEG_LIMIT(int index)
498 assert(index >= 0 && index < NUM_SEGMENTREGS);
499 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
502 static inline MiscRegIndex
503 MISCREG_SEG_ATTR(int index)
505 assert(index >= 0 && index < NUM_SEGMENTREGS);
506 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
510 * A type to describe the condition code bits of the RFLAGS register,
511 * plus two flags, EZF and ECF, which are only visible to microcode.
513 BitUnion64(CCFlagBits)
522 EndBitUnion(CCFlagBits)
528 Bitfield<21> id; // ID Flag
529 Bitfield<20> vip; // Virtual Interrupt Pending
530 Bitfield<19> vif; // Virtual Interrupt Flag
531 Bitfield<18> ac; // Alignment Check
532 Bitfield<17> vm; // Virtual-8086 Mode
533 Bitfield<16> rf; // Resume Flag
534 Bitfield<14> nt; // Nested Task
535 Bitfield<13, 12> iopl; // I/O Privilege Level
536 Bitfield<11> of; // Overflow Flag
537 Bitfield<10> df; // Direction Flag
538 Bitfield<9> intf; // Interrupt Flag
539 Bitfield<8> tf; // Trap Flag
540 Bitfield<7> sf; // Sign Flag
541 Bitfield<6> zf; // Zero Flag
542 Bitfield<4> af; // Auxiliary Flag
543 Bitfield<2> pf; // Parity Flag
544 Bitfield<0> cf; // Carry Flag
547 BitUnion64(HandyM5Reg)
549 Bitfield<3, 1> submode;
553 Bitfield<9, 8> defOp;
554 Bitfield<11, 10> altOp;
555 Bitfield<13, 12> defAddr;
556 Bitfield<15, 14> altAddr;
557 Bitfield<17, 16> stack;
558 EndBitUnion(HandyM5Reg)
564 Bitfield<31> pg; // Paging
565 Bitfield<30> cd; // Cache Disable
566 Bitfield<29> nw; // Not Writethrough
567 Bitfield<18> am; // Alignment Mask
568 Bitfield<16> wp; // Write Protect
569 Bitfield<5> ne; // Numeric Error
570 Bitfield<4> et; // Extension Type
571 Bitfield<3> ts; // Task Switched
572 Bitfield<2> em; // Emulation
573 Bitfield<1> mp; // Monitor Coprocessor
574 Bitfield<0> pe; // Protection Enabled
577 // Page Fault Virtual Address
579 Bitfield<31, 0> legacy;
583 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
585 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
587 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
589 Bitfield<4> pcd; // Page-Level Cache Disable
590 Bitfield<3> pwt; // Page-Level Writethrough
594 Bitfield<10> osxmmexcpt; // Operating System Unmasked
596 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
597 Bitfield<8> pce; // Performance-Monitoring Counter Enable
598 Bitfield<7> pge; // Page-Global Enable
599 Bitfield<6> mce; // Machine Check Enable
600 Bitfield<5> pae; // Physical-Address Extension
601 Bitfield<4> pse; // Page Size Extensions
602 Bitfield<3> de; // Debugging Extensions
603 Bitfield<2> tsd; // Time Stamp Disable
604 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
605 Bitfield<0> vme; // Virtual-8086 Mode Extensions
609 Bitfield<3, 0> tpr; // Task Priority Register
634 Bitfield<17, 16> rw0;
635 Bitfield<19, 18> len0;
636 Bitfield<21, 20> rw1;
637 Bitfield<23, 22> len1;
638 Bitfield<25, 24> rw2;
639 Bitfield<27, 26> len2;
640 Bitfield<29, 28> rw3;
641 Bitfield<31, 30> len3;
646 Bitfield<7, 0> vcnt; // Variable-Range Register Count
647 Bitfield<8> fix; // Fixed-Range Registers
648 Bitfield<10> wc; // Write-Combining
652 * SYSENTER configuration registers
654 BitUnion64(SysenterCS)
655 Bitfield<15, 0> targetCS;
656 EndBitUnion(SysenterCS)
658 BitUnion64(SysenterESP)
659 Bitfield<31, 0> targetESP;
660 EndBitUnion(SysenterESP)
662 BitUnion64(SysenterEIP)
663 Bitfield<31, 0> targetEIP;
664 EndBitUnion(SysenterEIP)
667 * Global machine check registers
670 Bitfield<7, 0> count; // Number of error reporting register banks
671 Bitfield<8> MCGCP; // MCG_CTL register present.
674 BitUnion64(McgStatus)
675 Bitfield<0> ripv; // Restart-IP valid
676 Bitfield<1> eipv; // Error-IP valid
677 Bitfield<2> mcip; // Machine check in-progress
678 EndBitUnion(McgStatus)
680 BitUnion64(DebugCtlMsr)
681 Bitfield<0> lbr; // Last-branch record
682 Bitfield<1> btf; // Branch single step
683 Bitfield<2> pb0; // Performance monitoring pin control 0
684 Bitfield<3> pb1; // Performance monitoring pin control 1
685 Bitfield<4> pb2; // Performance monitoring pin control 2
686 Bitfield<5> pb3; // Performance monitoring pin control 3
687 /*uint64_t pb(int index)
689 return bits(__data, index + 2);
691 EndBitUnion(DebugCtlMsr)
693 BitUnion64(MtrrPhysBase)
694 Bitfield<7, 0> type; // Default memory type
695 Bitfield<51, 12> physbase; // Range physical base address
696 EndBitUnion(MtrrPhysBase)
698 BitUnion64(MtrrPhysMask)
699 Bitfield<11> valid; // MTRR pair enable
700 Bitfield<51, 12> physmask; // Range physical mask
701 EndBitUnion(MtrrPhysMask)
703 BitUnion64(MtrrFixed)
704 /*uint64_t type(int index)
706 return bits(__data, index * 8 + 7, index * 8);
708 EndBitUnion(MtrrFixed)
711 /*uint64_t pa(int index)
713 return bits(__data, index * 8 + 2, index * 8);
717 BitUnion64(MtrrDefType)
718 Bitfield<7, 0> type; // Default type
719 Bitfield<10> fe; // Fixed range enable
720 Bitfield<11> e; // MTRR enable
721 EndBitUnion(MtrrDefType)
727 Bitfield<15,0> mcaErrorCode;
728 Bitfield<31,16> modelSpecificCode;
729 Bitfield<56,32> otherInfo;
730 Bitfield<57> pcc; // Processor-context corrupt
731 Bitfield<58> addrv; // Error-address register valid
732 Bitfield<59> miscv; // Miscellaneous-error register valid
733 Bitfield<60> en; // Error condition enabled
734 Bitfield<61> uc; // Uncorrected error
735 Bitfield<62> over; // Status register overflow
736 Bitfield<63> val; // Valid
737 EndBitUnion(McStatus)
740 /*uint64_t en(int index)
742 return bits(__data, index);
746 // Extended feature enable register
748 Bitfield<0> sce; // System call extensions
749 Bitfield<8> lme; // Long mode enable
750 Bitfield<10> lma; // Long mode active
751 Bitfield<11> nxe; // No-execute enable
752 Bitfield<12> svme; // Secure virtual machine enable
753 Bitfield<14> ffxsr; // Fast fxsave/fxrstor
757 Bitfield<31,0> targetEip;
758 Bitfield<47,32> syscallCsAndSs;
759 Bitfield<63,48> sysretCsAndSs;
766 BitUnion64(PerfEvtSel)
767 Bitfield<7,0> eventMask;
768 Bitfield<15,8> unitMask;
769 Bitfield<16> usr; // User mode
770 Bitfield<17> os; // Operating-system mode
771 Bitfield<18> e; // Edge detect
772 Bitfield<19> pc; // Pin control
773 Bitfield<20> intEn; // Interrupt enable
774 Bitfield<22> en; // Counter enable
775 Bitfield<23> inv; // Invert mask
776 Bitfield<31,24> counterMask;
777 EndBitUnion(PerfEvtSel)
780 Bitfield<18> mfde; // MtrrFixDramEn
781 Bitfield<19> mfdm; // MtrrFixDramModEn
782 Bitfield<20> mvdm; // MtrrVarDramEn
783 Bitfield<21> tom2; // MtrrTom2En
787 Bitfield<3> wr; // WrMem Enable
788 Bitfield<4> rd; // RdMem Enable
789 Bitfield<51,12> physbase; // Range physical base address
790 EndBitUnion(IorrBase)
793 Bitfield<11> v; // I/O register pair enable (valid)
794 Bitfield<51,12> physmask; // Range physical mask
795 EndBitUnion(IorrMask)
798 Bitfield<51,23> physAddr; // Top of memory physical address
809 EndBitUnion(IgnneMsr)
811 BitUnion64(SmmCtlMsr)
814 Bitfield<2> smiCycle;
816 Bitfield<4> rsmCycle;
817 EndBitUnion(SmmCtlMsr)
822 BitUnion64(SegSelector)
823 // The following bitfield is not defined in the ISA, but it's useful
824 // when checking selectors in larger data types to make sure they
826 Bitfield<63, 3> esi; // Extended selector
827 Bitfield<15, 3> si; // Selector Index
828 Bitfield<2> ti; // Table Indicator
829 Bitfield<1, 0> rpl; // Requestor Privilege Level
830 EndBitUnion(SegSelector)
833 * Segment Descriptors
836 BitUnion64(SegDescriptor)
837 Bitfield<63, 56> baseHigh;
838 Bitfield<39, 16> baseLow;
839 Bitfield<55> g; // Granularity
840 Bitfield<54> d; // Default Operand Size
841 Bitfield<54> b; // Default Operand Size
842 Bitfield<53> l; // Long Attribute Bit
843 Bitfield<52> avl; // Available To Software
844 Bitfield<51, 48> limitHigh;
845 Bitfield<15, 0> limitLow;
846 Bitfield<47> p; // Present
847 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
848 Bitfield<44> s; // System
849 SubBitUnion(type, 43, 40)
850 // Specifies whether this descriptor is for code or data.
851 Bitfield<43> codeOrData;
853 // These bit fields are for code segments
854 Bitfield<42> c; // Conforming
855 Bitfield<41> r; // Readable
857 // These bit fields are for data segments
858 Bitfield<42> e; // Expand-Down
859 Bitfield<41> w; // Writable
861 // This is used for both code and data segments.
862 Bitfield<40> a; // Accessed
864 EndBitUnion(SegDescriptor)
868 Bitfield<2> unusable;
869 Bitfield<3> defaultSize;
870 Bitfield<4> longMode;
872 Bitfield<6> granularity;
874 Bitfield<11, 8> type;
875 Bitfield<12> writable;
876 Bitfield<13> readable;
877 Bitfield<14> expandDown;
881 BitUnion64(GateDescriptor)
882 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
883 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
884 Bitfield<31, 16> selector; // Target Code-Segment Selector
885 Bitfield<47> p; // Present
886 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
887 Bitfield<43, 40> type;
888 Bitfield<36, 32> count; // Parameter Count
889 EndBitUnion(GateDescriptor)
892 * Descriptor-Table Registers
911 * Local APIC Base Register
913 BitUnion64(LocalApicBase)
914 Bitfield<51, 12> base;
917 EndBitUnion(LocalApicBase)
920 #endif // __ARCH_X86_INTREGS_HH__