src/arch/x86/miscregs.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
   7  * following conditions are met:
   8  *
   9  * The software must be used only for Non-Commercial Use which means any
  10  * use which is NOT directed to receiving any direct monetary
  11  * compensation for, or commercial advantage from such use.  Illustrative
  12  * examples of non-commercial use are academic research, personal study,
  13  * teaching, education and corporate research & development.
  14  * Illustrative examples of commercial use are distributing products for
  15  * commercial advantage and providing services using the software for
  16  * commercial advantage.
  17  *
  18  * If you wish to use this software or functionality therein that may be
  19  * covered by patents for commercial use, please contact:
  20  *     Director of Intellectual Property Licensing
  21  *     Office of Strategy and Technology
  22  *     Hewlett-Packard Company
  23  *     1501 Page Mill Road
  24  *     Palo Alto, California  94304
  25  *
  26  * Redistributions of source code must retain the above copyright notice,
  27  * this list of conditions and the following disclaimer.  Redistributions
  28  * in binary form must reproduce the above copyright notice, this list of
  29  * conditions and the following disclaimer in the documentation and/or
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  31  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  32  * contributors may be used to endorse or promote products derived from
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  35  * output created using the software may be prepared, but only for
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  38  * conditions herein which includes the Non-Commercial Use restrictions;
  39  * and (ii) such Derivatives of the software include the above copyright
  40  * notice to acknowledge the contribution from this software where
  41  * applicable, this list of conditions and the disclaimer below.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_MISCREGS_HH__
  59 #define __ARCH_X86_MISCREGS_HH__
  60
  61 #include "arch/x86/x86_traits.hh"
  62 #include "base/bitunion.hh"
  63
  64 //These get defined in some system headers (at least termbits.h). That confuses
  65 //things here significantly.
  66 #undef CR0
  67 #undef CR2
  68 #undef CR3
  69
  70 namespace X86ISA
  71 {
  72     enum CondFlagBit {
  73         CFBit = 1 << 0,
  74         PFBit = 1 << 2,
  75         ECFBit = 1 << 3,
  76         AFBit = 1 << 4,
  77         EZFBit = 1 << 5,
  78         ZFBit = 1 << 6,
  79         SFBit = 1 << 7,
  80         DFBit = 1 << 10,
  81         OFBit = 1 << 11
  82     };
  83
  84     enum MiscRegIndex
  85     {
  86         // Control registers
  87         // Most of these are invalid.
  88         MISCREG_CR_BASE,
  89         MISCREG_CR0 = MISCREG_CR_BASE,
  90         MISCREG_CR1,
  91         MISCREG_CR2,
  92         MISCREG_CR3,
  93         MISCREG_CR4,
  94         MISCREG_CR5,
  95         MISCREG_CR6,
  96         MISCREG_CR7,
  97         MISCREG_CR8,
  98         MISCREG_CR9,
  99         MISCREG_CR10,
 100         MISCREG_CR11,
 101         MISCREG_CR12,
 102         MISCREG_CR13,
 103         MISCREG_CR14,
 104         MISCREG_CR15,
 105
 106         // Debug registers
 107         MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
 108         MISCREG_DR0 = MISCREG_DR_BASE,
 109         MISCREG_DR1,
 110         MISCREG_DR2,
 111         MISCREG_DR3,
 112         MISCREG_DR4,
 113         MISCREG_DR5,
 114         MISCREG_DR6,
 115         MISCREG_DR7,
 116
 117         // Flags register
 118         MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
 119
 120         /*
 121          * Model Specific Registers
 122          */
 123         // Time stamp counter
 124         MISCREG_TSC,
 125
 126         MISCREG_MTRRCAP,
 127
 128         MISCREG_SYSENTER_CS,
 129         MISCREG_SYSENTER_ESP,
 130         MISCREG_SYSENTER_EIP,
 131
 132         MISCREG_MCG_CAP,
 133         MISCREG_MCG_STATUS,
 134         MISCREG_MCG_CTL,
 135
 136         MISCREG_DEBUG_CTL_MSR,
 137
 138         MISCREG_LAST_BRANCH_FROM_IP,
 139         MISCREG_LAST_BRANCH_TO_IP,
 140         MISCREG_LAST_EXCEPTION_FROM_IP,
 141         MISCREG_LAST_EXCEPTION_TO_IP,
 142
 143         MISCREG_MTRR_PHYS_BASE_BASE,
 144         MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
 145         MISCREG_MTRR_PHYS_BASE_1,
 146         MISCREG_MTRR_PHYS_BASE_2,
 147         MISCREG_MTRR_PHYS_BASE_3,
 148         MISCREG_MTRR_PHYS_BASE_4,
 149         MISCREG_MTRR_PHYS_BASE_5,
 150         MISCREG_MTRR_PHYS_BASE_6,
 151         MISCREG_MTRR_PHYS_BASE_7,
 152
 153         MISCREG_MTRR_PHYS_MASK_BASE,
 154         MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
 155         MISCREG_MTRR_PHYS_MASK_1,
 156         MISCREG_MTRR_PHYS_MASK_2,
 157         MISCREG_MTRR_PHYS_MASK_3,
 158         MISCREG_MTRR_PHYS_MASK_4,
 159         MISCREG_MTRR_PHYS_MASK_5,
 160         MISCREG_MTRR_PHYS_MASK_6,
 161         MISCREG_MTRR_PHYS_MASK_7,
 162
 163         MISCREG_MTRR_FIX_64K_00000,
 164         MISCREG_MTRR_FIX_16K_80000,
 165         MISCREG_MTRR_FIX_16K_A0000,
 166         MISCREG_MTRR_FIX_4K_C0000,
 167         MISCREG_MTRR_FIX_4K_C8000,
 168         MISCREG_MTRR_FIX_4K_D0000,
 169         MISCREG_MTRR_FIX_4K_D8000,
 170         MISCREG_MTRR_FIX_4K_E0000,
 171         MISCREG_MTRR_FIX_4K_E8000,
 172         MISCREG_MTRR_FIX_4K_F0000,
 173         MISCREG_MTRR_FIX_4K_F8000,
 174
 175         MISCREG_PAT,
 176
 177         MISCREG_DEF_TYPE,
 178
 179         MISCREG_MC_CTL_BASE,
 180         MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
 181         MISCREG_MC1_CTL,
 182         MISCREG_MC2_CTL,
 183         MISCREG_MC3_CTL,
 184         MISCREG_MC4_CTL,
 185
 186         MISCREG_MC_STATUS_BASE,
 187         MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
 188         MISCREG_MC1_STATUS,
 189         MISCREG_MC2_STATUS,
 190         MISCREG_MC3_STATUS,
 191         MISCREG_MC4_STATUS,
 192
 193         MISCREG_MC_ADDR_BASE,
 194         MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
 195         MISCREG_MC1_ADDR,
 196         MISCREG_MC2_ADDR,
 197         MISCREG_MC3_ADDR,
 198         MISCREG_MC4_ADDR,
 199
 200         MISCREG_MC_MISC_BASE,
 201         MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
 202         MISCREG_MC1_MISC,
 203         MISCREG_MC2_MISC,
 204         MISCREG_MC3_MISC,
 205         MISCREG_MC4_MISC,
 206
 207         // Extended feature enable register
 208         MISCREG_EFER,
 209
 210         MISCREG_STAR,
 211         MISCREG_LSTAR,
 212         MISCREG_CSTAR,
 213
 214         MISCREG_SF_MASK,
 215
 216         MISCREG_KERNEL_GS_BASE,
 217
 218         MISCREG_TSC_AUX,
 219
 220         MISCREG_PERF_EVT_SEL_BASE,
 221         MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
 222         MISCREG_PERF_EVT_SEL1,
 223         MISCREG_PERF_EVT_SEL2,
 224         MISCREG_PERF_EVT_SEL3,
 225
 226         MISCREG_PERF_EVT_CTR_BASE,
 227         MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
 228         MISCREG_PERF_EVT_CTR1,
 229         MISCREG_PERF_EVT_CTR2,
 230         MISCREG_PERF_EVT_CTR3,
 231
 232         MISCREG_SYSCFG,
 233
 234         MISCREG_IORR_BASE_BASE,
 235         MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
 236         MISCREG_IORR_BASE1,
 237
 238         MISCREG_IORR_MASK_BASE,
 239         MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
 240         MISCREG_IORR_MASK1,
 241
 242         MISCREG_TOP_MEM,
 243         MISCREG_TOP_MEM2,
 244
 245         MISCREG_VM_CR,
 246         MISCREG_IGNNE,
 247         MISCREG_SMM_CTL,
 248         MISCREG_VM_HSAVE_PA,
 249
 250         /*
 251          * Segment registers
 252          */
 253         // Segment selectors
 254         MISCREG_SEG_SEL_BASE,
 255         MISCREG_ES = MISCREG_SEG_SEL_BASE,
 256         MISCREG_CS,
 257         MISCREG_SS,
 258         MISCREG_DS,
 259         MISCREG_FS,
 260         MISCREG_GS,
 261         MISCREG_INT, // This isn't actually used.
 262
 263         // Hidden segment base field
 264         MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
 265         MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
 266         MISCREG_CS_BASE,
 267         MISCREG_SS_BASE,
 268         MISCREG_DS_BASE,
 269         MISCREG_FS_BASE,
 270         MISCREG_GS_BASE,
 271         MISCREG_INT_BASE,
 272
 273         // The effective segment base, ie what is actually added to an
 274         // address. In 64 bit mode this can be different from the above,
 275         // namely 0.
 276         MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
 277         MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
 278         MISCREG_CS_EFF_BASE,
 279         MISCREG_SS_EFF_BASE,
 280         MISCREG_DS_EFF_BASE,
 281         MISCREG_FS_EFF_BASE,
 282         MISCREG_GS_EFF_BASE,
 283         MISCREG_INT_EFF_BASE,
 284
 285         // Hidden segment limit field
 286         MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NumSegments,
 287         MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
 288         MISCREG_CS_LIMIT,
 289         MISCREG_SS_LIMIT,
 290         MISCREG_DS_LIMIT,
 291         MISCREG_FS_LIMIT,
 292         MISCREG_GS_LIMIT,
 293         MISCREG_INT_LIMIT, // This isn't actually used.
 294
 295         // Hidden segment limit attributes
 296         MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
 297         MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
 298         MISCREG_CS_ATTR,
 299         MISCREG_SS_ATTR,
 300         MISCREG_DS_ATTR,
 301         MISCREG_FS_ATTR,
 302         MISCREG_GS_ATTR,
 303         MISCREG_INT_ATTR, // This isn't actually used.
 304
 305         // System segment selectors
 306         MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
 307         MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
 308         MISCREG_TR,
 309
 310         // Hidden system segment base field
 311         MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
 312         MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
 313         MISCREG_TR_BASE,
 314         MISCREG_GDTR_BASE,
 315         MISCREG_IDTR_BASE,
 316
 317         // Hidden system segment limit field
 318         MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
 319         MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
 320         MISCREG_TR_LIMIT,
 321         MISCREG_GDTR_LIMIT,
 322         MISCREG_IDTR_LIMIT,
 323
 324         // Hidden system segment attribute field
 325         MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
 326         MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
 327         MISCREG_TR_ATTR,
 328
 329         // Floating point control registers
 330         MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments,
 331
 332         //XXX Add "Model-Specific Registers"
 333
 334         NUM_MISCREGS
 335     };
 336
 337     static inline MiscRegIndex
 338     MISCREG_CR(int index)
 339     {
 340         return (MiscRegIndex)(MISCREG_CR_BASE + index);
 341     }
 342
 343     static inline MiscRegIndex
 344     MISCREG_DR(int index)
 345     {
 346         return (MiscRegIndex)(MISCREG_DR_BASE + index);
 347     }
 348
 349     static inline MiscRegIndex
 350     MISCREG_MTRR_PHYS_BASE(int index)
 351     {
 352         return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
 353     }
 354
 355     static inline MiscRegIndex
 356     MISCREG_MTRR_PHYS_MASK(int index)
 357     {
 358         return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
 359     }
 360
 361     static inline MiscRegIndex
 362     MISCREG_MC_CTL(int index)
 363     {
 364         return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
 365     }
 366
 367     static inline MiscRegIndex
 368     MISCREG_MC_STATUS(int index)
 369     {
 370         return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
 371     }
 372
 373     static inline MiscRegIndex
 374     MISCREG_MC_ADDR(int index)
 375     {
 376         return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
 377     }
 378
 379     static inline MiscRegIndex
 380     MISCREG_MC_MISC(int index)
 381     {
 382         return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
 383     }
 384
 385     static inline MiscRegIndex
 386     MISCREG_PERF_EVT_SEL(int index)
 387     {
 388         return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
 389     }
 390
 391     static inline MiscRegIndex
 392     MISCREG_PERF_EVT_CTR(int index)
 393     {
 394         return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
 395     }
 396
 397     static inline MiscRegIndex
 398     MISCREG_IORR_BASE(int index)
 399     {
 400         return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
 401     }
 402
 403     static inline MiscRegIndex
 404     MISCREG_IORR_MASK(int index)
 405     {
 406         return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
 407     }
 408
 409     static inline MiscRegIndex
 410     MISCREG_SEG_SEL(int index)
 411     {
 412         return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
 413     }
 414
 415     static inline MiscRegIndex
 416     MISCREG_SEG_BASE(int index)
 417     {
 418         return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
 419     }
 420
 421     static inline MiscRegIndex
 422     MISCREG_SEG_EFF_BASE(int index)
 423     {
 424         return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
 425     }
 426
 427     static inline MiscRegIndex
 428     MISCREG_SEG_LIMIT(int index)
 429     {
 430         return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
 431     }
 432
 433     static inline MiscRegIndex
 434     MISCREG_SEG_ATTR(int index)
 435     {
 436         return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
 437     }
 438
 439     static inline MiscRegIndex
 440     MISCREG_SYSSEG_SEL(int index)
 441     {
 442         return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
 443     }
 444
 445     static inline MiscRegIndex
 446     MISCREG_SYSSEG_BASE(int index)
 447     {
 448         return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
 449     }
 450
 451     static inline MiscRegIndex
 452     MISCREG_SYSSEG_LIMIT(int index)
 453     {
 454         return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
 455     }
 456
 457     static inline MiscRegIndex
 458     MISCREG_SYSSEG_ATTR(int index)
 459     {
 460         return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
 461     }
 462
 463     /**
 464      * A type to describe the condition code bits of the RFLAGS register,
 465      * plus two flags, EZF and ECF, which are only visible to microcode.
 466      */
 467     BitUnion64(CCFlagBits)
 468         Bitfield<11> of;
 469         Bitfield<7> sf;
 470         Bitfield<6> zf;
 471         Bitfield<5> ezf;
 472         Bitfield<4> af;
 473         Bitfield<3> ecf;
 474         Bitfield<2> pf;
 475         Bitfield<0> cf;
 476     EndBitUnion(CCFlagBits)
 477
 478     /**
 479      * RFLAGS
 480      */
 481     BitUnion64(RFLAGS)
 482         Bitfield<21> id; // ID Flag
 483         Bitfield<20> vip; // Virtual Interrupt Pending
 484         Bitfield<19> vif; // Virtual Interrupt Flag
 485         Bitfield<18> ac; // Alignment Check
 486         Bitfield<17> vm; // Virtual-8086 Mode
 487         Bitfield<16> rf; // Resume Flag
 488         Bitfield<14> nt; // Nested Task
 489         Bitfield<13, 12> iopl; // I/O Privilege Level
 490         Bitfield<11> of; // Overflow Flag
 491         Bitfield<10> df; // Direction Flag
 492         Bitfield<9> intf; // Interrupt Flag
 493         Bitfield<8> tf; // Trap Flag
 494         Bitfield<7> sf; // Sign Flag
 495         Bitfield<6> zf; // Zero Flag
 496         Bitfield<4> af; // Auxiliary Flag
 497         Bitfield<2> pf; // Parity Flag
 498         Bitfield<0> cf; // Carry Flag
 499     EndBitUnion(RFLAGS)
 500
 501     /**
 502      * Control registers
 503      */
 504     BitUnion64(CR0)
 505         Bitfield<31> pg; // Paging
 506         Bitfield<30> cd; // Cache Disable
 507         Bitfield<29> nw; // Not Writethrough
 508         Bitfield<18> am; // Alignment Mask
 509         Bitfield<16> wp; // Write Protect
 510         Bitfield<5> ne; // Numeric Error
 511         Bitfield<4> et; // Extension Type
 512         Bitfield<3> ts; // Task Switched
 513         Bitfield<2> em; // Emulation
 514         Bitfield<1> mp; // Monitor Coprocessor
 515         Bitfield<0> pe; // Protection Enabled
 516     EndBitUnion(CR0)
 517
 518     // Page Fault Virtual Address
 519     BitUnion64(CR2)
 520         Bitfield<31, 0> legacy;
 521     EndBitUnion(CR2)
 522
 523     BitUnion64(CR3)
 524         Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
 525                                    // Base Address
 526         Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
 527                                // Base Address
 528         Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
 529                                  // Base Address
 530         Bitfield<4> pcd; // Page-Level Cache Disable
 531         Bitfield<3> pwt; // Page-Level Writethrough
 532     EndBitUnion(CR3)
 533
 534     BitUnion64(CR4)
 535         Bitfield<10> osxmmexcpt; // Operating System Unmasked
 536                                  // Exception Support
 537         Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
 538         Bitfield<8> pce; // Performance-Monitoring Counter Enable
 539         Bitfield<7> pge; // Page-Global Enable
 540         Bitfield<6> mce; // Machine Check Enable
 541         Bitfield<5> pae; // Physical-Address Extension
 542         Bitfield<4> pse; // Page Size Extensions
 543         Bitfield<3> de; // Debugging Extensions
 544         Bitfield<2> tsd; // Time Stamp Disable
 545         Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
 546         Bitfield<0> vme; // Virtual-8086 Mode Extensions
 547     EndBitUnion(CR4)
 548
 549     BitUnion64(CR8)
 550         Bitfield<3, 0> tpr; // Task Priority Register
 551     EndBitUnion(CR8)
 552
 553     // MTRR capabilities
 554     BitUnion64(MTRRcap)
 555         Bitfield<7, 0> vcnt; // Variable-Range Register Count
 556         Bitfield<8> fix; // Fixed-Range Registers
 557         Bitfield<10> wc; // Write-Combining
 558     EndBitUnion(MTRRcap)
 559
 560     /**
 561      * SYSENTER configuration registers
 562      */
 563     BitUnion64(SysenterCS)
 564         Bitfield<15, 0> targetCS;
 565     EndBitUnion(SysenterCS)
 566
 567     BitUnion64(SysenterESP)
 568         Bitfield<31, 0> targetESP;
 569     EndBitUnion(SysenterESP)
 570
 571     BitUnion64(SysenterEIP)
 572         Bitfield<31, 0> targetEIP;
 573     EndBitUnion(SysenterEIP)
 574
 575     /**
 576      * Global machine check registers
 577      */
 578     BitUnion64(McgCap)
 579         Bitfield<7, 0> count; // Number of error reporting register banks
 580         Bitfield<8> MCGCP; // MCG_CTL register present.
 581     EndBitUnion(McgCap)
 582
 583     BitUnion64(McgStatus)
 584         Bitfield<0> ripv; // Restart-IP valid
 585         Bitfield<1> eipv; // Error-IP valid
 586         Bitfield<2> mcip; // Machine check in-progress
 587     EndBitUnion(McgStatus)
 588
 589     BitUnion64(DebugCtlMsr)
 590         Bitfield<0> lbr; // Last-branch record
 591         Bitfield<1> btf; // Branch single step
 592         Bitfield<2> pb0; // Performance monitoring pin control 0
 593         Bitfield<3> pb1; // Performance monitoring pin control 1
 594         Bitfield<4> pb2; // Performance monitoring pin control 2
 595         Bitfield<5> pb3; // Performance monitoring pin control 3
 596         /*uint64_t pb(int index)
 597         {
 598             return bits(__data, index + 2);
 599         }*/
 600     EndBitUnion(DebugCtlMsr)
 601
 602     BitUnion64(MtrrPhysBase)
 603         Bitfield<7, 0> type; // Default memory type
 604         Bitfield<51, 12> physbase; // Range physical base address
 605     EndBitUnion(MtrrPhysBase)
 606
 607     BitUnion64(MtrrPhysMask)
 608         Bitfield<11> valid; // MTRR pair enable
 609         Bitfield<51, 12> physmask; // Range physical mask
 610     EndBitUnion(MtrrPhysMask)
 611
 612     BitUnion64(MtrrFixed)
 613         /*uint64_t type(int index)
 614         {
 615             return bits(__data, index * 8 + 7, index * 8);
 616         }*/
 617     EndBitUnion(MtrrFixed)
 618
 619     BitUnion64(Pat)
 620         /*uint64_t pa(int index)
 621         {
 622             return bits(__data, index * 8 + 2, index * 8);
 623         }*/
 624     EndBitUnion(Pat)
 625
 626     BitUnion64(MtrrDefType)
 627         Bitfield<7, 0> type; // Default type
 628         Bitfield<10> fe; // Fixed range enable
 629         Bitfield<11> e; // MTRR enable
 630     EndBitUnion(MtrrDefType)
 631
 632     /**
 633      * Machine check
 634      */
 635     BitUnion64(McStatus)
 636         Bitfield<15,0> mcaErrorCode;
 637         Bitfield<31,16> modelSpecificCode;
 638         Bitfield<56,32> otherInfo;
 639         Bitfield<57> pcc; // Processor-context corrupt
 640         Bitfield<58> addrv; // Error-address register valid
 641         Bitfield<59> miscv; // Miscellaneous-error register valid
 642         Bitfield<60> en; // Error condition enabled
 643         Bitfield<61> uc; // Uncorrected error
 644         Bitfield<62> over; // Status register overflow
 645         Bitfield<63> val; // Valid
 646     EndBitUnion(McStatus)
 647
 648     BitUnion64(McCtl)
 649         /*uint64_t en(int index)
 650         {
 651             return bits(__data, index);
 652         }*/
 653     EndBitUnion(McCtl)
 654
 655     // Extended feature enable register
 656     BitUnion64(Efer)
 657         Bitfield<0> sce; // System call extensions
 658         Bitfield<8> lme; // Long mode enable
 659         Bitfield<10> lma; // Long mode active
 660         Bitfield<11> nxe; // No-execute enable
 661         Bitfield<12> svme; // Secure virtual machine enable
 662         Bitfield<14> ffxsr; // Fast fxsave/fxrstor
 663     EndBitUnion(Efer)
 664
 665     BitUnion64(Star)
 666         Bitfield<31,0> targetEip;
 667         Bitfield<47,32> syscallCsAndSs;
 668         Bitfield<63,48> sysretCsAndSs;
 669     EndBitUnion(Star)
 670
 671     BitUnion64(SfMask)
 672         Bitfield<31,0> mask;
 673     EndBitUnion(SfMask)
 674
 675     BitUnion64(PerfEvtSel)
 676         Bitfield<7,0> eventMask;
 677         Bitfield<15,8> unitMask;
 678         Bitfield<16> usr; // User mode
 679         Bitfield<17> os; // Operating-system mode
 680         Bitfield<18> e; // Edge detect
 681         Bitfield<19> pc; // Pin control
 682         Bitfield<20> intEn; // Interrupt enable
 683         Bitfield<22> en; // Counter enable
 684         Bitfield<23> inv; // Invert mask
 685         Bitfield<31,24> counterMask;
 686     EndBitUnion(PerfEvtSel)
 687
 688     BitUnion32(Syscfg)
 689         Bitfield<18> mfde; // MtrrFixDramEn
 690         Bitfield<19> mfdm; // MtrrFixDramModEn
 691         Bitfield<20> mvdm; // MtrrVarDramEn
 692         Bitfield<21> tom2; // MtrrTom2En
 693     EndBitUnion(Syscfg)
 694
 695     BitUnion64(IorrBase)
 696         Bitfield<3> wr; // WrMem Enable
 697         Bitfield<4> rd; // RdMem Enable
 698         Bitfield<51,12> physbase; // Range physical base address
 699     EndBitUnion(IorrBase)
 700
 701     BitUnion64(IorrMask)
 702         Bitfield<11> v; // I/O register pair enable (valid)
 703         Bitfield<51,12> physmask; // Range physical mask
 704     EndBitUnion(IorrMask)
 705
 706     BitUnion64(Tom)
 707         Bitfield<51,23> physAddr; // Top of memory physical address
 708     EndBitUnion(Tom)
 709
 710     BitUnion64(VmCrMsr)
 711         Bitfield<0> dpd;
 712         Bitfield<1> rInit;
 713         Bitfield<2> disA20M;
 714     EndBitUnion(VmCrMsr)
 715
 716     BitUnion64(IgnneMsr)
 717         Bitfield<0> ignne;
 718     EndBitUnion(IgnneMsr)
 719
 720     BitUnion64(SmmCtlMsr)
 721         Bitfield<0> dismiss;
 722         Bitfield<1> enter;
 723         Bitfield<2> smiCycle;
 724         Bitfield<3> exit;
 725         Bitfield<4> rsmCycle;
 726     EndBitUnion(SmmCtlMsr)
 727
 728     /**
 729      * Segment Selector
 730      */
 731     BitUnion64(SegSelector)
 732         Bitfield<15, 3> si; // Selector Index
 733         Bitfield<2> ti; // Table Indicator
 734         Bitfield<1, 0> rpl; // Requestor Privilege Level
 735     EndBitUnion(SegSelector)
 736
 737     /**
 738      * Segment Descriptors
 739      */
 740
 741     BitUnion64(SegDescriptor)
 742         Bitfield<63, 56> baseHigh;
 743         Bitfield<39, 16> baseLow;
 744         Bitfield<55> g; // Granularity
 745         Bitfield<54> d; // Default Operand Size
 746         Bitfield<54> b; // Default Operand Size
 747         Bitfield<53> l; // Long Attribute Bit
 748         Bitfield<52> avl; // Available To Software
 749         Bitfield<51, 48> limitHigh;
 750         Bitfield<15, 0> limitLow;
 751         Bitfield<47> p; // Present
 752         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 753         Bitfield<44> s; // System
 754         SubBitUnion(type, 43, 40)
 755             // Specifies whether this descriptor is for code or data.
 756             Bitfield<43> codeOrData;
 757
 758             // These bit fields are for code segments
 759             Bitfield<42> c; // Conforming
 760             Bitfield<41> r; // Readable
 761
 762             // These bit fields are for data segments
 763             Bitfield<42> e; // Expand-Down
 764             Bitfield<41> w; // Writable
 765
 766             // This is used for both code and data segments.
 767             Bitfield<40> a; // Accessed
 768         EndSubBitUnion(type)
 769     EndBitUnion(SegDescriptor)
 770
 771     BitUnion64(SegAttr)
 772         Bitfield<0> writable;
 773         Bitfield<1> readable;
 774         Bitfield<2> expandDown;
 775         Bitfield<4, 3> dpl;
 776         Bitfield<5> defaultSize;
 777         Bitfield<6> longMode;
 778     EndBitUnion(SegAttr)
 779
 780     BitUnion64(GateDescriptor)
 781         Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
 782         Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
 783         Bitfield<31, 16> selector; // Target Code-Segment Selector
 784         Bitfield<47> p; // Present
 785         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 786         Bitfield<43, 40> type;
 787         Bitfield<36, 32> count; // Parameter Count
 788     EndBitUnion(GateDescriptor)
 789
 790     /**
 791      * Descriptor-Table Registers
 792      */
 793     BitUnion64(GDTR)
 794     EndBitUnion(GDTR)
 795
 796     BitUnion64(IDTR)
 797     EndBitUnion(IDTR)
 798
 799     BitUnion64(LDTR)
 800     EndBitUnion(LDTR)
 801
 802     /**
 803      * Task Register
 804      */
 805     BitUnion64(TR)
 806     EndBitUnion(TR)
 807 };
 808
 809 #endif // __ARCH_X86_INTREGS_HH__