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58 #ifndef __ARCH_X86_MISCREGS_HH__
59 #define __ARCH_X86_MISCREGS_HH__
61 #include "arch/x86/segmentregs.hh"
62 #include "arch/x86/x86_traits.hh"
63 #include "base/bitunion.hh"
65 //These get defined in some system headers (at least termbits.h). That confuses
66 //things here significantly.
100 // Most of these are invalid.
102 MISCREG_CR0 = MISCREG_CR_BASE,
120 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
121 MISCREG_DR0 = MISCREG_DR_BASE,
131 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
133 //Register to keep handy values like the CPU mode in.
137 * Model Specific Registers
139 // Time stamp counter
145 MISCREG_SYSENTER_ESP,
146 MISCREG_SYSENTER_EIP,
152 MISCREG_DEBUG_CTL_MSR,
154 MISCREG_LAST_BRANCH_FROM_IP,
155 MISCREG_LAST_BRANCH_TO_IP,
156 MISCREG_LAST_EXCEPTION_FROM_IP,
157 MISCREG_LAST_EXCEPTION_TO_IP,
159 MISCREG_MTRR_PHYS_BASE_BASE,
160 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
161 MISCREG_MTRR_PHYS_BASE_1,
162 MISCREG_MTRR_PHYS_BASE_2,
163 MISCREG_MTRR_PHYS_BASE_3,
164 MISCREG_MTRR_PHYS_BASE_4,
165 MISCREG_MTRR_PHYS_BASE_5,
166 MISCREG_MTRR_PHYS_BASE_6,
167 MISCREG_MTRR_PHYS_BASE_7,
169 MISCREG_MTRR_PHYS_MASK_BASE,
170 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
171 MISCREG_MTRR_PHYS_MASK_1,
172 MISCREG_MTRR_PHYS_MASK_2,
173 MISCREG_MTRR_PHYS_MASK_3,
174 MISCREG_MTRR_PHYS_MASK_4,
175 MISCREG_MTRR_PHYS_MASK_5,
176 MISCREG_MTRR_PHYS_MASK_6,
177 MISCREG_MTRR_PHYS_MASK_7,
179 MISCREG_MTRR_FIX_64K_00000,
180 MISCREG_MTRR_FIX_16K_80000,
181 MISCREG_MTRR_FIX_16K_A0000,
182 MISCREG_MTRR_FIX_4K_C0000,
183 MISCREG_MTRR_FIX_4K_C8000,
184 MISCREG_MTRR_FIX_4K_D0000,
185 MISCREG_MTRR_FIX_4K_D8000,
186 MISCREG_MTRR_FIX_4K_E0000,
187 MISCREG_MTRR_FIX_4K_E8000,
188 MISCREG_MTRR_FIX_4K_F0000,
189 MISCREG_MTRR_FIX_4K_F8000,
196 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
205 MISCREG_MC_STATUS_BASE,
206 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
215 MISCREG_MC_ADDR_BASE,
216 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
225 MISCREG_MC_MISC_BASE,
226 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
235 // Extended feature enable register
244 MISCREG_KERNEL_GS_BASE,
248 MISCREG_PERF_EVT_SEL_BASE,
249 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
250 MISCREG_PERF_EVT_SEL1,
251 MISCREG_PERF_EVT_SEL2,
252 MISCREG_PERF_EVT_SEL3,
254 MISCREG_PERF_EVT_CTR_BASE,
255 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
256 MISCREG_PERF_EVT_CTR1,
257 MISCREG_PERF_EVT_CTR2,
258 MISCREG_PERF_EVT_CTR3,
262 MISCREG_IORR_BASE_BASE,
263 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
266 MISCREG_IORR_MASK_BASE,
267 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
282 MISCREG_SEG_SEL_BASE,
283 MISCREG_ES = MISCREG_SEG_SEL_BASE,
297 // Hidden segment base field
298 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
299 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
313 // The effective segment base, ie what is actually added to an
314 // address. In 64 bit mode this can be different from the above,
316 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
317 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
324 MISCREG_TSL_EFF_BASE,
325 MISCREG_TSG_EFF_BASE,
329 MISCREG_IDTR_EFF_BASE,
331 // Hidden segment limit field
332 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
333 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
347 // Hidden segment limit attributes
348 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
349 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
363 // Floating point control registers
365 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
367 //XXX Add "Model-Specific Registers"
371 // "Fake" MSRs for internally implemented devices
372 MISCREG_PCI_CONFIG_ADDRESS,
377 static inline MiscRegIndex
378 MISCREG_CR(int index)
380 return (MiscRegIndex)(MISCREG_CR_BASE + index);
383 static inline MiscRegIndex
384 MISCREG_DR(int index)
386 return (MiscRegIndex)(MISCREG_DR_BASE + index);
389 static inline MiscRegIndex
390 MISCREG_MTRR_PHYS_BASE(int index)
392 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
395 static inline MiscRegIndex
396 MISCREG_MTRR_PHYS_MASK(int index)
398 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
401 static inline MiscRegIndex
402 MISCREG_MC_CTL(int index)
404 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
407 static inline MiscRegIndex
408 MISCREG_MC_STATUS(int index)
410 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
413 static inline MiscRegIndex
414 MISCREG_MC_ADDR(int index)
416 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
419 static inline MiscRegIndex
420 MISCREG_MC_MISC(int index)
422 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
425 static inline MiscRegIndex
426 MISCREG_PERF_EVT_SEL(int index)
428 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
431 static inline MiscRegIndex
432 MISCREG_PERF_EVT_CTR(int index)
434 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
437 static inline MiscRegIndex
438 MISCREG_IORR_BASE(int index)
440 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
443 static inline MiscRegIndex
444 MISCREG_IORR_MASK(int index)
446 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
449 static inline MiscRegIndex
450 MISCREG_SEG_SEL(int index)
452 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
455 static inline MiscRegIndex
456 MISCREG_SEG_BASE(int index)
458 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
461 static inline MiscRegIndex
462 MISCREG_SEG_EFF_BASE(int index)
464 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
467 static inline MiscRegIndex
468 MISCREG_SEG_LIMIT(int index)
470 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
473 static inline MiscRegIndex
474 MISCREG_SEG_ATTR(int index)
476 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
480 * A type to describe the condition code bits of the RFLAGS register,
481 * plus two flags, EZF and ECF, which are only visible to microcode.
483 BitUnion64(CCFlagBits)
492 EndBitUnion(CCFlagBits)
498 Bitfield<21> id; // ID Flag
499 Bitfield<20> vip; // Virtual Interrupt Pending
500 Bitfield<19> vif; // Virtual Interrupt Flag
501 Bitfield<18> ac; // Alignment Check
502 Bitfield<17> vm; // Virtual-8086 Mode
503 Bitfield<16> rf; // Resume Flag
504 Bitfield<14> nt; // Nested Task
505 Bitfield<13, 12> iopl; // I/O Privilege Level
506 Bitfield<11> of; // Overflow Flag
507 Bitfield<10> df; // Direction Flag
508 Bitfield<9> intf; // Interrupt Flag
509 Bitfield<8> tf; // Trap Flag
510 Bitfield<7> sf; // Sign Flag
511 Bitfield<6> zf; // Zero Flag
512 Bitfield<4> af; // Auxiliary Flag
513 Bitfield<2> pf; // Parity Flag
514 Bitfield<0> cf; // Carry Flag
517 BitUnion64(HandyM5Reg)
519 Bitfield<3, 1> submode;
521 EndBitUnion(HandyM5Reg)
527 Bitfield<31> pg; // Paging
528 Bitfield<30> cd; // Cache Disable
529 Bitfield<29> nw; // Not Writethrough
530 Bitfield<18> am; // Alignment Mask
531 Bitfield<16> wp; // Write Protect
532 Bitfield<5> ne; // Numeric Error
533 Bitfield<4> et; // Extension Type
534 Bitfield<3> ts; // Task Switched
535 Bitfield<2> em; // Emulation
536 Bitfield<1> mp; // Monitor Coprocessor
537 Bitfield<0> pe; // Protection Enabled
540 // Page Fault Virtual Address
542 Bitfield<31, 0> legacy;
546 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
548 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
550 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
552 Bitfield<4> pcd; // Page-Level Cache Disable
553 Bitfield<3> pwt; // Page-Level Writethrough
557 Bitfield<10> osxmmexcpt; // Operating System Unmasked
559 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
560 Bitfield<8> pce; // Performance-Monitoring Counter Enable
561 Bitfield<7> pge; // Page-Global Enable
562 Bitfield<6> mce; // Machine Check Enable
563 Bitfield<5> pae; // Physical-Address Extension
564 Bitfield<4> pse; // Page Size Extensions
565 Bitfield<3> de; // Debugging Extensions
566 Bitfield<2> tsd; // Time Stamp Disable
567 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
568 Bitfield<0> vme; // Virtual-8086 Mode Extensions
572 Bitfield<3, 0> tpr; // Task Priority Register
597 Bitfield<17, 16> rw0;
598 Bitfield<19, 18> len0;
599 Bitfield<21, 20> rw1;
600 Bitfield<23, 22> len1;
601 Bitfield<25, 24> rw2;
602 Bitfield<27, 26> len2;
603 Bitfield<29, 28> rw3;
604 Bitfield<31, 30> len3;
609 Bitfield<7, 0> vcnt; // Variable-Range Register Count
610 Bitfield<8> fix; // Fixed-Range Registers
611 Bitfield<10> wc; // Write-Combining
615 * SYSENTER configuration registers
617 BitUnion64(SysenterCS)
618 Bitfield<15, 0> targetCS;
619 EndBitUnion(SysenterCS)
621 BitUnion64(SysenterESP)
622 Bitfield<31, 0> targetESP;
623 EndBitUnion(SysenterESP)
625 BitUnion64(SysenterEIP)
626 Bitfield<31, 0> targetEIP;
627 EndBitUnion(SysenterEIP)
630 * Global machine check registers
633 Bitfield<7, 0> count; // Number of error reporting register banks
634 Bitfield<8> MCGCP; // MCG_CTL register present.
637 BitUnion64(McgStatus)
638 Bitfield<0> ripv; // Restart-IP valid
639 Bitfield<1> eipv; // Error-IP valid
640 Bitfield<2> mcip; // Machine check in-progress
641 EndBitUnion(McgStatus)
643 BitUnion64(DebugCtlMsr)
644 Bitfield<0> lbr; // Last-branch record
645 Bitfield<1> btf; // Branch single step
646 Bitfield<2> pb0; // Performance monitoring pin control 0
647 Bitfield<3> pb1; // Performance monitoring pin control 1
648 Bitfield<4> pb2; // Performance monitoring pin control 2
649 Bitfield<5> pb3; // Performance monitoring pin control 3
650 /*uint64_t pb(int index)
652 return bits(__data, index + 2);
654 EndBitUnion(DebugCtlMsr)
656 BitUnion64(MtrrPhysBase)
657 Bitfield<7, 0> type; // Default memory type
658 Bitfield<51, 12> physbase; // Range physical base address
659 EndBitUnion(MtrrPhysBase)
661 BitUnion64(MtrrPhysMask)
662 Bitfield<11> valid; // MTRR pair enable
663 Bitfield<51, 12> physmask; // Range physical mask
664 EndBitUnion(MtrrPhysMask)
666 BitUnion64(MtrrFixed)
667 /*uint64_t type(int index)
669 return bits(__data, index * 8 + 7, index * 8);
671 EndBitUnion(MtrrFixed)
674 /*uint64_t pa(int index)
676 return bits(__data, index * 8 + 2, index * 8);
680 BitUnion64(MtrrDefType)
681 Bitfield<7, 0> type; // Default type
682 Bitfield<10> fe; // Fixed range enable
683 Bitfield<11> e; // MTRR enable
684 EndBitUnion(MtrrDefType)
690 Bitfield<15,0> mcaErrorCode;
691 Bitfield<31,16> modelSpecificCode;
692 Bitfield<56,32> otherInfo;
693 Bitfield<57> pcc; // Processor-context corrupt
694 Bitfield<58> addrv; // Error-address register valid
695 Bitfield<59> miscv; // Miscellaneous-error register valid
696 Bitfield<60> en; // Error condition enabled
697 Bitfield<61> uc; // Uncorrected error
698 Bitfield<62> over; // Status register overflow
699 Bitfield<63> val; // Valid
700 EndBitUnion(McStatus)
703 /*uint64_t en(int index)
705 return bits(__data, index);
709 // Extended feature enable register
711 Bitfield<0> sce; // System call extensions
712 Bitfield<8> lme; // Long mode enable
713 Bitfield<10> lma; // Long mode active
714 Bitfield<11> nxe; // No-execute enable
715 Bitfield<12> svme; // Secure virtual machine enable
716 Bitfield<14> ffxsr; // Fast fxsave/fxrstor
720 Bitfield<31,0> targetEip;
721 Bitfield<47,32> syscallCsAndSs;
722 Bitfield<63,48> sysretCsAndSs;
729 BitUnion64(PerfEvtSel)
730 Bitfield<7,0> eventMask;
731 Bitfield<15,8> unitMask;
732 Bitfield<16> usr; // User mode
733 Bitfield<17> os; // Operating-system mode
734 Bitfield<18> e; // Edge detect
735 Bitfield<19> pc; // Pin control
736 Bitfield<20> intEn; // Interrupt enable
737 Bitfield<22> en; // Counter enable
738 Bitfield<23> inv; // Invert mask
739 Bitfield<31,24> counterMask;
740 EndBitUnion(PerfEvtSel)
743 Bitfield<18> mfde; // MtrrFixDramEn
744 Bitfield<19> mfdm; // MtrrFixDramModEn
745 Bitfield<20> mvdm; // MtrrVarDramEn
746 Bitfield<21> tom2; // MtrrTom2En
750 Bitfield<3> wr; // WrMem Enable
751 Bitfield<4> rd; // RdMem Enable
752 Bitfield<51,12> physbase; // Range physical base address
753 EndBitUnion(IorrBase)
756 Bitfield<11> v; // I/O register pair enable (valid)
757 Bitfield<51,12> physmask; // Range physical mask
758 EndBitUnion(IorrMask)
761 Bitfield<51,23> physAddr; // Top of memory physical address
772 EndBitUnion(IgnneMsr)
774 BitUnion64(SmmCtlMsr)
777 Bitfield<2> smiCycle;
779 Bitfield<4> rsmCycle;
780 EndBitUnion(SmmCtlMsr)
785 BitUnion64(SegSelector)
786 // The following bitfield is not defined in the ISA, but it's useful
787 // when checking selectors in larger data types to make sure they
789 Bitfield<63, 3> esi; // Extended selector
790 Bitfield<15, 3> si; // Selector Index
791 Bitfield<2> ti; // Table Indicator
792 Bitfield<1, 0> rpl; // Requestor Privilege Level
793 EndBitUnion(SegSelector)
796 * Segment Descriptors
799 BitUnion64(SegDescriptor)
800 Bitfield<63, 56> baseHigh;
801 Bitfield<39, 16> baseLow;
802 Bitfield<55> g; // Granularity
803 Bitfield<54> d; // Default Operand Size
804 Bitfield<54> b; // Default Operand Size
805 Bitfield<53> l; // Long Attribute Bit
806 Bitfield<52> avl; // Available To Software
807 Bitfield<51, 48> limitHigh;
808 Bitfield<15, 0> limitLow;
809 Bitfield<47> p; // Present
810 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
811 Bitfield<44> s; // System
812 SubBitUnion(type, 43, 40)
813 // Specifies whether this descriptor is for code or data.
814 Bitfield<43> codeOrData;
816 // These bit fields are for code segments
817 Bitfield<42> c; // Conforming
818 Bitfield<41> r; // Readable
820 // These bit fields are for data segments
821 Bitfield<42> e; // Expand-Down
822 Bitfield<41> w; // Writable
824 // This is used for both code and data segments.
825 Bitfield<40> a; // Accessed
827 EndBitUnion(SegDescriptor)
830 Bitfield<0> writable;
831 Bitfield<1> readable;
832 Bitfield<2> expandDown;
834 Bitfield<5> defaultSize;
835 Bitfield<6> longMode;
838 BitUnion64(GateDescriptor)
839 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
840 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
841 Bitfield<31, 16> selector; // Target Code-Segment Selector
842 Bitfield<47> p; // Present
843 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
844 Bitfield<43, 40> type;
845 Bitfield<36, 32> count; // Parameter Count
846 EndBitUnion(GateDescriptor)
849 * Descriptor-Table Registers
868 * Local APIC Base Register
870 BitUnion64(LocalApicBase)
871 Bitfield<51, 12> base;
874 EndBitUnion(LocalApicBase)
877 #endif // __ARCH_X86_INTREGS_HH__