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58 #ifndef __ARCH_X86_MISCREGS_HH__
59 #define __ARCH_X86_MISCREGS_HH__
61 #include "arch/x86/segmentregs.hh"
62 #include "arch/x86/x86_traits.hh"
63 #include "base/bitunion.hh"
65 //These get defined in some system headers (at least termbits.h). That confuses
66 //things here significantly.
88 // Most of these are invalid.
90 MISCREG_CR0 = MISCREG_CR_BASE,
108 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
109 MISCREG_DR0 = MISCREG_DR_BASE,
119 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
122 * Model Specific Registers
124 // Time stamp counter
130 MISCREG_SYSENTER_ESP,
131 MISCREG_SYSENTER_EIP,
137 MISCREG_DEBUG_CTL_MSR,
139 MISCREG_LAST_BRANCH_FROM_IP,
140 MISCREG_LAST_BRANCH_TO_IP,
141 MISCREG_LAST_EXCEPTION_FROM_IP,
142 MISCREG_LAST_EXCEPTION_TO_IP,
144 MISCREG_MTRR_PHYS_BASE_BASE,
145 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
146 MISCREG_MTRR_PHYS_BASE_1,
147 MISCREG_MTRR_PHYS_BASE_2,
148 MISCREG_MTRR_PHYS_BASE_3,
149 MISCREG_MTRR_PHYS_BASE_4,
150 MISCREG_MTRR_PHYS_BASE_5,
151 MISCREG_MTRR_PHYS_BASE_6,
152 MISCREG_MTRR_PHYS_BASE_7,
154 MISCREG_MTRR_PHYS_MASK_BASE,
155 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
156 MISCREG_MTRR_PHYS_MASK_1,
157 MISCREG_MTRR_PHYS_MASK_2,
158 MISCREG_MTRR_PHYS_MASK_3,
159 MISCREG_MTRR_PHYS_MASK_4,
160 MISCREG_MTRR_PHYS_MASK_5,
161 MISCREG_MTRR_PHYS_MASK_6,
162 MISCREG_MTRR_PHYS_MASK_7,
164 MISCREG_MTRR_FIX_64K_00000,
165 MISCREG_MTRR_FIX_16K_80000,
166 MISCREG_MTRR_FIX_16K_A0000,
167 MISCREG_MTRR_FIX_4K_C0000,
168 MISCREG_MTRR_FIX_4K_C8000,
169 MISCREG_MTRR_FIX_4K_D0000,
170 MISCREG_MTRR_FIX_4K_D8000,
171 MISCREG_MTRR_FIX_4K_E0000,
172 MISCREG_MTRR_FIX_4K_E8000,
173 MISCREG_MTRR_FIX_4K_F0000,
174 MISCREG_MTRR_FIX_4K_F8000,
181 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
187 MISCREG_MC_STATUS_BASE,
188 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
194 MISCREG_MC_ADDR_BASE,
195 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
201 MISCREG_MC_MISC_BASE,
202 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
208 // Extended feature enable register
217 MISCREG_KERNEL_GS_BASE,
221 MISCREG_PERF_EVT_SEL_BASE,
222 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
223 MISCREG_PERF_EVT_SEL1,
224 MISCREG_PERF_EVT_SEL2,
225 MISCREG_PERF_EVT_SEL3,
227 MISCREG_PERF_EVT_CTR_BASE,
228 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
229 MISCREG_PERF_EVT_CTR1,
230 MISCREG_PERF_EVT_CTR2,
231 MISCREG_PERF_EVT_CTR3,
235 MISCREG_IORR_BASE_BASE,
236 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
239 MISCREG_IORR_MASK_BASE,
240 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
255 MISCREG_SEG_SEL_BASE,
256 MISCREG_ES = MISCREG_SEG_SEL_BASE,
270 // Hidden segment base field
271 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
272 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
286 // The effective segment base, ie what is actually added to an
287 // address. In 64 bit mode this can be different from the above,
289 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
290 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
297 MISCREG_TSL_EFF_BASE,
298 MISCREG_TSG_EFF_BASE,
302 MISCREG_IDTR_EFF_BASE,
304 // Hidden segment limit field
305 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
306 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
320 // Hidden segment limit attributes
321 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
322 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
336 // Floating point control registers
338 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
340 //XXX Add "Model-Specific Registers"
345 MISCREG_APIC_ID = MISCREG_APIC_START,
346 MISCREG_APIC_VERSION,
347 MISCREG_APIC_TASK_PRIORITY,
348 MISCREG_APIC_ARBITRATION_PRIORITY,
349 MISCREG_APIC_PROCESSOR_PRIORITY,
351 MISCREG_APIC_LOGICAL_DESTINATION,
352 MISCREG_APIC_DESTINATION_FORMAT,
353 MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR,
355 MISCREG_APIC_IN_SERVICE_BASE,
357 MISCREG_APIC_TRIGGER_MODE_BASE = MISCREG_APIC_IN_SERVICE_BASE + 16,
359 MISCREG_APIC_INTERRUPT_REQUEST_BASE =
360 MISCREG_APIC_TRIGGER_MODE_BASE + 16,
362 MISCREG_APIC_ERROR_STATUS = MISCREG_APIC_INTERRUPT_REQUEST_BASE + 16,
363 MISCREG_APIC_INTERRUPT_COMMAND_LOW,
364 MISCREG_APIC_INTERRUPT_COMMAND_HIGH,
365 MISCREG_APIC_LVT_TIMER,
366 MISCREG_APIC_LVT_THERMAL_SENSOR,
367 MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS,
368 MISCREG_APIC_LVT_LINT0,
369 MISCREG_APIC_LVT_LINT1,
370 MISCREG_APIC_LVT_ERROR,
371 MISCREG_APIC_INITIAL_COUNT,
372 MISCREG_APIC_CURRENT_COUNT,
373 MISCREG_APIC_DIVIDE_COUNT,
374 MISCREG_APIC_END = MISCREG_APIC_DIVIDE_COUNT,
376 // "Fake" MSRs for internally implemented devices
377 MISCREG_PCI_CONFIG_ADDRESS,
382 static inline MiscRegIndex
383 MISCREG_CR(int index)
385 return (MiscRegIndex)(MISCREG_CR_BASE + index);
388 static inline MiscRegIndex
389 MISCREG_DR(int index)
391 return (MiscRegIndex)(MISCREG_DR_BASE + index);
394 static inline MiscRegIndex
395 MISCREG_MTRR_PHYS_BASE(int index)
397 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
400 static inline MiscRegIndex
401 MISCREG_MTRR_PHYS_MASK(int index)
403 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
406 static inline MiscRegIndex
407 MISCREG_MC_CTL(int index)
409 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
412 static inline MiscRegIndex
413 MISCREG_MC_STATUS(int index)
415 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
418 static inline MiscRegIndex
419 MISCREG_MC_ADDR(int index)
421 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
424 static inline MiscRegIndex
425 MISCREG_MC_MISC(int index)
427 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
430 static inline MiscRegIndex
431 MISCREG_PERF_EVT_SEL(int index)
433 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
436 static inline MiscRegIndex
437 MISCREG_PERF_EVT_CTR(int index)
439 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
442 static inline MiscRegIndex
443 MISCREG_IORR_BASE(int index)
445 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
448 static inline MiscRegIndex
449 MISCREG_IORR_MASK(int index)
451 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
454 static inline MiscRegIndex
455 MISCREG_SEG_SEL(int index)
457 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
460 static inline MiscRegIndex
461 MISCREG_SEG_BASE(int index)
463 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
466 static inline MiscRegIndex
467 MISCREG_SEG_EFF_BASE(int index)
469 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
472 static inline MiscRegIndex
473 MISCREG_SEG_LIMIT(int index)
475 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
478 static inline MiscRegIndex
479 MISCREG_SEG_ATTR(int index)
481 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
484 static inline MiscRegIndex
485 MISCREG_APIC_IN_SERVICE(int index)
487 return (MiscRegIndex)(MISCREG_APIC_IN_SERVICE_BASE + index);
490 static inline MiscRegIndex
491 MISCREG_APIC_TRIGGER_MODE(int index)
493 return (MiscRegIndex)(MISCREG_APIC_TRIGGER_MODE_BASE + index);
496 static inline MiscRegIndex
497 MISCREG_APIC_INTERRUPT_REQUEST(int index)
499 return (MiscRegIndex)(MISCREG_APIC_INTERRUPT_REQUEST_BASE + index);
503 * A type to describe the condition code bits of the RFLAGS register,
504 * plus two flags, EZF and ECF, which are only visible to microcode.
506 BitUnion64(CCFlagBits)
515 EndBitUnion(CCFlagBits)
521 Bitfield<21> id; // ID Flag
522 Bitfield<20> vip; // Virtual Interrupt Pending
523 Bitfield<19> vif; // Virtual Interrupt Flag
524 Bitfield<18> ac; // Alignment Check
525 Bitfield<17> vm; // Virtual-8086 Mode
526 Bitfield<16> rf; // Resume Flag
527 Bitfield<14> nt; // Nested Task
528 Bitfield<13, 12> iopl; // I/O Privilege Level
529 Bitfield<11> of; // Overflow Flag
530 Bitfield<10> df; // Direction Flag
531 Bitfield<9> intf; // Interrupt Flag
532 Bitfield<8> tf; // Trap Flag
533 Bitfield<7> sf; // Sign Flag
534 Bitfield<6> zf; // Zero Flag
535 Bitfield<4> af; // Auxiliary Flag
536 Bitfield<2> pf; // Parity Flag
537 Bitfield<0> cf; // Carry Flag
544 Bitfield<31> pg; // Paging
545 Bitfield<30> cd; // Cache Disable
546 Bitfield<29> nw; // Not Writethrough
547 Bitfield<18> am; // Alignment Mask
548 Bitfield<16> wp; // Write Protect
549 Bitfield<5> ne; // Numeric Error
550 Bitfield<4> et; // Extension Type
551 Bitfield<3> ts; // Task Switched
552 Bitfield<2> em; // Emulation
553 Bitfield<1> mp; // Monitor Coprocessor
554 Bitfield<0> pe; // Protection Enabled
557 // Page Fault Virtual Address
559 Bitfield<31, 0> legacy;
563 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
565 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
567 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
569 Bitfield<4> pcd; // Page-Level Cache Disable
570 Bitfield<3> pwt; // Page-Level Writethrough
574 Bitfield<10> osxmmexcpt; // Operating System Unmasked
576 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
577 Bitfield<8> pce; // Performance-Monitoring Counter Enable
578 Bitfield<7> pge; // Page-Global Enable
579 Bitfield<6> mce; // Machine Check Enable
580 Bitfield<5> pae; // Physical-Address Extension
581 Bitfield<4> pse; // Page Size Extensions
582 Bitfield<3> de; // Debugging Extensions
583 Bitfield<2> tsd; // Time Stamp Disable
584 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
585 Bitfield<0> vme; // Virtual-8086 Mode Extensions
589 Bitfield<3, 0> tpr; // Task Priority Register
594 Bitfield<7, 0> vcnt; // Variable-Range Register Count
595 Bitfield<8> fix; // Fixed-Range Registers
596 Bitfield<10> wc; // Write-Combining
600 * SYSENTER configuration registers
602 BitUnion64(SysenterCS)
603 Bitfield<15, 0> targetCS;
604 EndBitUnion(SysenterCS)
606 BitUnion64(SysenterESP)
607 Bitfield<31, 0> targetESP;
608 EndBitUnion(SysenterESP)
610 BitUnion64(SysenterEIP)
611 Bitfield<31, 0> targetEIP;
612 EndBitUnion(SysenterEIP)
615 * Global machine check registers
618 Bitfield<7, 0> count; // Number of error reporting register banks
619 Bitfield<8> MCGCP; // MCG_CTL register present.
622 BitUnion64(McgStatus)
623 Bitfield<0> ripv; // Restart-IP valid
624 Bitfield<1> eipv; // Error-IP valid
625 Bitfield<2> mcip; // Machine check in-progress
626 EndBitUnion(McgStatus)
628 BitUnion64(DebugCtlMsr)
629 Bitfield<0> lbr; // Last-branch record
630 Bitfield<1> btf; // Branch single step
631 Bitfield<2> pb0; // Performance monitoring pin control 0
632 Bitfield<3> pb1; // Performance monitoring pin control 1
633 Bitfield<4> pb2; // Performance monitoring pin control 2
634 Bitfield<5> pb3; // Performance monitoring pin control 3
635 /*uint64_t pb(int index)
637 return bits(__data, index + 2);
639 EndBitUnion(DebugCtlMsr)
641 BitUnion64(MtrrPhysBase)
642 Bitfield<7, 0> type; // Default memory type
643 Bitfield<51, 12> physbase; // Range physical base address
644 EndBitUnion(MtrrPhysBase)
646 BitUnion64(MtrrPhysMask)
647 Bitfield<11> valid; // MTRR pair enable
648 Bitfield<51, 12> physmask; // Range physical mask
649 EndBitUnion(MtrrPhysMask)
651 BitUnion64(MtrrFixed)
652 /*uint64_t type(int index)
654 return bits(__data, index * 8 + 7, index * 8);
656 EndBitUnion(MtrrFixed)
659 /*uint64_t pa(int index)
661 return bits(__data, index * 8 + 2, index * 8);
665 BitUnion64(MtrrDefType)
666 Bitfield<7, 0> type; // Default type
667 Bitfield<10> fe; // Fixed range enable
668 Bitfield<11> e; // MTRR enable
669 EndBitUnion(MtrrDefType)
675 Bitfield<15,0> mcaErrorCode;
676 Bitfield<31,16> modelSpecificCode;
677 Bitfield<56,32> otherInfo;
678 Bitfield<57> pcc; // Processor-context corrupt
679 Bitfield<58> addrv; // Error-address register valid
680 Bitfield<59> miscv; // Miscellaneous-error register valid
681 Bitfield<60> en; // Error condition enabled
682 Bitfield<61> uc; // Uncorrected error
683 Bitfield<62> over; // Status register overflow
684 Bitfield<63> val; // Valid
685 EndBitUnion(McStatus)
688 /*uint64_t en(int index)
690 return bits(__data, index);
694 // Extended feature enable register
696 Bitfield<0> sce; // System call extensions
697 Bitfield<8> lme; // Long mode enable
698 Bitfield<10> lma; // Long mode active
699 Bitfield<11> nxe; // No-execute enable
700 Bitfield<12> svme; // Secure virtual machine enable
701 Bitfield<14> ffxsr; // Fast fxsave/fxrstor
705 Bitfield<31,0> targetEip;
706 Bitfield<47,32> syscallCsAndSs;
707 Bitfield<63,48> sysretCsAndSs;
714 BitUnion64(PerfEvtSel)
715 Bitfield<7,0> eventMask;
716 Bitfield<15,8> unitMask;
717 Bitfield<16> usr; // User mode
718 Bitfield<17> os; // Operating-system mode
719 Bitfield<18> e; // Edge detect
720 Bitfield<19> pc; // Pin control
721 Bitfield<20> intEn; // Interrupt enable
722 Bitfield<22> en; // Counter enable
723 Bitfield<23> inv; // Invert mask
724 Bitfield<31,24> counterMask;
725 EndBitUnion(PerfEvtSel)
728 Bitfield<18> mfde; // MtrrFixDramEn
729 Bitfield<19> mfdm; // MtrrFixDramModEn
730 Bitfield<20> mvdm; // MtrrVarDramEn
731 Bitfield<21> tom2; // MtrrTom2En
735 Bitfield<3> wr; // WrMem Enable
736 Bitfield<4> rd; // RdMem Enable
737 Bitfield<51,12> physbase; // Range physical base address
738 EndBitUnion(IorrBase)
741 Bitfield<11> v; // I/O register pair enable (valid)
742 Bitfield<51,12> physmask; // Range physical mask
743 EndBitUnion(IorrMask)
746 Bitfield<51,23> physAddr; // Top of memory physical address
757 EndBitUnion(IgnneMsr)
759 BitUnion64(SmmCtlMsr)
762 Bitfield<2> smiCycle;
764 Bitfield<4> rsmCycle;
765 EndBitUnion(SmmCtlMsr)
770 BitUnion64(SegSelector)
771 // The following bitfield is not defined in the ISA, but it's useful
772 // when checking selectors in larger data types to make sure they
774 Bitfield<63, 3> esi; // Extended selector
775 Bitfield<15, 3> si; // Selector Index
776 Bitfield<2> ti; // Table Indicator
777 Bitfield<1, 0> rpl; // Requestor Privilege Level
778 EndBitUnion(SegSelector)
781 * Segment Descriptors
784 BitUnion64(SegDescriptor)
785 Bitfield<63, 56> baseHigh;
786 Bitfield<39, 16> baseLow;
787 Bitfield<55> g; // Granularity
788 Bitfield<54> d; // Default Operand Size
789 Bitfield<54> b; // Default Operand Size
790 Bitfield<53> l; // Long Attribute Bit
791 Bitfield<52> avl; // Available To Software
792 Bitfield<51, 48> limitHigh;
793 Bitfield<15, 0> limitLow;
794 Bitfield<47> p; // Present
795 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
796 Bitfield<44> s; // System
797 SubBitUnion(type, 43, 40)
798 // Specifies whether this descriptor is for code or data.
799 Bitfield<43> codeOrData;
801 // These bit fields are for code segments
802 Bitfield<42> c; // Conforming
803 Bitfield<41> r; // Readable
805 // These bit fields are for data segments
806 Bitfield<42> e; // Expand-Down
807 Bitfield<41> w; // Writable
809 // This is used for both code and data segments.
810 Bitfield<40> a; // Accessed
812 EndBitUnion(SegDescriptor)
815 Bitfield<0> writable;
816 Bitfield<1> readable;
817 Bitfield<2> expandDown;
819 Bitfield<5> defaultSize;
820 Bitfield<6> longMode;
823 BitUnion64(GateDescriptor)
824 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
825 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
826 Bitfield<31, 16> selector; // Target Code-Segment Selector
827 Bitfield<47> p; // Present
828 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
829 Bitfield<43, 40> type;
830 Bitfield<36, 32> count; // Parameter Count
831 EndBitUnion(GateDescriptor)
834 * Descriptor-Table Registers
853 * Local APIC Base Register
855 BitUnion64(LocalApicBase)
856 Bitfield<51, 12> base;
859 EndBitUnion(LocalApicBase)
862 #endif // __ARCH_X86_INTREGS_HH__