src/arch/x86/miscregs.hh

   1 /*
   2  * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
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   8  *
   9  * The software must be used only for Non-Commercial Use which means any
  10  * use which is NOT directed to receiving any direct monetary
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  12  * examples of non-commercial use are academic research, personal study,
  13  * teaching, education and corporate research & development.
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  19  * covered by patents for commercial use, please contact:
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  39  * and (ii) such Derivatives of the software include the above copyright
  40  * notice to acknowledge the contribution from this software where
  41  * applicable, this list of conditions and the disclaimer below.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_MISCREGS_HH__
  59 #define __ARCH_X86_MISCREGS_HH__
  60
  61 #include "arch/x86/segmentregs.hh"
  62 #include "arch/x86/x86_traits.hh"
  63 #include "base/bitunion.hh"
  64
  65 //These get defined in some system headers (at least termbits.h). That confuses
  66 //things here significantly.
  67 #undef CR0
  68 #undef CR2
  69 #undef CR3
  70
  71 namespace X86ISA
  72 {
  73     enum CondFlagBit {
  74         CFBit = 1 << 0,
  75         PFBit = 1 << 2,
  76         ECFBit = 1 << 3,
  77         AFBit = 1 << 4,
  78         EZFBit = 1 << 5,
  79         ZFBit = 1 << 6,
  80         SFBit = 1 << 7,
  81         DFBit = 1 << 10,
  82         OFBit = 1 << 11
  83     };
  84
  85     enum RFLAGBit {
  86         TFBit = 1 << 8,
  87         IFBit = 1 << 9,
  88         NTBit = 1 << 14,
  89         RFBit = 1 << 16,
  90         VMBit = 1 << 17,
  91         ACBit = 1 << 18,
  92         VIFBit = 1 << 19,
  93         VIPBit = 1 << 20,
  94         IDBit = 1 << 21
  95     };
  96
  97     enum MiscRegIndex
  98     {
  99         // Control registers
 100         // Most of these are invalid.
 101         MISCREG_CR_BASE,
 102         MISCREG_CR0 = MISCREG_CR_BASE,
 103         MISCREG_CR1,
 104         MISCREG_CR2,
 105         MISCREG_CR3,
 106         MISCREG_CR4,
 107         MISCREG_CR5,
 108         MISCREG_CR6,
 109         MISCREG_CR7,
 110         MISCREG_CR8,
 111         MISCREG_CR9,
 112         MISCREG_CR10,
 113         MISCREG_CR11,
 114         MISCREG_CR12,
 115         MISCREG_CR13,
 116         MISCREG_CR14,
 117         MISCREG_CR15,
 118
 119         // Debug registers
 120         MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
 121         MISCREG_DR0 = MISCREG_DR_BASE,
 122         MISCREG_DR1,
 123         MISCREG_DR2,
 124         MISCREG_DR3,
 125         MISCREG_DR4,
 126         MISCREG_DR5,
 127         MISCREG_DR6,
 128         MISCREG_DR7,
 129
 130         // Flags register
 131         MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
 132
 133         //Register to keep handy values like the CPU mode in.
 134         MISCREG_M5_REG,
 135
 136         /*
 137          * Model Specific Registers
 138          */
 139         // Time stamp counter
 140         MISCREG_TSC,
 141
 142         MISCREG_MTRRCAP,
 143
 144         MISCREG_SYSENTER_CS,
 145         MISCREG_SYSENTER_ESP,
 146         MISCREG_SYSENTER_EIP,
 147
 148         MISCREG_MCG_CAP,
 149         MISCREG_MCG_STATUS,
 150         MISCREG_MCG_CTL,
 151
 152         MISCREG_DEBUG_CTL_MSR,
 153
 154         MISCREG_LAST_BRANCH_FROM_IP,
 155         MISCREG_LAST_BRANCH_TO_IP,
 156         MISCREG_LAST_EXCEPTION_FROM_IP,
 157         MISCREG_LAST_EXCEPTION_TO_IP,
 158
 159         MISCREG_MTRR_PHYS_BASE_BASE,
 160         MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
 161         MISCREG_MTRR_PHYS_BASE_1,
 162         MISCREG_MTRR_PHYS_BASE_2,
 163         MISCREG_MTRR_PHYS_BASE_3,
 164         MISCREG_MTRR_PHYS_BASE_4,
 165         MISCREG_MTRR_PHYS_BASE_5,
 166         MISCREG_MTRR_PHYS_BASE_6,
 167         MISCREG_MTRR_PHYS_BASE_7,
 168
 169         MISCREG_MTRR_PHYS_MASK_BASE,
 170         MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
 171         MISCREG_MTRR_PHYS_MASK_1,
 172         MISCREG_MTRR_PHYS_MASK_2,
 173         MISCREG_MTRR_PHYS_MASK_3,
 174         MISCREG_MTRR_PHYS_MASK_4,
 175         MISCREG_MTRR_PHYS_MASK_5,
 176         MISCREG_MTRR_PHYS_MASK_6,
 177         MISCREG_MTRR_PHYS_MASK_7,
 178
 179         MISCREG_MTRR_FIX_64K_00000,
 180         MISCREG_MTRR_FIX_16K_80000,
 181         MISCREG_MTRR_FIX_16K_A0000,
 182         MISCREG_MTRR_FIX_4K_C0000,
 183         MISCREG_MTRR_FIX_4K_C8000,
 184         MISCREG_MTRR_FIX_4K_D0000,
 185         MISCREG_MTRR_FIX_4K_D8000,
 186         MISCREG_MTRR_FIX_4K_E0000,
 187         MISCREG_MTRR_FIX_4K_E8000,
 188         MISCREG_MTRR_FIX_4K_F0000,
 189         MISCREG_MTRR_FIX_4K_F8000,
 190
 191         MISCREG_PAT,
 192
 193         MISCREG_DEF_TYPE,
 194
 195         MISCREG_MC_CTL_BASE,
 196         MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
 197         MISCREG_MC1_CTL,
 198         MISCREG_MC2_CTL,
 199         MISCREG_MC3_CTL,
 200         MISCREG_MC4_CTL,
 201         MISCREG_MC5_CTL,
 202         MISCREG_MC6_CTL,
 203         MISCREG_MC7_CTL,
 204
 205         MISCREG_MC_STATUS_BASE,
 206         MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
 207         MISCREG_MC1_STATUS,
 208         MISCREG_MC2_STATUS,
 209         MISCREG_MC3_STATUS,
 210         MISCREG_MC4_STATUS,
 211         MISCREG_MC5_STATUS,
 212         MISCREG_MC6_STATUS,
 213         MISCREG_MC7_STATUS,
 214
 215         MISCREG_MC_ADDR_BASE,
 216         MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
 217         MISCREG_MC1_ADDR,
 218         MISCREG_MC2_ADDR,
 219         MISCREG_MC3_ADDR,
 220         MISCREG_MC4_ADDR,
 221         MISCREG_MC5_ADDR,
 222         MISCREG_MC6_ADDR,
 223         MISCREG_MC7_ADDR,
 224
 225         MISCREG_MC_MISC_BASE,
 226         MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
 227         MISCREG_MC1_MISC,
 228         MISCREG_MC2_MISC,
 229         MISCREG_MC3_MISC,
 230         MISCREG_MC4_MISC,
 231         MISCREG_MC5_MISC,
 232         MISCREG_MC6_MISC,
 233         MISCREG_MC7_MISC,
 234
 235         // Extended feature enable register
 236         MISCREG_EFER,
 237
 238         MISCREG_STAR,
 239         MISCREG_LSTAR,
 240         MISCREG_CSTAR,
 241
 242         MISCREG_SF_MASK,
 243
 244         MISCREG_KERNEL_GS_BASE,
 245
 246         MISCREG_TSC_AUX,
 247
 248         MISCREG_PERF_EVT_SEL_BASE,
 249         MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
 250         MISCREG_PERF_EVT_SEL1,
 251         MISCREG_PERF_EVT_SEL2,
 252         MISCREG_PERF_EVT_SEL3,
 253
 254         MISCREG_PERF_EVT_CTR_BASE,
 255         MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
 256         MISCREG_PERF_EVT_CTR1,
 257         MISCREG_PERF_EVT_CTR2,
 258         MISCREG_PERF_EVT_CTR3,
 259
 260         MISCREG_SYSCFG,
 261
 262         MISCREG_IORR_BASE_BASE,
 263         MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
 264         MISCREG_IORR_BASE1,
 265
 266         MISCREG_IORR_MASK_BASE,
 267         MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
 268         MISCREG_IORR_MASK1,
 269
 270         MISCREG_TOP_MEM,
 271         MISCREG_TOP_MEM2,
 272
 273         MISCREG_VM_CR,
 274         MISCREG_IGNNE,
 275         MISCREG_SMM_CTL,
 276         MISCREG_VM_HSAVE_PA,
 277
 278         /*
 279          * Segment registers
 280          */
 281         // Segment selectors
 282         MISCREG_SEG_SEL_BASE,
 283         MISCREG_ES = MISCREG_SEG_SEL_BASE,
 284         MISCREG_CS,
 285         MISCREG_SS,
 286         MISCREG_DS,
 287         MISCREG_FS,
 288         MISCREG_GS,
 289         MISCREG_HS,
 290         MISCREG_TSL,
 291         MISCREG_TSG,
 292         MISCREG_LS,
 293         MISCREG_MS,
 294         MISCREG_TR,
 295         MISCREG_IDTR,
 296
 297         // Hidden segment base field
 298         MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
 299         MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
 300         MISCREG_CS_BASE,
 301         MISCREG_SS_BASE,
 302         MISCREG_DS_BASE,
 303         MISCREG_FS_BASE,
 304         MISCREG_GS_BASE,
 305         MISCREG_HS_BASE,
 306         MISCREG_TSL_BASE,
 307         MISCREG_TSG_BASE,
 308         MISCREG_LS_BASE,
 309         MISCREG_MS_BASE,
 310         MISCREG_TR_BASE,
 311         MISCREG_IDTR_BASE,
 312
 313         // The effective segment base, ie what is actually added to an
 314         // address. In 64 bit mode this can be different from the above,
 315         // namely 0.
 316         MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
 317         MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
 318         MISCREG_CS_EFF_BASE,
 319         MISCREG_SS_EFF_BASE,
 320         MISCREG_DS_EFF_BASE,
 321         MISCREG_FS_EFF_BASE,
 322         MISCREG_GS_EFF_BASE,
 323         MISCREG_HS_EFF_BASE,
 324         MISCREG_TSL_EFF_BASE,
 325         MISCREG_TSG_EFF_BASE,
 326         MISCREG_LS_EFF_BASE,
 327         MISCREG_MS_EFF_BASE,
 328         MISCREG_TR_EFF_BASE,
 329         MISCREG_IDTR_EFF_BASE,
 330
 331         // Hidden segment limit field
 332         MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
 333         MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
 334         MISCREG_CS_LIMIT,
 335         MISCREG_SS_LIMIT,
 336         MISCREG_DS_LIMIT,
 337         MISCREG_FS_LIMIT,
 338         MISCREG_GS_LIMIT,
 339         MISCREG_HS_LIMIT,
 340         MISCREG_TSL_LIMIT,
 341         MISCREG_TSG_LIMIT,
 342         MISCREG_LS_LIMIT,
 343         MISCREG_MS_LIMIT,
 344         MISCREG_TR_LIMIT,
 345         MISCREG_IDTR_LIMIT,
 346
 347         // Hidden segment limit attributes
 348         MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
 349         MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
 350         MISCREG_CS_ATTR,
 351         MISCREG_SS_ATTR,
 352         MISCREG_DS_ATTR,
 353         MISCREG_FS_ATTR,
 354         MISCREG_GS_ATTR,
 355         MISCREG_HS_ATTR,
 356         MISCREG_TSL_ATTR,
 357         MISCREG_TSG_ATTR,
 358         MISCREG_LS_ATTR,
 359         MISCREG_MS_ATTR,
 360         MISCREG_TR_ATTR,
 361         MISCREG_IDTR_ATTR,
 362
 363         // Floating point control registers
 364         MISCREG_X87_TOP =
 365             MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
 366
 367         //XXX Add "Model-Specific Registers"
 368
 369         MISCREG_APIC_BASE,
 370
 371         // "Fake" MSRs for internally implemented devices
 372         MISCREG_PCI_CONFIG_ADDRESS,
 373
 374         NUM_MISCREGS
 375     };
 376
 377     static inline MiscRegIndex
 378     MISCREG_CR(int index)
 379     {
 380         return (MiscRegIndex)(MISCREG_CR_BASE + index);
 381     }
 382
 383     static inline MiscRegIndex
 384     MISCREG_DR(int index)
 385     {
 386         return (MiscRegIndex)(MISCREG_DR_BASE + index);
 387     }
 388
 389     static inline MiscRegIndex
 390     MISCREG_MTRR_PHYS_BASE(int index)
 391     {
 392         return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
 393     }
 394
 395     static inline MiscRegIndex
 396     MISCREG_MTRR_PHYS_MASK(int index)
 397     {
 398         return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
 399     }
 400
 401     static inline MiscRegIndex
 402     MISCREG_MC_CTL(int index)
 403     {
 404         return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
 405     }
 406
 407     static inline MiscRegIndex
 408     MISCREG_MC_STATUS(int index)
 409     {
 410         return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
 411     }
 412
 413     static inline MiscRegIndex
 414     MISCREG_MC_ADDR(int index)
 415     {
 416         return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
 417     }
 418
 419     static inline MiscRegIndex
 420     MISCREG_MC_MISC(int index)
 421     {
 422         return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
 423     }
 424
 425     static inline MiscRegIndex
 426     MISCREG_PERF_EVT_SEL(int index)
 427     {
 428         return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
 429     }
 430
 431     static inline MiscRegIndex
 432     MISCREG_PERF_EVT_CTR(int index)
 433     {
 434         return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
 435     }
 436
 437     static inline MiscRegIndex
 438     MISCREG_IORR_BASE(int index)
 439     {
 440         return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
 441     }
 442
 443     static inline MiscRegIndex
 444     MISCREG_IORR_MASK(int index)
 445     {
 446         return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
 447     }
 448
 449     static inline MiscRegIndex
 450     MISCREG_SEG_SEL(int index)
 451     {
 452         return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
 453     }
 454
 455     static inline MiscRegIndex
 456     MISCREG_SEG_BASE(int index)
 457     {
 458         return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
 459     }
 460
 461     static inline MiscRegIndex
 462     MISCREG_SEG_EFF_BASE(int index)
 463     {
 464         return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
 465     }
 466
 467     static inline MiscRegIndex
 468     MISCREG_SEG_LIMIT(int index)
 469     {
 470         return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
 471     }
 472
 473     static inline MiscRegIndex
 474     MISCREG_SEG_ATTR(int index)
 475     {
 476         return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
 477     }
 478
 479     /**
 480      * A type to describe the condition code bits of the RFLAGS register,
 481      * plus two flags, EZF and ECF, which are only visible to microcode.
 482      */
 483     BitUnion64(CCFlagBits)
 484         Bitfield<11> of;
 485         Bitfield<7> sf;
 486         Bitfield<6> zf;
 487         Bitfield<5> ezf;
 488         Bitfield<4> af;
 489         Bitfield<3> ecf;
 490         Bitfield<2> pf;
 491         Bitfield<0> cf;
 492     EndBitUnion(CCFlagBits)
 493
 494     /**
 495      * RFLAGS
 496      */
 497     BitUnion64(RFLAGS)
 498         Bitfield<21> id; // ID Flag
 499         Bitfield<20> vip; // Virtual Interrupt Pending
 500         Bitfield<19> vif; // Virtual Interrupt Flag
 501         Bitfield<18> ac; // Alignment Check
 502         Bitfield<17> vm; // Virtual-8086 Mode
 503         Bitfield<16> rf; // Resume Flag
 504         Bitfield<14> nt; // Nested Task
 505         Bitfield<13, 12> iopl; // I/O Privilege Level
 506         Bitfield<11> of; // Overflow Flag
 507         Bitfield<10> df; // Direction Flag
 508         Bitfield<9> intf; // Interrupt Flag
 509         Bitfield<8> tf; // Trap Flag
 510         Bitfield<7> sf; // Sign Flag
 511         Bitfield<6> zf; // Zero Flag
 512         Bitfield<4> af; // Auxiliary Flag
 513         Bitfield<2> pf; // Parity Flag
 514         Bitfield<0> cf; // Carry Flag
 515     EndBitUnion(RFLAGS)
 516
 517     BitUnion64(HandyM5Reg)
 518         Bitfield<0> mode;
 519         Bitfield<3, 1> submode;
 520         Bitfield<5, 4> cpl;
 521     EndBitUnion(HandyM5Reg)
 522
 523     /**
 524      * Control registers
 525      */
 526     BitUnion64(CR0)
 527         Bitfield<31> pg; // Paging
 528         Bitfield<30> cd; // Cache Disable
 529         Bitfield<29> nw; // Not Writethrough
 530         Bitfield<18> am; // Alignment Mask
 531         Bitfield<16> wp; // Write Protect
 532         Bitfield<5> ne; // Numeric Error
 533         Bitfield<4> et; // Extension Type
 534         Bitfield<3> ts; // Task Switched
 535         Bitfield<2> em; // Emulation
 536         Bitfield<1> mp; // Monitor Coprocessor
 537         Bitfield<0> pe; // Protection Enabled
 538     EndBitUnion(CR0)
 539
 540     // Page Fault Virtual Address
 541     BitUnion64(CR2)
 542         Bitfield<31, 0> legacy;
 543     EndBitUnion(CR2)
 544
 545     BitUnion64(CR3)
 546         Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
 547                                    // Base Address
 548         Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
 549                                // Base Address
 550         Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
 551                                  // Base Address
 552         Bitfield<4> pcd; // Page-Level Cache Disable
 553         Bitfield<3> pwt; // Page-Level Writethrough
 554     EndBitUnion(CR3)
 555
 556     BitUnion64(CR4)
 557         Bitfield<10> osxmmexcpt; // Operating System Unmasked
 558                                  // Exception Support
 559         Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
 560         Bitfield<8> pce; // Performance-Monitoring Counter Enable
 561         Bitfield<7> pge; // Page-Global Enable
 562         Bitfield<6> mce; // Machine Check Enable
 563         Bitfield<5> pae; // Physical-Address Extension
 564         Bitfield<4> pse; // Page Size Extensions
 565         Bitfield<3> de; // Debugging Extensions
 566         Bitfield<2> tsd; // Time Stamp Disable
 567         Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
 568         Bitfield<0> vme; // Virtual-8086 Mode Extensions
 569     EndBitUnion(CR4)
 570
 571     BitUnion64(CR8)
 572         Bitfield<3, 0> tpr; // Task Priority Register
 573     EndBitUnion(CR8)
 574
 575     // MTRR capabilities
 576     BitUnion64(MTRRcap)
 577         Bitfield<7, 0> vcnt; // Variable-Range Register Count
 578         Bitfield<8> fix; // Fixed-Range Registers
 579         Bitfield<10> wc; // Write-Combining
 580     EndBitUnion(MTRRcap)
 581
 582     /**
 583      * SYSENTER configuration registers
 584      */
 585     BitUnion64(SysenterCS)
 586         Bitfield<15, 0> targetCS;
 587     EndBitUnion(SysenterCS)
 588
 589     BitUnion64(SysenterESP)
 590         Bitfield<31, 0> targetESP;
 591     EndBitUnion(SysenterESP)
 592
 593     BitUnion64(SysenterEIP)
 594         Bitfield<31, 0> targetEIP;
 595     EndBitUnion(SysenterEIP)
 596
 597     /**
 598      * Global machine check registers
 599      */
 600     BitUnion64(McgCap)
 601         Bitfield<7, 0> count; // Number of error reporting register banks
 602         Bitfield<8> MCGCP; // MCG_CTL register present.
 603     EndBitUnion(McgCap)
 604
 605     BitUnion64(McgStatus)
 606         Bitfield<0> ripv; // Restart-IP valid
 607         Bitfield<1> eipv; // Error-IP valid
 608         Bitfield<2> mcip; // Machine check in-progress
 609     EndBitUnion(McgStatus)
 610
 611     BitUnion64(DebugCtlMsr)
 612         Bitfield<0> lbr; // Last-branch record
 613         Bitfield<1> btf; // Branch single step
 614         Bitfield<2> pb0; // Performance monitoring pin control 0
 615         Bitfield<3> pb1; // Performance monitoring pin control 1
 616         Bitfield<4> pb2; // Performance monitoring pin control 2
 617         Bitfield<5> pb3; // Performance monitoring pin control 3
 618         /*uint64_t pb(int index)
 619         {
 620             return bits(__data, index + 2);
 621         }*/
 622     EndBitUnion(DebugCtlMsr)
 623
 624     BitUnion64(MtrrPhysBase)
 625         Bitfield<7, 0> type; // Default memory type
 626         Bitfield<51, 12> physbase; // Range physical base address
 627     EndBitUnion(MtrrPhysBase)
 628
 629     BitUnion64(MtrrPhysMask)
 630         Bitfield<11> valid; // MTRR pair enable
 631         Bitfield<51, 12> physmask; // Range physical mask
 632     EndBitUnion(MtrrPhysMask)
 633
 634     BitUnion64(MtrrFixed)
 635         /*uint64_t type(int index)
 636         {
 637             return bits(__data, index * 8 + 7, index * 8);
 638         }*/
 639     EndBitUnion(MtrrFixed)
 640
 641     BitUnion64(Pat)
 642         /*uint64_t pa(int index)
 643         {
 644             return bits(__data, index * 8 + 2, index * 8);
 645         }*/
 646     EndBitUnion(Pat)
 647
 648     BitUnion64(MtrrDefType)
 649         Bitfield<7, 0> type; // Default type
 650         Bitfield<10> fe; // Fixed range enable
 651         Bitfield<11> e; // MTRR enable
 652     EndBitUnion(MtrrDefType)
 653
 654     /**
 655      * Machine check
 656      */
 657     BitUnion64(McStatus)
 658         Bitfield<15,0> mcaErrorCode;
 659         Bitfield<31,16> modelSpecificCode;
 660         Bitfield<56,32> otherInfo;
 661         Bitfield<57> pcc; // Processor-context corrupt
 662         Bitfield<58> addrv; // Error-address register valid
 663         Bitfield<59> miscv; // Miscellaneous-error register valid
 664         Bitfield<60> en; // Error condition enabled
 665         Bitfield<61> uc; // Uncorrected error
 666         Bitfield<62> over; // Status register overflow
 667         Bitfield<63> val; // Valid
 668     EndBitUnion(McStatus)
 669
 670     BitUnion64(McCtl)
 671         /*uint64_t en(int index)
 672         {
 673             return bits(__data, index);
 674         }*/
 675     EndBitUnion(McCtl)
 676
 677     // Extended feature enable register
 678     BitUnion64(Efer)
 679         Bitfield<0> sce; // System call extensions
 680         Bitfield<8> lme; // Long mode enable
 681         Bitfield<10> lma; // Long mode active
 682         Bitfield<11> nxe; // No-execute enable
 683         Bitfield<12> svme; // Secure virtual machine enable
 684         Bitfield<14> ffxsr; // Fast fxsave/fxrstor
 685     EndBitUnion(Efer)
 686
 687     BitUnion64(Star)
 688         Bitfield<31,0> targetEip;
 689         Bitfield<47,32> syscallCsAndSs;
 690         Bitfield<63,48> sysretCsAndSs;
 691     EndBitUnion(Star)
 692
 693     BitUnion64(SfMask)
 694         Bitfield<31,0> mask;
 695     EndBitUnion(SfMask)
 696
 697     BitUnion64(PerfEvtSel)
 698         Bitfield<7,0> eventMask;
 699         Bitfield<15,8> unitMask;
 700         Bitfield<16> usr; // User mode
 701         Bitfield<17> os; // Operating-system mode
 702         Bitfield<18> e; // Edge detect
 703         Bitfield<19> pc; // Pin control
 704         Bitfield<20> intEn; // Interrupt enable
 705         Bitfield<22> en; // Counter enable
 706         Bitfield<23> inv; // Invert mask
 707         Bitfield<31,24> counterMask;
 708     EndBitUnion(PerfEvtSel)
 709
 710     BitUnion32(Syscfg)
 711         Bitfield<18> mfde; // MtrrFixDramEn
 712         Bitfield<19> mfdm; // MtrrFixDramModEn
 713         Bitfield<20> mvdm; // MtrrVarDramEn
 714         Bitfield<21> tom2; // MtrrTom2En
 715     EndBitUnion(Syscfg)
 716
 717     BitUnion64(IorrBase)
 718         Bitfield<3> wr; // WrMem Enable
 719         Bitfield<4> rd; // RdMem Enable
 720         Bitfield<51,12> physbase; // Range physical base address
 721     EndBitUnion(IorrBase)
 722
 723     BitUnion64(IorrMask)
 724         Bitfield<11> v; // I/O register pair enable (valid)
 725         Bitfield<51,12> physmask; // Range physical mask
 726     EndBitUnion(IorrMask)
 727
 728     BitUnion64(Tom)
 729         Bitfield<51,23> physAddr; // Top of memory physical address
 730     EndBitUnion(Tom)
 731
 732     BitUnion64(VmCrMsr)
 733         Bitfield<0> dpd;
 734         Bitfield<1> rInit;
 735         Bitfield<2> disA20M;
 736     EndBitUnion(VmCrMsr)
 737
 738     BitUnion64(IgnneMsr)
 739         Bitfield<0> ignne;
 740     EndBitUnion(IgnneMsr)
 741
 742     BitUnion64(SmmCtlMsr)
 743         Bitfield<0> dismiss;
 744         Bitfield<1> enter;
 745         Bitfield<2> smiCycle;
 746         Bitfield<3> exit;
 747         Bitfield<4> rsmCycle;
 748     EndBitUnion(SmmCtlMsr)
 749
 750     /**
 751      * Segment Selector
 752      */
 753     BitUnion64(SegSelector)
 754         // The following bitfield is not defined in the ISA, but it's useful
 755         // when checking selectors in larger data types to make sure they
 756         // aren't too large.
 757         Bitfield<63, 3> esi; // Extended selector
 758         Bitfield<15, 3> si; // Selector Index
 759         Bitfield<2> ti; // Table Indicator
 760         Bitfield<1, 0> rpl; // Requestor Privilege Level
 761     EndBitUnion(SegSelector)
 762
 763     /**
 764      * Segment Descriptors
 765      */
 766
 767     BitUnion64(SegDescriptor)
 768         Bitfield<63, 56> baseHigh;
 769         Bitfield<39, 16> baseLow;
 770         Bitfield<55> g; // Granularity
 771         Bitfield<54> d; // Default Operand Size
 772         Bitfield<54> b; // Default Operand Size
 773         Bitfield<53> l; // Long Attribute Bit
 774         Bitfield<52> avl; // Available To Software
 775         Bitfield<51, 48> limitHigh;
 776         Bitfield<15, 0> limitLow;
 777         Bitfield<47> p; // Present
 778         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 779         Bitfield<44> s; // System
 780         SubBitUnion(type, 43, 40)
 781             // Specifies whether this descriptor is for code or data.
 782             Bitfield<43> codeOrData;
 783
 784             // These bit fields are for code segments
 785             Bitfield<42> c; // Conforming
 786             Bitfield<41> r; // Readable
 787
 788             // These bit fields are for data segments
 789             Bitfield<42> e; // Expand-Down
 790             Bitfield<41> w; // Writable
 791
 792             // This is used for both code and data segments.
 793             Bitfield<40> a; // Accessed
 794         EndSubBitUnion(type)
 795     EndBitUnion(SegDescriptor)
 796
 797     BitUnion64(SegAttr)
 798         Bitfield<0> writable;
 799         Bitfield<1> readable;
 800         Bitfield<2> expandDown;
 801         Bitfield<4, 3> dpl;
 802         Bitfield<5> defaultSize;
 803         Bitfield<6> longMode;
 804     EndBitUnion(SegAttr)
 805
 806     BitUnion64(GateDescriptor)
 807         Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
 808         Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
 809         Bitfield<31, 16> selector; // Target Code-Segment Selector
 810         Bitfield<47> p; // Present
 811         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 812         Bitfield<43, 40> type;
 813         Bitfield<36, 32> count; // Parameter Count
 814     EndBitUnion(GateDescriptor)
 815
 816     /**
 817      * Descriptor-Table Registers
 818      */
 819     BitUnion64(GDTR)
 820     EndBitUnion(GDTR)
 821
 822     BitUnion64(IDTR)
 823     EndBitUnion(IDTR)
 824
 825     BitUnion64(LDTR)
 826     EndBitUnion(LDTR)
 827
 828     /**
 829      * Task Register
 830      */
 831     BitUnion64(TR)
 832     EndBitUnion(TR)
 833
 834
 835     /**
 836      * Local APIC Base Register
 837      */
 838     BitUnion64(LocalApicBase)
 839         Bitfield<51, 12> base;
 840         Bitfield<11> enable;
 841         Bitfield<8> bsp;
 842     EndBitUnion(LocalApicBase)
 843 };
 844
 845 #endif // __ARCH_X86_INTREGS_HH__