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58 #ifndef __ARCH_X86_MISCREGS_HH__
59 #define __ARCH_X86_MISCREGS_HH__
61 #include "arch/x86/segmentregs.hh"
62 #include "arch/x86/x86_traits.hh"
63 #include "base/bitunion.hh"
65 //These get defined in some system headers (at least termbits.h). That confuses
66 //things here significantly.
88 // Most of these are invalid.
90 MISCREG_CR0 = MISCREG_CR_BASE,
108 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
109 MISCREG_DR0 = MISCREG_DR_BASE,
119 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
122 * Model Specific Registers
124 // Time stamp counter
130 MISCREG_SYSENTER_ESP,
131 MISCREG_SYSENTER_EIP,
137 MISCREG_DEBUG_CTL_MSR,
139 MISCREG_LAST_BRANCH_FROM_IP,
140 MISCREG_LAST_BRANCH_TO_IP,
141 MISCREG_LAST_EXCEPTION_FROM_IP,
142 MISCREG_LAST_EXCEPTION_TO_IP,
144 MISCREG_MTRR_PHYS_BASE_BASE,
145 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
146 MISCREG_MTRR_PHYS_BASE_1,
147 MISCREG_MTRR_PHYS_BASE_2,
148 MISCREG_MTRR_PHYS_BASE_3,
149 MISCREG_MTRR_PHYS_BASE_4,
150 MISCREG_MTRR_PHYS_BASE_5,
151 MISCREG_MTRR_PHYS_BASE_6,
152 MISCREG_MTRR_PHYS_BASE_7,
154 MISCREG_MTRR_PHYS_MASK_BASE,
155 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
156 MISCREG_MTRR_PHYS_MASK_1,
157 MISCREG_MTRR_PHYS_MASK_2,
158 MISCREG_MTRR_PHYS_MASK_3,
159 MISCREG_MTRR_PHYS_MASK_4,
160 MISCREG_MTRR_PHYS_MASK_5,
161 MISCREG_MTRR_PHYS_MASK_6,
162 MISCREG_MTRR_PHYS_MASK_7,
164 MISCREG_MTRR_FIX_64K_00000,
165 MISCREG_MTRR_FIX_16K_80000,
166 MISCREG_MTRR_FIX_16K_A0000,
167 MISCREG_MTRR_FIX_4K_C0000,
168 MISCREG_MTRR_FIX_4K_C8000,
169 MISCREG_MTRR_FIX_4K_D0000,
170 MISCREG_MTRR_FIX_4K_D8000,
171 MISCREG_MTRR_FIX_4K_E0000,
172 MISCREG_MTRR_FIX_4K_E8000,
173 MISCREG_MTRR_FIX_4K_F0000,
174 MISCREG_MTRR_FIX_4K_F8000,
181 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
187 MISCREG_MC_STATUS_BASE,
188 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
194 MISCREG_MC_ADDR_BASE,
195 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
201 MISCREG_MC_MISC_BASE,
202 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
208 // Extended feature enable register
217 MISCREG_KERNEL_GS_BASE,
221 MISCREG_PERF_EVT_SEL_BASE,
222 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
223 MISCREG_PERF_EVT_SEL1,
224 MISCREG_PERF_EVT_SEL2,
225 MISCREG_PERF_EVT_SEL3,
227 MISCREG_PERF_EVT_CTR_BASE,
228 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
229 MISCREG_PERF_EVT_CTR1,
230 MISCREG_PERF_EVT_CTR2,
231 MISCREG_PERF_EVT_CTR3,
235 MISCREG_IORR_BASE_BASE,
236 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
239 MISCREG_IORR_MASK_BASE,
240 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
255 MISCREG_SEG_SEL_BASE,
256 MISCREG_ES = MISCREG_SEG_SEL_BASE,
270 // Hidden segment base field
271 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
272 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
286 // The effective segment base, ie what is actually added to an
287 // address. In 64 bit mode this can be different from the above,
289 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
290 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
297 MISCREG_TSL_EFF_BASE,
298 MISCREG_TSG_EFF_BASE,
302 MISCREG_IDTR_EFF_BASE,
304 // Hidden segment limit field
305 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
306 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
320 // Hidden segment limit attributes
321 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
322 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
336 // Floating point control registers
338 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
340 //XXX Add "Model-Specific Registers"
345 MISCREG_APIC_ID = MISCREG_APIC_START,
346 MISCREG_APIC_VERSION,
347 MISCREG_APIC_TASK_PRIORITY,
348 MISCREG_APIC_ARBITRATION_PRIORITY,
349 MISCREG_APIC_PROCESSOR_PRIORITY,
351 MISCREG_APIC_LOGICAL_DESTINATION,
352 MISCREG_APIC_DESTINATION_FORMAT,
353 MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR,
355 MISCREG_APIC_IN_SERVICE_BASE,
357 MISCREG_APIC_TRIGGER_MODE_BASE = MISCREG_APIC_IN_SERVICE_BASE + 16,
359 MISCREG_APIC_INTERRUPT_REQUEST_BASE =
360 MISCREG_APIC_TRIGGER_MODE_BASE + 16,
362 MISCREG_APIC_ERROR_STATUS = MISCREG_APIC_INTERRUPT_REQUEST_BASE + 16,
363 MISCREG_APIC_INTERRUPT_COMMAND_LOW,
364 MISCREG_APIC_INTERRUPT_COMMAND_HIGH,
365 MISCREG_APIC_LVT_TIMER,
366 MISCREG_APIC_LVT_THERMAL_SENSOR,
367 MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS,
368 MISCREG_APIC_LVT_LINT0,
369 MISCREG_APIC_LVT_LINT1,
370 MISCREG_APIC_LVT_ERROR,
371 MISCREG_APIC_INITIAL_COUNT,
372 MISCREG_APIC_CURRENT_COUNT,
373 MISCREG_APIC_DIVIDE_COUNT,
374 MISCREG_APIC_END = MISCREG_APIC_DIVIDE_COUNT,
376 MISCREG_APIC_INTERNAL_STATE,
378 // "Fake" MSRs for internally implemented devices
379 MISCREG_PCI_CONFIG_ADDRESS,
384 static inline MiscRegIndex
385 MISCREG_CR(int index)
387 return (MiscRegIndex)(MISCREG_CR_BASE + index);
390 static inline MiscRegIndex
391 MISCREG_DR(int index)
393 return (MiscRegIndex)(MISCREG_DR_BASE + index);
396 static inline MiscRegIndex
397 MISCREG_MTRR_PHYS_BASE(int index)
399 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
402 static inline MiscRegIndex
403 MISCREG_MTRR_PHYS_MASK(int index)
405 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
408 static inline MiscRegIndex
409 MISCREG_MC_CTL(int index)
411 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
414 static inline MiscRegIndex
415 MISCREG_MC_STATUS(int index)
417 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
420 static inline MiscRegIndex
421 MISCREG_MC_ADDR(int index)
423 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
426 static inline MiscRegIndex
427 MISCREG_MC_MISC(int index)
429 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
432 static inline MiscRegIndex
433 MISCREG_PERF_EVT_SEL(int index)
435 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
438 static inline MiscRegIndex
439 MISCREG_PERF_EVT_CTR(int index)
441 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
444 static inline MiscRegIndex
445 MISCREG_IORR_BASE(int index)
447 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
450 static inline MiscRegIndex
451 MISCREG_IORR_MASK(int index)
453 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
456 static inline MiscRegIndex
457 MISCREG_SEG_SEL(int index)
459 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
462 static inline MiscRegIndex
463 MISCREG_SEG_BASE(int index)
465 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
468 static inline MiscRegIndex
469 MISCREG_SEG_EFF_BASE(int index)
471 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
474 static inline MiscRegIndex
475 MISCREG_SEG_LIMIT(int index)
477 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
480 static inline MiscRegIndex
481 MISCREG_SEG_ATTR(int index)
483 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
486 static inline MiscRegIndex
487 MISCREG_APIC_IN_SERVICE(int index)
489 return (MiscRegIndex)(MISCREG_APIC_IN_SERVICE_BASE + index);
492 static inline MiscRegIndex
493 MISCREG_APIC_TRIGGER_MODE(int index)
495 return (MiscRegIndex)(MISCREG_APIC_TRIGGER_MODE_BASE + index);
498 static inline MiscRegIndex
499 MISCREG_APIC_INTERRUPT_REQUEST(int index)
501 return (MiscRegIndex)(MISCREG_APIC_INTERRUPT_REQUEST_BASE + index);
505 * A type to describe the condition code bits of the RFLAGS register,
506 * plus two flags, EZF and ECF, which are only visible to microcode.
508 BitUnion64(CCFlagBits)
517 EndBitUnion(CCFlagBits)
523 Bitfield<21> id; // ID Flag
524 Bitfield<20> vip; // Virtual Interrupt Pending
525 Bitfield<19> vif; // Virtual Interrupt Flag
526 Bitfield<18> ac; // Alignment Check
527 Bitfield<17> vm; // Virtual-8086 Mode
528 Bitfield<16> rf; // Resume Flag
529 Bitfield<14> nt; // Nested Task
530 Bitfield<13, 12> iopl; // I/O Privilege Level
531 Bitfield<11> of; // Overflow Flag
532 Bitfield<10> df; // Direction Flag
533 Bitfield<9> intf; // Interrupt Flag
534 Bitfield<8> tf; // Trap Flag
535 Bitfield<7> sf; // Sign Flag
536 Bitfield<6> zf; // Zero Flag
537 Bitfield<4> af; // Auxiliary Flag
538 Bitfield<2> pf; // Parity Flag
539 Bitfield<0> cf; // Carry Flag
546 Bitfield<31> pg; // Paging
547 Bitfield<30> cd; // Cache Disable
548 Bitfield<29> nw; // Not Writethrough
549 Bitfield<18> am; // Alignment Mask
550 Bitfield<16> wp; // Write Protect
551 Bitfield<5> ne; // Numeric Error
552 Bitfield<4> et; // Extension Type
553 Bitfield<3> ts; // Task Switched
554 Bitfield<2> em; // Emulation
555 Bitfield<1> mp; // Monitor Coprocessor
556 Bitfield<0> pe; // Protection Enabled
559 // Page Fault Virtual Address
561 Bitfield<31, 0> legacy;
565 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
567 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
569 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
571 Bitfield<4> pcd; // Page-Level Cache Disable
572 Bitfield<3> pwt; // Page-Level Writethrough
576 Bitfield<10> osxmmexcpt; // Operating System Unmasked
578 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
579 Bitfield<8> pce; // Performance-Monitoring Counter Enable
580 Bitfield<7> pge; // Page-Global Enable
581 Bitfield<6> mce; // Machine Check Enable
582 Bitfield<5> pae; // Physical-Address Extension
583 Bitfield<4> pse; // Page Size Extensions
584 Bitfield<3> de; // Debugging Extensions
585 Bitfield<2> tsd; // Time Stamp Disable
586 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
587 Bitfield<0> vme; // Virtual-8086 Mode Extensions
591 Bitfield<3, 0> tpr; // Task Priority Register
596 Bitfield<7, 0> vcnt; // Variable-Range Register Count
597 Bitfield<8> fix; // Fixed-Range Registers
598 Bitfield<10> wc; // Write-Combining
602 * SYSENTER configuration registers
604 BitUnion64(SysenterCS)
605 Bitfield<15, 0> targetCS;
606 EndBitUnion(SysenterCS)
608 BitUnion64(SysenterESP)
609 Bitfield<31, 0> targetESP;
610 EndBitUnion(SysenterESP)
612 BitUnion64(SysenterEIP)
613 Bitfield<31, 0> targetEIP;
614 EndBitUnion(SysenterEIP)
617 * Global machine check registers
620 Bitfield<7, 0> count; // Number of error reporting register banks
621 Bitfield<8> MCGCP; // MCG_CTL register present.
624 BitUnion64(McgStatus)
625 Bitfield<0> ripv; // Restart-IP valid
626 Bitfield<1> eipv; // Error-IP valid
627 Bitfield<2> mcip; // Machine check in-progress
628 EndBitUnion(McgStatus)
630 BitUnion64(DebugCtlMsr)
631 Bitfield<0> lbr; // Last-branch record
632 Bitfield<1> btf; // Branch single step
633 Bitfield<2> pb0; // Performance monitoring pin control 0
634 Bitfield<3> pb1; // Performance monitoring pin control 1
635 Bitfield<4> pb2; // Performance monitoring pin control 2
636 Bitfield<5> pb3; // Performance monitoring pin control 3
637 /*uint64_t pb(int index)
639 return bits(__data, index + 2);
641 EndBitUnion(DebugCtlMsr)
643 BitUnion64(MtrrPhysBase)
644 Bitfield<7, 0> type; // Default memory type
645 Bitfield<51, 12> physbase; // Range physical base address
646 EndBitUnion(MtrrPhysBase)
648 BitUnion64(MtrrPhysMask)
649 Bitfield<11> valid; // MTRR pair enable
650 Bitfield<51, 12> physmask; // Range physical mask
651 EndBitUnion(MtrrPhysMask)
653 BitUnion64(MtrrFixed)
654 /*uint64_t type(int index)
656 return bits(__data, index * 8 + 7, index * 8);
658 EndBitUnion(MtrrFixed)
661 /*uint64_t pa(int index)
663 return bits(__data, index * 8 + 2, index * 8);
667 BitUnion64(MtrrDefType)
668 Bitfield<7, 0> type; // Default type
669 Bitfield<10> fe; // Fixed range enable
670 Bitfield<11> e; // MTRR enable
671 EndBitUnion(MtrrDefType)
677 Bitfield<15,0> mcaErrorCode;
678 Bitfield<31,16> modelSpecificCode;
679 Bitfield<56,32> otherInfo;
680 Bitfield<57> pcc; // Processor-context corrupt
681 Bitfield<58> addrv; // Error-address register valid
682 Bitfield<59> miscv; // Miscellaneous-error register valid
683 Bitfield<60> en; // Error condition enabled
684 Bitfield<61> uc; // Uncorrected error
685 Bitfield<62> over; // Status register overflow
686 Bitfield<63> val; // Valid
687 EndBitUnion(McStatus)
690 /*uint64_t en(int index)
692 return bits(__data, index);
696 // Extended feature enable register
698 Bitfield<0> sce; // System call extensions
699 Bitfield<8> lme; // Long mode enable
700 Bitfield<10> lma; // Long mode active
701 Bitfield<11> nxe; // No-execute enable
702 Bitfield<12> svme; // Secure virtual machine enable
703 Bitfield<14> ffxsr; // Fast fxsave/fxrstor
707 Bitfield<31,0> targetEip;
708 Bitfield<47,32> syscallCsAndSs;
709 Bitfield<63,48> sysretCsAndSs;
716 BitUnion64(PerfEvtSel)
717 Bitfield<7,0> eventMask;
718 Bitfield<15,8> unitMask;
719 Bitfield<16> usr; // User mode
720 Bitfield<17> os; // Operating-system mode
721 Bitfield<18> e; // Edge detect
722 Bitfield<19> pc; // Pin control
723 Bitfield<20> intEn; // Interrupt enable
724 Bitfield<22> en; // Counter enable
725 Bitfield<23> inv; // Invert mask
726 Bitfield<31,24> counterMask;
727 EndBitUnion(PerfEvtSel)
730 Bitfield<18> mfde; // MtrrFixDramEn
731 Bitfield<19> mfdm; // MtrrFixDramModEn
732 Bitfield<20> mvdm; // MtrrVarDramEn
733 Bitfield<21> tom2; // MtrrTom2En
737 Bitfield<3> wr; // WrMem Enable
738 Bitfield<4> rd; // RdMem Enable
739 Bitfield<51,12> physbase; // Range physical base address
740 EndBitUnion(IorrBase)
743 Bitfield<11> v; // I/O register pair enable (valid)
744 Bitfield<51,12> physmask; // Range physical mask
745 EndBitUnion(IorrMask)
748 Bitfield<51,23> physAddr; // Top of memory physical address
759 EndBitUnion(IgnneMsr)
761 BitUnion64(SmmCtlMsr)
764 Bitfield<2> smiCycle;
766 Bitfield<4> rsmCycle;
767 EndBitUnion(SmmCtlMsr)
772 BitUnion64(SegSelector)
773 // The following bitfield is not defined in the ISA, but it's useful
774 // when checking selectors in larger data types to make sure they
776 Bitfield<63, 3> esi; // Extended selector
777 Bitfield<15, 3> si; // Selector Index
778 Bitfield<2> ti; // Table Indicator
779 Bitfield<1, 0> rpl; // Requestor Privilege Level
780 EndBitUnion(SegSelector)
783 * Segment Descriptors
786 BitUnion64(SegDescriptor)
787 Bitfield<63, 56> baseHigh;
788 Bitfield<39, 16> baseLow;
789 Bitfield<55> g; // Granularity
790 Bitfield<54> d; // Default Operand Size
791 Bitfield<54> b; // Default Operand Size
792 Bitfield<53> l; // Long Attribute Bit
793 Bitfield<52> avl; // Available To Software
794 Bitfield<51, 48> limitHigh;
795 Bitfield<15, 0> limitLow;
796 Bitfield<47> p; // Present
797 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
798 Bitfield<44> s; // System
799 SubBitUnion(type, 43, 40)
800 // Specifies whether this descriptor is for code or data.
801 Bitfield<43> codeOrData;
803 // These bit fields are for code segments
804 Bitfield<42> c; // Conforming
805 Bitfield<41> r; // Readable
807 // These bit fields are for data segments
808 Bitfield<42> e; // Expand-Down
809 Bitfield<41> w; // Writable
811 // This is used for both code and data segments.
812 Bitfield<40> a; // Accessed
814 EndBitUnion(SegDescriptor)
817 Bitfield<0> writable;
818 Bitfield<1> readable;
819 Bitfield<2> expandDown;
821 Bitfield<5> defaultSize;
822 Bitfield<6> longMode;
825 BitUnion64(GateDescriptor)
826 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
827 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
828 Bitfield<31, 16> selector; // Target Code-Segment Selector
829 Bitfield<47> p; // Present
830 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
831 Bitfield<43, 40> type;
832 Bitfield<36, 32> count; // Parameter Count
833 EndBitUnion(GateDescriptor)
836 * Descriptor-Table Registers
855 * Local APIC Base Register
857 BitUnion64(LocalApicBase)
858 Bitfield<51, 12> base;
861 EndBitUnion(LocalApicBase)
864 #endif // __ARCH_X86_INTREGS_HH__