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58 #ifndef __ARCH_X86_MISCREGS_HH__
59 #define __ARCH_X86_MISCREGS_HH__
61 #include "arch/x86/segmentregs.hh"
62 #include "arch/x86/x86_traits.hh"
63 #include "base/bitunion.hh"
65 //These get defined in some system headers (at least termbits.h). That confuses
66 //things here significantly.
88 // Most of these are invalid.
90 MISCREG_CR0 = MISCREG_CR_BASE,
108 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
109 MISCREG_DR0 = MISCREG_DR_BASE,
119 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
122 * Model Specific Registers
124 // Time stamp counter
130 MISCREG_SYSENTER_ESP,
131 MISCREG_SYSENTER_EIP,
137 MISCREG_DEBUG_CTL_MSR,
139 MISCREG_LAST_BRANCH_FROM_IP,
140 MISCREG_LAST_BRANCH_TO_IP,
141 MISCREG_LAST_EXCEPTION_FROM_IP,
142 MISCREG_LAST_EXCEPTION_TO_IP,
144 MISCREG_MTRR_PHYS_BASE_BASE,
145 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
146 MISCREG_MTRR_PHYS_BASE_1,
147 MISCREG_MTRR_PHYS_BASE_2,
148 MISCREG_MTRR_PHYS_BASE_3,
149 MISCREG_MTRR_PHYS_BASE_4,
150 MISCREG_MTRR_PHYS_BASE_5,
151 MISCREG_MTRR_PHYS_BASE_6,
152 MISCREG_MTRR_PHYS_BASE_7,
154 MISCREG_MTRR_PHYS_MASK_BASE,
155 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
156 MISCREG_MTRR_PHYS_MASK_1,
157 MISCREG_MTRR_PHYS_MASK_2,
158 MISCREG_MTRR_PHYS_MASK_3,
159 MISCREG_MTRR_PHYS_MASK_4,
160 MISCREG_MTRR_PHYS_MASK_5,
161 MISCREG_MTRR_PHYS_MASK_6,
162 MISCREG_MTRR_PHYS_MASK_7,
164 MISCREG_MTRR_FIX_64K_00000,
165 MISCREG_MTRR_FIX_16K_80000,
166 MISCREG_MTRR_FIX_16K_A0000,
167 MISCREG_MTRR_FIX_4K_C0000,
168 MISCREG_MTRR_FIX_4K_C8000,
169 MISCREG_MTRR_FIX_4K_D0000,
170 MISCREG_MTRR_FIX_4K_D8000,
171 MISCREG_MTRR_FIX_4K_E0000,
172 MISCREG_MTRR_FIX_4K_E8000,
173 MISCREG_MTRR_FIX_4K_F0000,
174 MISCREG_MTRR_FIX_4K_F8000,
181 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
187 MISCREG_MC_STATUS_BASE,
188 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
194 MISCREG_MC_ADDR_BASE,
195 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
201 MISCREG_MC_MISC_BASE,
202 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
208 // Extended feature enable register
217 MISCREG_KERNEL_GS_BASE,
221 MISCREG_PERF_EVT_SEL_BASE,
222 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
223 MISCREG_PERF_EVT_SEL1,
224 MISCREG_PERF_EVT_SEL2,
225 MISCREG_PERF_EVT_SEL3,
227 MISCREG_PERF_EVT_CTR_BASE,
228 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
229 MISCREG_PERF_EVT_CTR1,
230 MISCREG_PERF_EVT_CTR2,
231 MISCREG_PERF_EVT_CTR3,
235 MISCREG_IORR_BASE_BASE,
236 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
239 MISCREG_IORR_MASK_BASE,
240 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
255 MISCREG_SEG_SEL_BASE,
256 MISCREG_ES = MISCREG_SEG_SEL_BASE,
270 // Hidden segment base field
271 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
272 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
286 // The effective segment base, ie what is actually added to an
287 // address. In 64 bit mode this can be different from the above,
289 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
290 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
297 MISCREG_TSL_EFF_BASE,
298 MISCREG_TSG_EFF_BASE,
302 MISCREG_IDTR_EFF_BASE,
304 // Hidden segment limit field
305 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
306 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
320 // Hidden segment limit attributes
321 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
322 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
336 // Floating point control registers
338 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
340 //XXX Add "Model-Specific Registers"
342 MISCREG_PCI_CONFIG_ADDRESS,
347 static inline MiscRegIndex
348 MISCREG_CR(int index)
350 return (MiscRegIndex)(MISCREG_CR_BASE + index);
353 static inline MiscRegIndex
354 MISCREG_DR(int index)
356 return (MiscRegIndex)(MISCREG_DR_BASE + index);
359 static inline MiscRegIndex
360 MISCREG_MTRR_PHYS_BASE(int index)
362 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
365 static inline MiscRegIndex
366 MISCREG_MTRR_PHYS_MASK(int index)
368 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
371 static inline MiscRegIndex
372 MISCREG_MC_CTL(int index)
374 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
377 static inline MiscRegIndex
378 MISCREG_MC_STATUS(int index)
380 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
383 static inline MiscRegIndex
384 MISCREG_MC_ADDR(int index)
386 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
389 static inline MiscRegIndex
390 MISCREG_MC_MISC(int index)
392 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
395 static inline MiscRegIndex
396 MISCREG_PERF_EVT_SEL(int index)
398 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
401 static inline MiscRegIndex
402 MISCREG_PERF_EVT_CTR(int index)
404 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
407 static inline MiscRegIndex
408 MISCREG_IORR_BASE(int index)
410 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
413 static inline MiscRegIndex
414 MISCREG_IORR_MASK(int index)
416 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
419 static inline MiscRegIndex
420 MISCREG_SEG_SEL(int index)
422 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
425 static inline MiscRegIndex
426 MISCREG_SEG_BASE(int index)
428 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
431 static inline MiscRegIndex
432 MISCREG_SEG_EFF_BASE(int index)
434 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
437 static inline MiscRegIndex
438 MISCREG_SEG_LIMIT(int index)
440 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
443 static inline MiscRegIndex
444 MISCREG_SEG_ATTR(int index)
446 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
450 * A type to describe the condition code bits of the RFLAGS register,
451 * plus two flags, EZF and ECF, which are only visible to microcode.
453 BitUnion64(CCFlagBits)
462 EndBitUnion(CCFlagBits)
468 Bitfield<21> id; // ID Flag
469 Bitfield<20> vip; // Virtual Interrupt Pending
470 Bitfield<19> vif; // Virtual Interrupt Flag
471 Bitfield<18> ac; // Alignment Check
472 Bitfield<17> vm; // Virtual-8086 Mode
473 Bitfield<16> rf; // Resume Flag
474 Bitfield<14> nt; // Nested Task
475 Bitfield<13, 12> iopl; // I/O Privilege Level
476 Bitfield<11> of; // Overflow Flag
477 Bitfield<10> df; // Direction Flag
478 Bitfield<9> intf; // Interrupt Flag
479 Bitfield<8> tf; // Trap Flag
480 Bitfield<7> sf; // Sign Flag
481 Bitfield<6> zf; // Zero Flag
482 Bitfield<4> af; // Auxiliary Flag
483 Bitfield<2> pf; // Parity Flag
484 Bitfield<0> cf; // Carry Flag
491 Bitfield<31> pg; // Paging
492 Bitfield<30> cd; // Cache Disable
493 Bitfield<29> nw; // Not Writethrough
494 Bitfield<18> am; // Alignment Mask
495 Bitfield<16> wp; // Write Protect
496 Bitfield<5> ne; // Numeric Error
497 Bitfield<4> et; // Extension Type
498 Bitfield<3> ts; // Task Switched
499 Bitfield<2> em; // Emulation
500 Bitfield<1> mp; // Monitor Coprocessor
501 Bitfield<0> pe; // Protection Enabled
504 // Page Fault Virtual Address
506 Bitfield<31, 0> legacy;
510 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
512 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
514 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
516 Bitfield<4> pcd; // Page-Level Cache Disable
517 Bitfield<3> pwt; // Page-Level Writethrough
521 Bitfield<10> osxmmexcpt; // Operating System Unmasked
523 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
524 Bitfield<8> pce; // Performance-Monitoring Counter Enable
525 Bitfield<7> pge; // Page-Global Enable
526 Bitfield<6> mce; // Machine Check Enable
527 Bitfield<5> pae; // Physical-Address Extension
528 Bitfield<4> pse; // Page Size Extensions
529 Bitfield<3> de; // Debugging Extensions
530 Bitfield<2> tsd; // Time Stamp Disable
531 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
532 Bitfield<0> vme; // Virtual-8086 Mode Extensions
536 Bitfield<3, 0> tpr; // Task Priority Register
541 Bitfield<7, 0> vcnt; // Variable-Range Register Count
542 Bitfield<8> fix; // Fixed-Range Registers
543 Bitfield<10> wc; // Write-Combining
547 * SYSENTER configuration registers
549 BitUnion64(SysenterCS)
550 Bitfield<15, 0> targetCS;
551 EndBitUnion(SysenterCS)
553 BitUnion64(SysenterESP)
554 Bitfield<31, 0> targetESP;
555 EndBitUnion(SysenterESP)
557 BitUnion64(SysenterEIP)
558 Bitfield<31, 0> targetEIP;
559 EndBitUnion(SysenterEIP)
562 * Global machine check registers
565 Bitfield<7, 0> count; // Number of error reporting register banks
566 Bitfield<8> MCGCP; // MCG_CTL register present.
569 BitUnion64(McgStatus)
570 Bitfield<0> ripv; // Restart-IP valid
571 Bitfield<1> eipv; // Error-IP valid
572 Bitfield<2> mcip; // Machine check in-progress
573 EndBitUnion(McgStatus)
575 BitUnion64(DebugCtlMsr)
576 Bitfield<0> lbr; // Last-branch record
577 Bitfield<1> btf; // Branch single step
578 Bitfield<2> pb0; // Performance monitoring pin control 0
579 Bitfield<3> pb1; // Performance monitoring pin control 1
580 Bitfield<4> pb2; // Performance monitoring pin control 2
581 Bitfield<5> pb3; // Performance monitoring pin control 3
582 /*uint64_t pb(int index)
584 return bits(__data, index + 2);
586 EndBitUnion(DebugCtlMsr)
588 BitUnion64(MtrrPhysBase)
589 Bitfield<7, 0> type; // Default memory type
590 Bitfield<51, 12> physbase; // Range physical base address
591 EndBitUnion(MtrrPhysBase)
593 BitUnion64(MtrrPhysMask)
594 Bitfield<11> valid; // MTRR pair enable
595 Bitfield<51, 12> physmask; // Range physical mask
596 EndBitUnion(MtrrPhysMask)
598 BitUnion64(MtrrFixed)
599 /*uint64_t type(int index)
601 return bits(__data, index * 8 + 7, index * 8);
603 EndBitUnion(MtrrFixed)
606 /*uint64_t pa(int index)
608 return bits(__data, index * 8 + 2, index * 8);
612 BitUnion64(MtrrDefType)
613 Bitfield<7, 0> type; // Default type
614 Bitfield<10> fe; // Fixed range enable
615 Bitfield<11> e; // MTRR enable
616 EndBitUnion(MtrrDefType)
622 Bitfield<15,0> mcaErrorCode;
623 Bitfield<31,16> modelSpecificCode;
624 Bitfield<56,32> otherInfo;
625 Bitfield<57> pcc; // Processor-context corrupt
626 Bitfield<58> addrv; // Error-address register valid
627 Bitfield<59> miscv; // Miscellaneous-error register valid
628 Bitfield<60> en; // Error condition enabled
629 Bitfield<61> uc; // Uncorrected error
630 Bitfield<62> over; // Status register overflow
631 Bitfield<63> val; // Valid
632 EndBitUnion(McStatus)
635 /*uint64_t en(int index)
637 return bits(__data, index);
641 // Extended feature enable register
643 Bitfield<0> sce; // System call extensions
644 Bitfield<8> lme; // Long mode enable
645 Bitfield<10> lma; // Long mode active
646 Bitfield<11> nxe; // No-execute enable
647 Bitfield<12> svme; // Secure virtual machine enable
648 Bitfield<14> ffxsr; // Fast fxsave/fxrstor
652 Bitfield<31,0> targetEip;
653 Bitfield<47,32> syscallCsAndSs;
654 Bitfield<63,48> sysretCsAndSs;
661 BitUnion64(PerfEvtSel)
662 Bitfield<7,0> eventMask;
663 Bitfield<15,8> unitMask;
664 Bitfield<16> usr; // User mode
665 Bitfield<17> os; // Operating-system mode
666 Bitfield<18> e; // Edge detect
667 Bitfield<19> pc; // Pin control
668 Bitfield<20> intEn; // Interrupt enable
669 Bitfield<22> en; // Counter enable
670 Bitfield<23> inv; // Invert mask
671 Bitfield<31,24> counterMask;
672 EndBitUnion(PerfEvtSel)
675 Bitfield<18> mfde; // MtrrFixDramEn
676 Bitfield<19> mfdm; // MtrrFixDramModEn
677 Bitfield<20> mvdm; // MtrrVarDramEn
678 Bitfield<21> tom2; // MtrrTom2En
682 Bitfield<3> wr; // WrMem Enable
683 Bitfield<4> rd; // RdMem Enable
684 Bitfield<51,12> physbase; // Range physical base address
685 EndBitUnion(IorrBase)
688 Bitfield<11> v; // I/O register pair enable (valid)
689 Bitfield<51,12> physmask; // Range physical mask
690 EndBitUnion(IorrMask)
693 Bitfield<51,23> physAddr; // Top of memory physical address
704 EndBitUnion(IgnneMsr)
706 BitUnion64(SmmCtlMsr)
709 Bitfield<2> smiCycle;
711 Bitfield<4> rsmCycle;
712 EndBitUnion(SmmCtlMsr)
717 BitUnion64(SegSelector)
718 // The following bitfield is not defined in the ISA, but it's useful
719 // when checking selectors in larger data types to make sure they
721 Bitfield<63, 3> esi; // Extended selector
722 Bitfield<15, 3> si; // Selector Index
723 Bitfield<2> ti; // Table Indicator
724 Bitfield<1, 0> rpl; // Requestor Privilege Level
725 EndBitUnion(SegSelector)
728 * Segment Descriptors
731 BitUnion64(SegDescriptor)
732 Bitfield<63, 56> baseHigh;
733 Bitfield<39, 16> baseLow;
734 Bitfield<55> g; // Granularity
735 Bitfield<54> d; // Default Operand Size
736 Bitfield<54> b; // Default Operand Size
737 Bitfield<53> l; // Long Attribute Bit
738 Bitfield<52> avl; // Available To Software
739 Bitfield<51, 48> limitHigh;
740 Bitfield<15, 0> limitLow;
741 Bitfield<47> p; // Present
742 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
743 Bitfield<44> s; // System
744 SubBitUnion(type, 43, 40)
745 // Specifies whether this descriptor is for code or data.
746 Bitfield<43> codeOrData;
748 // These bit fields are for code segments
749 Bitfield<42> c; // Conforming
750 Bitfield<41> r; // Readable
752 // These bit fields are for data segments
753 Bitfield<42> e; // Expand-Down
754 Bitfield<41> w; // Writable
756 // This is used for both code and data segments.
757 Bitfield<40> a; // Accessed
759 EndBitUnion(SegDescriptor)
762 Bitfield<0> writable;
763 Bitfield<1> readable;
764 Bitfield<2> expandDown;
766 Bitfield<5> defaultSize;
767 Bitfield<6> longMode;
770 BitUnion64(GateDescriptor)
771 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
772 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
773 Bitfield<31, 16> selector; // Target Code-Segment Selector
774 Bitfield<47> p; // Present
775 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
776 Bitfield<43, 40> type;
777 Bitfield<36, 32> count; // Parameter Count
778 EndBitUnion(GateDescriptor)
781 * Descriptor-Table Registers
799 #endif // __ARCH_X86_INTREGS_HH__