src/arch/x86/miscregs.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
   7  * following conditions are met:
   8  *
   9  * The software must be used only for Non-Commercial Use which means any
  10  * use which is NOT directed to receiving any direct monetary
  11  * compensation for, or commercial advantage from such use.  Illustrative
  12  * examples of non-commercial use are academic research, personal study,
  13  * teaching, education and corporate research & development.
  14  * Illustrative examples of commercial use are distributing products for
  15  * commercial advantage and providing services using the software for
  16  * commercial advantage.
  17  *
  18  * If you wish to use this software or functionality therein that may be
  19  * covered by patents for commercial use, please contact:
  20  *     Director of Intellectual Property Licensing
  21  *     Office of Strategy and Technology
  22  *     Hewlett-Packard Company
  23  *     1501 Page Mill Road
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  25  *
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  28  * in binary form must reproduce the above copyright notice, this list of
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  31  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  32  * contributors may be used to endorse or promote products derived from
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  35  * output created using the software may be prepared, but only for
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  38  * conditions herein which includes the Non-Commercial Use restrictions;
  39  * and (ii) such Derivatives of the software include the above copyright
  40  * notice to acknowledge the contribution from this software where
  41  * applicable, this list of conditions and the disclaimer below.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_MISCREGS_HH__
  59 #define __ARCH_X86_MISCREGS_HH__
  60
  61 #include "arch/x86/segmentregs.hh"
  62 #include "arch/x86/x86_traits.hh"
  63 #include "base/bitunion.hh"
  64
  65 //These get defined in some system headers (at least termbits.h). That confuses
  66 //things here significantly.
  67 #undef CR0
  68 #undef CR2
  69 #undef CR3
  70
  71 namespace X86ISA
  72 {
  73     enum CondFlagBit {
  74         CFBit = 1 << 0,
  75         PFBit = 1 << 2,
  76         ECFBit = 1 << 3,
  77         AFBit = 1 << 4,
  78         EZFBit = 1 << 5,
  79         ZFBit = 1 << 6,
  80         SFBit = 1 << 7,
  81         DFBit = 1 << 10,
  82         OFBit = 1 << 11
  83     };
  84
  85     enum MiscRegIndex
  86     {
  87         // Control registers
  88         // Most of these are invalid.
  89         MISCREG_CR_BASE,
  90         MISCREG_CR0 = MISCREG_CR_BASE,
  91         MISCREG_CR1,
  92         MISCREG_CR2,
  93         MISCREG_CR3,
  94         MISCREG_CR4,
  95         MISCREG_CR5,
  96         MISCREG_CR6,
  97         MISCREG_CR7,
  98         MISCREG_CR8,
  99         MISCREG_CR9,
 100         MISCREG_CR10,
 101         MISCREG_CR11,
 102         MISCREG_CR12,
 103         MISCREG_CR13,
 104         MISCREG_CR14,
 105         MISCREG_CR15,
 106
 107         // Debug registers
 108         MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
 109         MISCREG_DR0 = MISCREG_DR_BASE,
 110         MISCREG_DR1,
 111         MISCREG_DR2,
 112         MISCREG_DR3,
 113         MISCREG_DR4,
 114         MISCREG_DR5,
 115         MISCREG_DR6,
 116         MISCREG_DR7,
 117
 118         // Flags register
 119         MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
 120
 121         /*
 122          * Model Specific Registers
 123          */
 124         // Time stamp counter
 125         MISCREG_TSC,
 126
 127         MISCREG_MTRRCAP,
 128
 129         MISCREG_SYSENTER_CS,
 130         MISCREG_SYSENTER_ESP,
 131         MISCREG_SYSENTER_EIP,
 132
 133         MISCREG_MCG_CAP,
 134         MISCREG_MCG_STATUS,
 135         MISCREG_MCG_CTL,
 136
 137         MISCREG_DEBUG_CTL_MSR,
 138
 139         MISCREG_LAST_BRANCH_FROM_IP,
 140         MISCREG_LAST_BRANCH_TO_IP,
 141         MISCREG_LAST_EXCEPTION_FROM_IP,
 142         MISCREG_LAST_EXCEPTION_TO_IP,
 143
 144         MISCREG_MTRR_PHYS_BASE_BASE,
 145         MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
 146         MISCREG_MTRR_PHYS_BASE_1,
 147         MISCREG_MTRR_PHYS_BASE_2,
 148         MISCREG_MTRR_PHYS_BASE_3,
 149         MISCREG_MTRR_PHYS_BASE_4,
 150         MISCREG_MTRR_PHYS_BASE_5,
 151         MISCREG_MTRR_PHYS_BASE_6,
 152         MISCREG_MTRR_PHYS_BASE_7,
 153
 154         MISCREG_MTRR_PHYS_MASK_BASE,
 155         MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
 156         MISCREG_MTRR_PHYS_MASK_1,
 157         MISCREG_MTRR_PHYS_MASK_2,
 158         MISCREG_MTRR_PHYS_MASK_3,
 159         MISCREG_MTRR_PHYS_MASK_4,
 160         MISCREG_MTRR_PHYS_MASK_5,
 161         MISCREG_MTRR_PHYS_MASK_6,
 162         MISCREG_MTRR_PHYS_MASK_7,
 163
 164         MISCREG_MTRR_FIX_64K_00000,
 165         MISCREG_MTRR_FIX_16K_80000,
 166         MISCREG_MTRR_FIX_16K_A0000,
 167         MISCREG_MTRR_FIX_4K_C0000,
 168         MISCREG_MTRR_FIX_4K_C8000,
 169         MISCREG_MTRR_FIX_4K_D0000,
 170         MISCREG_MTRR_FIX_4K_D8000,
 171         MISCREG_MTRR_FIX_4K_E0000,
 172         MISCREG_MTRR_FIX_4K_E8000,
 173         MISCREG_MTRR_FIX_4K_F0000,
 174         MISCREG_MTRR_FIX_4K_F8000,
 175
 176         MISCREG_PAT,
 177
 178         MISCREG_DEF_TYPE,
 179
 180         MISCREG_MC_CTL_BASE,
 181         MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
 182         MISCREG_MC1_CTL,
 183         MISCREG_MC2_CTL,
 184         MISCREG_MC3_CTL,
 185         MISCREG_MC4_CTL,
 186
 187         MISCREG_MC_STATUS_BASE,
 188         MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
 189         MISCREG_MC1_STATUS,
 190         MISCREG_MC2_STATUS,
 191         MISCREG_MC3_STATUS,
 192         MISCREG_MC4_STATUS,
 193
 194         MISCREG_MC_ADDR_BASE,
 195         MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
 196         MISCREG_MC1_ADDR,
 197         MISCREG_MC2_ADDR,
 198         MISCREG_MC3_ADDR,
 199         MISCREG_MC4_ADDR,
 200
 201         MISCREG_MC_MISC_BASE,
 202         MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
 203         MISCREG_MC1_MISC,
 204         MISCREG_MC2_MISC,
 205         MISCREG_MC3_MISC,
 206         MISCREG_MC4_MISC,
 207
 208         // Extended feature enable register
 209         MISCREG_EFER,
 210
 211         MISCREG_STAR,
 212         MISCREG_LSTAR,
 213         MISCREG_CSTAR,
 214
 215         MISCREG_SF_MASK,
 216
 217         MISCREG_KERNEL_GS_BASE,
 218
 219         MISCREG_TSC_AUX,
 220
 221         MISCREG_PERF_EVT_SEL_BASE,
 222         MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
 223         MISCREG_PERF_EVT_SEL1,
 224         MISCREG_PERF_EVT_SEL2,
 225         MISCREG_PERF_EVT_SEL3,
 226
 227         MISCREG_PERF_EVT_CTR_BASE,
 228         MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
 229         MISCREG_PERF_EVT_CTR1,
 230         MISCREG_PERF_EVT_CTR2,
 231         MISCREG_PERF_EVT_CTR3,
 232
 233         MISCREG_SYSCFG,
 234
 235         MISCREG_IORR_BASE_BASE,
 236         MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
 237         MISCREG_IORR_BASE1,
 238
 239         MISCREG_IORR_MASK_BASE,
 240         MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
 241         MISCREG_IORR_MASK1,
 242
 243         MISCREG_TOP_MEM,
 244         MISCREG_TOP_MEM2,
 245
 246         MISCREG_VM_CR,
 247         MISCREG_IGNNE,
 248         MISCREG_SMM_CTL,
 249         MISCREG_VM_HSAVE_PA,
 250
 251         /*
 252          * Segment registers
 253          */
 254         // Segment selectors
 255         MISCREG_SEG_SEL_BASE,
 256         MISCREG_ES = MISCREG_SEG_SEL_BASE,
 257         MISCREG_CS,
 258         MISCREG_SS,
 259         MISCREG_DS,
 260         MISCREG_FS,
 261         MISCREG_GS,
 262         MISCREG_HS,
 263         MISCREG_TSL,
 264         MISCREG_TSG,
 265         MISCREG_LS,
 266         MISCREG_MS,
 267         MISCREG_TR,
 268         MISCREG_IDTR,
 269
 270         // Hidden segment base field
 271         MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
 272         MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
 273         MISCREG_CS_BASE,
 274         MISCREG_SS_BASE,
 275         MISCREG_DS_BASE,
 276         MISCREG_FS_BASE,
 277         MISCREG_GS_BASE,
 278         MISCREG_HS_BASE,
 279         MISCREG_TSL_BASE,
 280         MISCREG_TSG_BASE,
 281         MISCREG_LS_BASE,
 282         MISCREG_MS_BASE,
 283         MISCREG_TR_BASE,
 284         MISCREG_IDTR_BASE,
 285
 286         // The effective segment base, ie what is actually added to an
 287         // address. In 64 bit mode this can be different from the above,
 288         // namely 0.
 289         MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
 290         MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
 291         MISCREG_CS_EFF_BASE,
 292         MISCREG_SS_EFF_BASE,
 293         MISCREG_DS_EFF_BASE,
 294         MISCREG_FS_EFF_BASE,
 295         MISCREG_GS_EFF_BASE,
 296         MISCREG_HS_EFF_BASE,
 297         MISCREG_TSL_EFF_BASE,
 298         MISCREG_TSG_EFF_BASE,
 299         MISCREG_LS_EFF_BASE,
 300         MISCREG_MS_EFF_BASE,
 301         MISCREG_TR_EFF_BASE,
 302         MISCREG_IDTR_EFF_BASE,
 303
 304         // Hidden segment limit field
 305         MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
 306         MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
 307         MISCREG_CS_LIMIT,
 308         MISCREG_SS_LIMIT,
 309         MISCREG_DS_LIMIT,
 310         MISCREG_FS_LIMIT,
 311         MISCREG_GS_LIMIT,
 312         MISCREG_HS_LIMIT,
 313         MISCREG_TSL_LIMIT,
 314         MISCREG_TSG_LIMIT,
 315         MISCREG_LS_LIMIT,
 316         MISCREG_MS_LIMIT,
 317         MISCREG_TR_LIMIT,
 318         MISCREG_IDTR_LIMIT,
 319
 320         // Hidden segment limit attributes
 321         MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
 322         MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
 323         MISCREG_CS_ATTR,
 324         MISCREG_SS_ATTR,
 325         MISCREG_DS_ATTR,
 326         MISCREG_FS_ATTR,
 327         MISCREG_GS_ATTR,
 328         MISCREG_HS_ATTR,
 329         MISCREG_TSL_ATTR,
 330         MISCREG_TSG_ATTR,
 331         MISCREG_LS_ATTR,
 332         MISCREG_MS_ATTR,
 333         MISCREG_TR_ATTR,
 334         MISCREG_IDTR_ATTR,
 335
 336         // Floating point control registers
 337         MISCREG_X87_TOP =
 338             MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
 339
 340         //XXX Add "Model-Specific Registers"
 341
 342         MISCREG_PCI_CONFIG_ADDRESS,
 343
 344         NUM_MISCREGS
 345     };
 346
 347     static inline MiscRegIndex
 348     MISCREG_CR(int index)
 349     {
 350         return (MiscRegIndex)(MISCREG_CR_BASE + index);
 351     }
 352
 353     static inline MiscRegIndex
 354     MISCREG_DR(int index)
 355     {
 356         return (MiscRegIndex)(MISCREG_DR_BASE + index);
 357     }
 358
 359     static inline MiscRegIndex
 360     MISCREG_MTRR_PHYS_BASE(int index)
 361     {
 362         return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
 363     }
 364
 365     static inline MiscRegIndex
 366     MISCREG_MTRR_PHYS_MASK(int index)
 367     {
 368         return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
 369     }
 370
 371     static inline MiscRegIndex
 372     MISCREG_MC_CTL(int index)
 373     {
 374         return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
 375     }
 376
 377     static inline MiscRegIndex
 378     MISCREG_MC_STATUS(int index)
 379     {
 380         return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
 381     }
 382
 383     static inline MiscRegIndex
 384     MISCREG_MC_ADDR(int index)
 385     {
 386         return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
 387     }
 388
 389     static inline MiscRegIndex
 390     MISCREG_MC_MISC(int index)
 391     {
 392         return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
 393     }
 394
 395     static inline MiscRegIndex
 396     MISCREG_PERF_EVT_SEL(int index)
 397     {
 398         return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
 399     }
 400
 401     static inline MiscRegIndex
 402     MISCREG_PERF_EVT_CTR(int index)
 403     {
 404         return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
 405     }
 406
 407     static inline MiscRegIndex
 408     MISCREG_IORR_BASE(int index)
 409     {
 410         return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
 411     }
 412
 413     static inline MiscRegIndex
 414     MISCREG_IORR_MASK(int index)
 415     {
 416         return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
 417     }
 418
 419     static inline MiscRegIndex
 420     MISCREG_SEG_SEL(int index)
 421     {
 422         return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
 423     }
 424
 425     static inline MiscRegIndex
 426     MISCREG_SEG_BASE(int index)
 427     {
 428         return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
 429     }
 430
 431     static inline MiscRegIndex
 432     MISCREG_SEG_EFF_BASE(int index)
 433     {
 434         return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
 435     }
 436
 437     static inline MiscRegIndex
 438     MISCREG_SEG_LIMIT(int index)
 439     {
 440         return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
 441     }
 442
 443     static inline MiscRegIndex
 444     MISCREG_SEG_ATTR(int index)
 445     {
 446         return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
 447     }
 448
 449     /**
 450      * A type to describe the condition code bits of the RFLAGS register,
 451      * plus two flags, EZF and ECF, which are only visible to microcode.
 452      */
 453     BitUnion64(CCFlagBits)
 454         Bitfield<11> of;
 455         Bitfield<7> sf;
 456         Bitfield<6> zf;
 457         Bitfield<5> ezf;
 458         Bitfield<4> af;
 459         Bitfield<3> ecf;
 460         Bitfield<2> pf;
 461         Bitfield<0> cf;
 462     EndBitUnion(CCFlagBits)
 463
 464     /**
 465      * RFLAGS
 466      */
 467     BitUnion64(RFLAGS)
 468         Bitfield<21> id; // ID Flag
 469         Bitfield<20> vip; // Virtual Interrupt Pending
 470         Bitfield<19> vif; // Virtual Interrupt Flag
 471         Bitfield<18> ac; // Alignment Check
 472         Bitfield<17> vm; // Virtual-8086 Mode
 473         Bitfield<16> rf; // Resume Flag
 474         Bitfield<14> nt; // Nested Task
 475         Bitfield<13, 12> iopl; // I/O Privilege Level
 476         Bitfield<11> of; // Overflow Flag
 477         Bitfield<10> df; // Direction Flag
 478         Bitfield<9> intf; // Interrupt Flag
 479         Bitfield<8> tf; // Trap Flag
 480         Bitfield<7> sf; // Sign Flag
 481         Bitfield<6> zf; // Zero Flag
 482         Bitfield<4> af; // Auxiliary Flag
 483         Bitfield<2> pf; // Parity Flag
 484         Bitfield<0> cf; // Carry Flag
 485     EndBitUnion(RFLAGS)
 486
 487     /**
 488      * Control registers
 489      */
 490     BitUnion64(CR0)
 491         Bitfield<31> pg; // Paging
 492         Bitfield<30> cd; // Cache Disable
 493         Bitfield<29> nw; // Not Writethrough
 494         Bitfield<18> am; // Alignment Mask
 495         Bitfield<16> wp; // Write Protect
 496         Bitfield<5> ne; // Numeric Error
 497         Bitfield<4> et; // Extension Type
 498         Bitfield<3> ts; // Task Switched
 499         Bitfield<2> em; // Emulation
 500         Bitfield<1> mp; // Monitor Coprocessor
 501         Bitfield<0> pe; // Protection Enabled
 502     EndBitUnion(CR0)
 503
 504     // Page Fault Virtual Address
 505     BitUnion64(CR2)
 506         Bitfield<31, 0> legacy;
 507     EndBitUnion(CR2)
 508
 509     BitUnion64(CR3)
 510         Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
 511                                    // Base Address
 512         Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
 513                                // Base Address
 514         Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
 515                                  // Base Address
 516         Bitfield<4> pcd; // Page-Level Cache Disable
 517         Bitfield<3> pwt; // Page-Level Writethrough
 518     EndBitUnion(CR3)
 519
 520     BitUnion64(CR4)
 521         Bitfield<10> osxmmexcpt; // Operating System Unmasked
 522                                  // Exception Support
 523         Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
 524         Bitfield<8> pce; // Performance-Monitoring Counter Enable
 525         Bitfield<7> pge; // Page-Global Enable
 526         Bitfield<6> mce; // Machine Check Enable
 527         Bitfield<5> pae; // Physical-Address Extension
 528         Bitfield<4> pse; // Page Size Extensions
 529         Bitfield<3> de; // Debugging Extensions
 530         Bitfield<2> tsd; // Time Stamp Disable
 531         Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
 532         Bitfield<0> vme; // Virtual-8086 Mode Extensions
 533     EndBitUnion(CR4)
 534
 535     BitUnion64(CR8)
 536         Bitfield<3, 0> tpr; // Task Priority Register
 537     EndBitUnion(CR8)
 538
 539     // MTRR capabilities
 540     BitUnion64(MTRRcap)
 541         Bitfield<7, 0> vcnt; // Variable-Range Register Count
 542         Bitfield<8> fix; // Fixed-Range Registers
 543         Bitfield<10> wc; // Write-Combining
 544     EndBitUnion(MTRRcap)
 545
 546     /**
 547      * SYSENTER configuration registers
 548      */
 549     BitUnion64(SysenterCS)
 550         Bitfield<15, 0> targetCS;
 551     EndBitUnion(SysenterCS)
 552
 553     BitUnion64(SysenterESP)
 554         Bitfield<31, 0> targetESP;
 555     EndBitUnion(SysenterESP)
 556
 557     BitUnion64(SysenterEIP)
 558         Bitfield<31, 0> targetEIP;
 559     EndBitUnion(SysenterEIP)
 560
 561     /**
 562      * Global machine check registers
 563      */
 564     BitUnion64(McgCap)
 565         Bitfield<7, 0> count; // Number of error reporting register banks
 566         Bitfield<8> MCGCP; // MCG_CTL register present.
 567     EndBitUnion(McgCap)
 568
 569     BitUnion64(McgStatus)
 570         Bitfield<0> ripv; // Restart-IP valid
 571         Bitfield<1> eipv; // Error-IP valid
 572         Bitfield<2> mcip; // Machine check in-progress
 573     EndBitUnion(McgStatus)
 574
 575     BitUnion64(DebugCtlMsr)
 576         Bitfield<0> lbr; // Last-branch record
 577         Bitfield<1> btf; // Branch single step
 578         Bitfield<2> pb0; // Performance monitoring pin control 0
 579         Bitfield<3> pb1; // Performance monitoring pin control 1
 580         Bitfield<4> pb2; // Performance monitoring pin control 2
 581         Bitfield<5> pb3; // Performance monitoring pin control 3
 582         /*uint64_t pb(int index)
 583         {
 584             return bits(__data, index + 2);
 585         }*/
 586     EndBitUnion(DebugCtlMsr)
 587
 588     BitUnion64(MtrrPhysBase)
 589         Bitfield<7, 0> type; // Default memory type
 590         Bitfield<51, 12> physbase; // Range physical base address
 591     EndBitUnion(MtrrPhysBase)
 592
 593     BitUnion64(MtrrPhysMask)
 594         Bitfield<11> valid; // MTRR pair enable
 595         Bitfield<51, 12> physmask; // Range physical mask
 596     EndBitUnion(MtrrPhysMask)
 597
 598     BitUnion64(MtrrFixed)
 599         /*uint64_t type(int index)
 600         {
 601             return bits(__data, index * 8 + 7, index * 8);
 602         }*/
 603     EndBitUnion(MtrrFixed)
 604
 605     BitUnion64(Pat)
 606         /*uint64_t pa(int index)
 607         {
 608             return bits(__data, index * 8 + 2, index * 8);
 609         }*/
 610     EndBitUnion(Pat)
 611
 612     BitUnion64(MtrrDefType)
 613         Bitfield<7, 0> type; // Default type
 614         Bitfield<10> fe; // Fixed range enable
 615         Bitfield<11> e; // MTRR enable
 616     EndBitUnion(MtrrDefType)
 617
 618     /**
 619      * Machine check
 620      */
 621     BitUnion64(McStatus)
 622         Bitfield<15,0> mcaErrorCode;
 623         Bitfield<31,16> modelSpecificCode;
 624         Bitfield<56,32> otherInfo;
 625         Bitfield<57> pcc; // Processor-context corrupt
 626         Bitfield<58> addrv; // Error-address register valid
 627         Bitfield<59> miscv; // Miscellaneous-error register valid
 628         Bitfield<60> en; // Error condition enabled
 629         Bitfield<61> uc; // Uncorrected error
 630         Bitfield<62> over; // Status register overflow
 631         Bitfield<63> val; // Valid
 632     EndBitUnion(McStatus)
 633
 634     BitUnion64(McCtl)
 635         /*uint64_t en(int index)
 636         {
 637             return bits(__data, index);
 638         }*/
 639     EndBitUnion(McCtl)
 640
 641     // Extended feature enable register
 642     BitUnion64(Efer)
 643         Bitfield<0> sce; // System call extensions
 644         Bitfield<8> lme; // Long mode enable
 645         Bitfield<10> lma; // Long mode active
 646         Bitfield<11> nxe; // No-execute enable
 647         Bitfield<12> svme; // Secure virtual machine enable
 648         Bitfield<14> ffxsr; // Fast fxsave/fxrstor
 649     EndBitUnion(Efer)
 650
 651     BitUnion64(Star)
 652         Bitfield<31,0> targetEip;
 653         Bitfield<47,32> syscallCsAndSs;
 654         Bitfield<63,48> sysretCsAndSs;
 655     EndBitUnion(Star)
 656
 657     BitUnion64(SfMask)
 658         Bitfield<31,0> mask;
 659     EndBitUnion(SfMask)
 660
 661     BitUnion64(PerfEvtSel)
 662         Bitfield<7,0> eventMask;
 663         Bitfield<15,8> unitMask;
 664         Bitfield<16> usr; // User mode
 665         Bitfield<17> os; // Operating-system mode
 666         Bitfield<18> e; // Edge detect
 667         Bitfield<19> pc; // Pin control
 668         Bitfield<20> intEn; // Interrupt enable
 669         Bitfield<22> en; // Counter enable
 670         Bitfield<23> inv; // Invert mask
 671         Bitfield<31,24> counterMask;
 672     EndBitUnion(PerfEvtSel)
 673
 674     BitUnion32(Syscfg)
 675         Bitfield<18> mfde; // MtrrFixDramEn
 676         Bitfield<19> mfdm; // MtrrFixDramModEn
 677         Bitfield<20> mvdm; // MtrrVarDramEn
 678         Bitfield<21> tom2; // MtrrTom2En
 679     EndBitUnion(Syscfg)
 680
 681     BitUnion64(IorrBase)
 682         Bitfield<3> wr; // WrMem Enable
 683         Bitfield<4> rd; // RdMem Enable
 684         Bitfield<51,12> physbase; // Range physical base address
 685     EndBitUnion(IorrBase)
 686
 687     BitUnion64(IorrMask)
 688         Bitfield<11> v; // I/O register pair enable (valid)
 689         Bitfield<51,12> physmask; // Range physical mask
 690     EndBitUnion(IorrMask)
 691
 692     BitUnion64(Tom)
 693         Bitfield<51,23> physAddr; // Top of memory physical address
 694     EndBitUnion(Tom)
 695
 696     BitUnion64(VmCrMsr)
 697         Bitfield<0> dpd;
 698         Bitfield<1> rInit;
 699         Bitfield<2> disA20M;
 700     EndBitUnion(VmCrMsr)
 701
 702     BitUnion64(IgnneMsr)
 703         Bitfield<0> ignne;
 704     EndBitUnion(IgnneMsr)
 705
 706     BitUnion64(SmmCtlMsr)
 707         Bitfield<0> dismiss;
 708         Bitfield<1> enter;
 709         Bitfield<2> smiCycle;
 710         Bitfield<3> exit;
 711         Bitfield<4> rsmCycle;
 712     EndBitUnion(SmmCtlMsr)
 713
 714     /**
 715      * Segment Selector
 716      */
 717     BitUnion64(SegSelector)
 718         // The following bitfield is not defined in the ISA, but it's useful
 719         // when checking selectors in larger data types to make sure they
 720         // aren't too large.
 721         Bitfield<63, 3> esi; // Extended selector
 722         Bitfield<15, 3> si; // Selector Index
 723         Bitfield<2> ti; // Table Indicator
 724         Bitfield<1, 0> rpl; // Requestor Privilege Level
 725     EndBitUnion(SegSelector)
 726
 727     /**
 728      * Segment Descriptors
 729      */
 730
 731     BitUnion64(SegDescriptor)
 732         Bitfield<63, 56> baseHigh;
 733         Bitfield<39, 16> baseLow;
 734         Bitfield<55> g; // Granularity
 735         Bitfield<54> d; // Default Operand Size
 736         Bitfield<54> b; // Default Operand Size
 737         Bitfield<53> l; // Long Attribute Bit
 738         Bitfield<52> avl; // Available To Software
 739         Bitfield<51, 48> limitHigh;
 740         Bitfield<15, 0> limitLow;
 741         Bitfield<47> p; // Present
 742         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 743         Bitfield<44> s; // System
 744         SubBitUnion(type, 43, 40)
 745             // Specifies whether this descriptor is for code or data.
 746             Bitfield<43> codeOrData;
 747
 748             // These bit fields are for code segments
 749             Bitfield<42> c; // Conforming
 750             Bitfield<41> r; // Readable
 751
 752             // These bit fields are for data segments
 753             Bitfield<42> e; // Expand-Down
 754             Bitfield<41> w; // Writable
 755
 756             // This is used for both code and data segments.
 757             Bitfield<40> a; // Accessed
 758         EndSubBitUnion(type)
 759     EndBitUnion(SegDescriptor)
 760
 761     BitUnion64(SegAttr)
 762         Bitfield<0> writable;
 763         Bitfield<1> readable;
 764         Bitfield<2> expandDown;
 765         Bitfield<4, 3> dpl;
 766         Bitfield<5> defaultSize;
 767         Bitfield<6> longMode;
 768     EndBitUnion(SegAttr)
 769
 770     BitUnion64(GateDescriptor)
 771         Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
 772         Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
 773         Bitfield<31, 16> selector; // Target Code-Segment Selector
 774         Bitfield<47> p; // Present
 775         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 776         Bitfield<43, 40> type;
 777         Bitfield<36, 32> count; // Parameter Count
 778     EndBitUnion(GateDescriptor)
 779
 780     /**
 781      * Descriptor-Table Registers
 782      */
 783     BitUnion64(GDTR)
 784     EndBitUnion(GDTR)
 785
 786     BitUnion64(IDTR)
 787     EndBitUnion(IDTR)
 788
 789     BitUnion64(LDTR)
 790     EndBitUnion(LDTR)
 791
 792     /**
 793      * Task Register
 794      */
 795     BitUnion64(TR)
 796     EndBitUnion(TR)
 797 };
 798
 799 #endif // __ARCH_X86_INTREGS_HH__