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58 #ifndef __ARCH_X86_MISCREGS_HH__
59 #define __ARCH_X86_MISCREGS_HH__
61 #include "arch/x86/segmentregs.hh"
62 #include "arch/x86/x86_traits.hh"
63 #include "base/bitunion.hh"
65 //These get defined in some system headers (at least termbits.h). That confuses
66 //things here significantly.
88 // Most of these are invalid.
90 MISCREG_CR0 = MISCREG_CR_BASE,
108 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
109 MISCREG_DR0 = MISCREG_DR_BASE,
119 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
122 * Model Specific Registers
124 // Time stamp counter
130 MISCREG_SYSENTER_ESP,
131 MISCREG_SYSENTER_EIP,
137 MISCREG_DEBUG_CTL_MSR,
139 MISCREG_LAST_BRANCH_FROM_IP,
140 MISCREG_LAST_BRANCH_TO_IP,
141 MISCREG_LAST_EXCEPTION_FROM_IP,
142 MISCREG_LAST_EXCEPTION_TO_IP,
144 MISCREG_MTRR_PHYS_BASE_BASE,
145 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
146 MISCREG_MTRR_PHYS_BASE_1,
147 MISCREG_MTRR_PHYS_BASE_2,
148 MISCREG_MTRR_PHYS_BASE_3,
149 MISCREG_MTRR_PHYS_BASE_4,
150 MISCREG_MTRR_PHYS_BASE_5,
151 MISCREG_MTRR_PHYS_BASE_6,
152 MISCREG_MTRR_PHYS_BASE_7,
154 MISCREG_MTRR_PHYS_MASK_BASE,
155 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
156 MISCREG_MTRR_PHYS_MASK_1,
157 MISCREG_MTRR_PHYS_MASK_2,
158 MISCREG_MTRR_PHYS_MASK_3,
159 MISCREG_MTRR_PHYS_MASK_4,
160 MISCREG_MTRR_PHYS_MASK_5,
161 MISCREG_MTRR_PHYS_MASK_6,
162 MISCREG_MTRR_PHYS_MASK_7,
164 MISCREG_MTRR_FIX_64K_00000,
165 MISCREG_MTRR_FIX_16K_80000,
166 MISCREG_MTRR_FIX_16K_A0000,
167 MISCREG_MTRR_FIX_4K_C0000,
168 MISCREG_MTRR_FIX_4K_C8000,
169 MISCREG_MTRR_FIX_4K_D0000,
170 MISCREG_MTRR_FIX_4K_D8000,
171 MISCREG_MTRR_FIX_4K_E0000,
172 MISCREG_MTRR_FIX_4K_E8000,
173 MISCREG_MTRR_FIX_4K_F0000,
174 MISCREG_MTRR_FIX_4K_F8000,
181 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
190 MISCREG_MC_STATUS_BASE,
191 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
200 MISCREG_MC_ADDR_BASE,
201 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
210 MISCREG_MC_MISC_BASE,
211 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
220 // Extended feature enable register
229 MISCREG_KERNEL_GS_BASE,
233 MISCREG_PERF_EVT_SEL_BASE,
234 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
235 MISCREG_PERF_EVT_SEL1,
236 MISCREG_PERF_EVT_SEL2,
237 MISCREG_PERF_EVT_SEL3,
239 MISCREG_PERF_EVT_CTR_BASE,
240 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
241 MISCREG_PERF_EVT_CTR1,
242 MISCREG_PERF_EVT_CTR2,
243 MISCREG_PERF_EVT_CTR3,
247 MISCREG_IORR_BASE_BASE,
248 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
251 MISCREG_IORR_MASK_BASE,
252 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
267 MISCREG_SEG_SEL_BASE,
268 MISCREG_ES = MISCREG_SEG_SEL_BASE,
282 // Hidden segment base field
283 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
284 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
298 // The effective segment base, ie what is actually added to an
299 // address. In 64 bit mode this can be different from the above,
301 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
302 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
309 MISCREG_TSL_EFF_BASE,
310 MISCREG_TSG_EFF_BASE,
314 MISCREG_IDTR_EFF_BASE,
316 // Hidden segment limit field
317 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
318 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
332 // Hidden segment limit attributes
333 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
334 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
348 // Floating point control registers
350 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
352 //XXX Add "Model-Specific Registers"
357 MISCREG_APIC_ID = MISCREG_APIC_START,
358 MISCREG_APIC_VERSION,
359 MISCREG_APIC_TASK_PRIORITY,
360 MISCREG_APIC_ARBITRATION_PRIORITY,
361 MISCREG_APIC_PROCESSOR_PRIORITY,
363 MISCREG_APIC_LOGICAL_DESTINATION,
364 MISCREG_APIC_DESTINATION_FORMAT,
365 MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR,
367 MISCREG_APIC_IN_SERVICE_BASE,
369 MISCREG_APIC_TRIGGER_MODE_BASE = MISCREG_APIC_IN_SERVICE_BASE + 16,
371 MISCREG_APIC_INTERRUPT_REQUEST_BASE =
372 MISCREG_APIC_TRIGGER_MODE_BASE + 16,
374 MISCREG_APIC_ERROR_STATUS = MISCREG_APIC_INTERRUPT_REQUEST_BASE + 16,
375 MISCREG_APIC_INTERRUPT_COMMAND_LOW,
376 MISCREG_APIC_INTERRUPT_COMMAND_HIGH,
377 MISCREG_APIC_LVT_TIMER,
378 MISCREG_APIC_LVT_THERMAL_SENSOR,
379 MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS,
380 MISCREG_APIC_LVT_LINT0,
381 MISCREG_APIC_LVT_LINT1,
382 MISCREG_APIC_LVT_ERROR,
383 MISCREG_APIC_INITIAL_COUNT,
384 MISCREG_APIC_CURRENT_COUNT,
385 MISCREG_APIC_DIVIDE_COUNT,
386 MISCREG_APIC_END = MISCREG_APIC_DIVIDE_COUNT,
388 MISCREG_APIC_INTERNAL_STATE,
390 // "Fake" MSRs for internally implemented devices
391 MISCREG_PCI_CONFIG_ADDRESS,
396 static inline MiscRegIndex
397 MISCREG_CR(int index)
399 return (MiscRegIndex)(MISCREG_CR_BASE + index);
402 static inline MiscRegIndex
403 MISCREG_DR(int index)
405 return (MiscRegIndex)(MISCREG_DR_BASE + index);
408 static inline MiscRegIndex
409 MISCREG_MTRR_PHYS_BASE(int index)
411 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
414 static inline MiscRegIndex
415 MISCREG_MTRR_PHYS_MASK(int index)
417 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
420 static inline MiscRegIndex
421 MISCREG_MC_CTL(int index)
423 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
426 static inline MiscRegIndex
427 MISCREG_MC_STATUS(int index)
429 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
432 static inline MiscRegIndex
433 MISCREG_MC_ADDR(int index)
435 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
438 static inline MiscRegIndex
439 MISCREG_MC_MISC(int index)
441 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
444 static inline MiscRegIndex
445 MISCREG_PERF_EVT_SEL(int index)
447 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
450 static inline MiscRegIndex
451 MISCREG_PERF_EVT_CTR(int index)
453 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
456 static inline MiscRegIndex
457 MISCREG_IORR_BASE(int index)
459 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
462 static inline MiscRegIndex
463 MISCREG_IORR_MASK(int index)
465 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
468 static inline MiscRegIndex
469 MISCREG_SEG_SEL(int index)
471 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
474 static inline MiscRegIndex
475 MISCREG_SEG_BASE(int index)
477 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
480 static inline MiscRegIndex
481 MISCREG_SEG_EFF_BASE(int index)
483 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
486 static inline MiscRegIndex
487 MISCREG_SEG_LIMIT(int index)
489 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
492 static inline MiscRegIndex
493 MISCREG_SEG_ATTR(int index)
495 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
498 static inline MiscRegIndex
499 MISCREG_APIC_IN_SERVICE(int index)
501 return (MiscRegIndex)(MISCREG_APIC_IN_SERVICE_BASE + index);
504 static inline MiscRegIndex
505 MISCREG_APIC_TRIGGER_MODE(int index)
507 return (MiscRegIndex)(MISCREG_APIC_TRIGGER_MODE_BASE + index);
510 static inline MiscRegIndex
511 MISCREG_APIC_INTERRUPT_REQUEST(int index)
513 return (MiscRegIndex)(MISCREG_APIC_INTERRUPT_REQUEST_BASE + index);
517 * A type to describe the condition code bits of the RFLAGS register,
518 * plus two flags, EZF and ECF, which are only visible to microcode.
520 BitUnion64(CCFlagBits)
529 EndBitUnion(CCFlagBits)
535 Bitfield<21> id; // ID Flag
536 Bitfield<20> vip; // Virtual Interrupt Pending
537 Bitfield<19> vif; // Virtual Interrupt Flag
538 Bitfield<18> ac; // Alignment Check
539 Bitfield<17> vm; // Virtual-8086 Mode
540 Bitfield<16> rf; // Resume Flag
541 Bitfield<14> nt; // Nested Task
542 Bitfield<13, 12> iopl; // I/O Privilege Level
543 Bitfield<11> of; // Overflow Flag
544 Bitfield<10> df; // Direction Flag
545 Bitfield<9> intf; // Interrupt Flag
546 Bitfield<8> tf; // Trap Flag
547 Bitfield<7> sf; // Sign Flag
548 Bitfield<6> zf; // Zero Flag
549 Bitfield<4> af; // Auxiliary Flag
550 Bitfield<2> pf; // Parity Flag
551 Bitfield<0> cf; // Carry Flag
558 Bitfield<31> pg; // Paging
559 Bitfield<30> cd; // Cache Disable
560 Bitfield<29> nw; // Not Writethrough
561 Bitfield<18> am; // Alignment Mask
562 Bitfield<16> wp; // Write Protect
563 Bitfield<5> ne; // Numeric Error
564 Bitfield<4> et; // Extension Type
565 Bitfield<3> ts; // Task Switched
566 Bitfield<2> em; // Emulation
567 Bitfield<1> mp; // Monitor Coprocessor
568 Bitfield<0> pe; // Protection Enabled
571 // Page Fault Virtual Address
573 Bitfield<31, 0> legacy;
577 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
579 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
581 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
583 Bitfield<4> pcd; // Page-Level Cache Disable
584 Bitfield<3> pwt; // Page-Level Writethrough
588 Bitfield<10> osxmmexcpt; // Operating System Unmasked
590 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
591 Bitfield<8> pce; // Performance-Monitoring Counter Enable
592 Bitfield<7> pge; // Page-Global Enable
593 Bitfield<6> mce; // Machine Check Enable
594 Bitfield<5> pae; // Physical-Address Extension
595 Bitfield<4> pse; // Page Size Extensions
596 Bitfield<3> de; // Debugging Extensions
597 Bitfield<2> tsd; // Time Stamp Disable
598 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
599 Bitfield<0> vme; // Virtual-8086 Mode Extensions
603 Bitfield<3, 0> tpr; // Task Priority Register
608 Bitfield<7, 0> vcnt; // Variable-Range Register Count
609 Bitfield<8> fix; // Fixed-Range Registers
610 Bitfield<10> wc; // Write-Combining
614 * SYSENTER configuration registers
616 BitUnion64(SysenterCS)
617 Bitfield<15, 0> targetCS;
618 EndBitUnion(SysenterCS)
620 BitUnion64(SysenterESP)
621 Bitfield<31, 0> targetESP;
622 EndBitUnion(SysenterESP)
624 BitUnion64(SysenterEIP)
625 Bitfield<31, 0> targetEIP;
626 EndBitUnion(SysenterEIP)
629 * Global machine check registers
632 Bitfield<7, 0> count; // Number of error reporting register banks
633 Bitfield<8> MCGCP; // MCG_CTL register present.
636 BitUnion64(McgStatus)
637 Bitfield<0> ripv; // Restart-IP valid
638 Bitfield<1> eipv; // Error-IP valid
639 Bitfield<2> mcip; // Machine check in-progress
640 EndBitUnion(McgStatus)
642 BitUnion64(DebugCtlMsr)
643 Bitfield<0> lbr; // Last-branch record
644 Bitfield<1> btf; // Branch single step
645 Bitfield<2> pb0; // Performance monitoring pin control 0
646 Bitfield<3> pb1; // Performance monitoring pin control 1
647 Bitfield<4> pb2; // Performance monitoring pin control 2
648 Bitfield<5> pb3; // Performance monitoring pin control 3
649 /*uint64_t pb(int index)
651 return bits(__data, index + 2);
653 EndBitUnion(DebugCtlMsr)
655 BitUnion64(MtrrPhysBase)
656 Bitfield<7, 0> type; // Default memory type
657 Bitfield<51, 12> physbase; // Range physical base address
658 EndBitUnion(MtrrPhysBase)
660 BitUnion64(MtrrPhysMask)
661 Bitfield<11> valid; // MTRR pair enable
662 Bitfield<51, 12> physmask; // Range physical mask
663 EndBitUnion(MtrrPhysMask)
665 BitUnion64(MtrrFixed)
666 /*uint64_t type(int index)
668 return bits(__data, index * 8 + 7, index * 8);
670 EndBitUnion(MtrrFixed)
673 /*uint64_t pa(int index)
675 return bits(__data, index * 8 + 2, index * 8);
679 BitUnion64(MtrrDefType)
680 Bitfield<7, 0> type; // Default type
681 Bitfield<10> fe; // Fixed range enable
682 Bitfield<11> e; // MTRR enable
683 EndBitUnion(MtrrDefType)
689 Bitfield<15,0> mcaErrorCode;
690 Bitfield<31,16> modelSpecificCode;
691 Bitfield<56,32> otherInfo;
692 Bitfield<57> pcc; // Processor-context corrupt
693 Bitfield<58> addrv; // Error-address register valid
694 Bitfield<59> miscv; // Miscellaneous-error register valid
695 Bitfield<60> en; // Error condition enabled
696 Bitfield<61> uc; // Uncorrected error
697 Bitfield<62> over; // Status register overflow
698 Bitfield<63> val; // Valid
699 EndBitUnion(McStatus)
702 /*uint64_t en(int index)
704 return bits(__data, index);
708 // Extended feature enable register
710 Bitfield<0> sce; // System call extensions
711 Bitfield<8> lme; // Long mode enable
712 Bitfield<10> lma; // Long mode active
713 Bitfield<11> nxe; // No-execute enable
714 Bitfield<12> svme; // Secure virtual machine enable
715 Bitfield<14> ffxsr; // Fast fxsave/fxrstor
719 Bitfield<31,0> targetEip;
720 Bitfield<47,32> syscallCsAndSs;
721 Bitfield<63,48> sysretCsAndSs;
728 BitUnion64(PerfEvtSel)
729 Bitfield<7,0> eventMask;
730 Bitfield<15,8> unitMask;
731 Bitfield<16> usr; // User mode
732 Bitfield<17> os; // Operating-system mode
733 Bitfield<18> e; // Edge detect
734 Bitfield<19> pc; // Pin control
735 Bitfield<20> intEn; // Interrupt enable
736 Bitfield<22> en; // Counter enable
737 Bitfield<23> inv; // Invert mask
738 Bitfield<31,24> counterMask;
739 EndBitUnion(PerfEvtSel)
742 Bitfield<18> mfde; // MtrrFixDramEn
743 Bitfield<19> mfdm; // MtrrFixDramModEn
744 Bitfield<20> mvdm; // MtrrVarDramEn
745 Bitfield<21> tom2; // MtrrTom2En
749 Bitfield<3> wr; // WrMem Enable
750 Bitfield<4> rd; // RdMem Enable
751 Bitfield<51,12> physbase; // Range physical base address
752 EndBitUnion(IorrBase)
755 Bitfield<11> v; // I/O register pair enable (valid)
756 Bitfield<51,12> physmask; // Range physical mask
757 EndBitUnion(IorrMask)
760 Bitfield<51,23> physAddr; // Top of memory physical address
771 EndBitUnion(IgnneMsr)
773 BitUnion64(SmmCtlMsr)
776 Bitfield<2> smiCycle;
778 Bitfield<4> rsmCycle;
779 EndBitUnion(SmmCtlMsr)
784 BitUnion64(SegSelector)
785 // The following bitfield is not defined in the ISA, but it's useful
786 // when checking selectors in larger data types to make sure they
788 Bitfield<63, 3> esi; // Extended selector
789 Bitfield<15, 3> si; // Selector Index
790 Bitfield<2> ti; // Table Indicator
791 Bitfield<1, 0> rpl; // Requestor Privilege Level
792 EndBitUnion(SegSelector)
795 * Segment Descriptors
798 BitUnion64(SegDescriptor)
799 Bitfield<63, 56> baseHigh;
800 Bitfield<39, 16> baseLow;
801 Bitfield<55> g; // Granularity
802 Bitfield<54> d; // Default Operand Size
803 Bitfield<54> b; // Default Operand Size
804 Bitfield<53> l; // Long Attribute Bit
805 Bitfield<52> avl; // Available To Software
806 Bitfield<51, 48> limitHigh;
807 Bitfield<15, 0> limitLow;
808 Bitfield<47> p; // Present
809 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
810 Bitfield<44> s; // System
811 SubBitUnion(type, 43, 40)
812 // Specifies whether this descriptor is for code or data.
813 Bitfield<43> codeOrData;
815 // These bit fields are for code segments
816 Bitfield<42> c; // Conforming
817 Bitfield<41> r; // Readable
819 // These bit fields are for data segments
820 Bitfield<42> e; // Expand-Down
821 Bitfield<41> w; // Writable
823 // This is used for both code and data segments.
824 Bitfield<40> a; // Accessed
826 EndBitUnion(SegDescriptor)
829 Bitfield<0> writable;
830 Bitfield<1> readable;
831 Bitfield<2> expandDown;
833 Bitfield<5> defaultSize;
834 Bitfield<6> longMode;
837 BitUnion64(GateDescriptor)
838 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
839 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
840 Bitfield<31, 16> selector; // Target Code-Segment Selector
841 Bitfield<47> p; // Present
842 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
843 Bitfield<43, 40> type;
844 Bitfield<36, 32> count; // Parameter Count
845 EndBitUnion(GateDescriptor)
848 * Descriptor-Table Registers
867 * Local APIC Base Register
869 BitUnion64(LocalApicBase)
870 Bitfield<51, 12> base;
873 EndBitUnion(LocalApicBase)
876 #endif // __ARCH_X86_INTREGS_HH__