src/arch/x86/miscregs.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
   7  * following conditions are met:
   8  *
   9  * The software must be used only for Non-Commercial Use which means any
  10  * use which is NOT directed to receiving any direct monetary
  11  * compensation for, or commercial advantage from such use.  Illustrative
  12  * examples of non-commercial use are academic research, personal study,
  13  * teaching, education and corporate research & development.
  14  * Illustrative examples of commercial use are distributing products for
  15  * commercial advantage and providing services using the software for
  16  * commercial advantage.
  17  *
  18  * If you wish to use this software or functionality therein that may be
  19  * covered by patents for commercial use, please contact:
  20  *     Director of Intellectual Property Licensing
  21  *     Office of Strategy and Technology
  22  *     Hewlett-Packard Company
  23  *     1501 Page Mill Road
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  25  *
  26  * Redistributions of source code must retain the above copyright notice,
  27  * this list of conditions and the following disclaimer.  Redistributions
  28  * in binary form must reproduce the above copyright notice, this list of
  29  * conditions and the following disclaimer in the documentation and/or
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  31  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  32  * contributors may be used to endorse or promote products derived from
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  35  * output created using the software may be prepared, but only for
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  38  * conditions herein which includes the Non-Commercial Use restrictions;
  39  * and (ii) such Derivatives of the software include the above copyright
  40  * notice to acknowledge the contribution from this software where
  41  * applicable, this list of conditions and the disclaimer below.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_MISCREGS_HH__
  59 #define __ARCH_X86_MISCREGS_HH__
  60
  61 #include "arch/x86/x86_traits.hh"
  62 #include "base/bitunion.hh"
  63
  64 //These get defined in some system headers (at least termbits.h). That confuses
  65 //things here significantly.
  66 #undef CR0
  67 #undef CR2
  68 #undef CR3
  69
  70 namespace X86ISA
  71 {
  72     enum CondFlagBit {
  73         CFBit = 1 << 0,
  74         PFBit = 1 << 2,
  75         ECFBit = 1 << 3,
  76         AFBit = 1 << 4,
  77         EZFBit = 1 << 5,
  78         ZFBit = 1 << 6,
  79         SFBit = 1 << 7,
  80         DFBit = 1 << 10,
  81         OFBit = 1 << 11
  82     };
  83
  84     enum MiscRegIndex
  85     {
  86         // Control registers
  87         // Most of these are invalid.
  88         MISCREG_CR_BASE,
  89         MISCREG_CR0 = MISCREG_CR_BASE,
  90         MISCREG_CR1,
  91         MISCREG_CR2,
  92         MISCREG_CR3,
  93         MISCREG_CR4,
  94         MISCREG_CR5,
  95         MISCREG_CR6,
  96         MISCREG_CR7,
  97         MISCREG_CR8,
  98         MISCREG_CR9,
  99         MISCREG_CR10,
 100         MISCREG_CR11,
 101         MISCREG_CR12,
 102         MISCREG_CR13,
 103         MISCREG_CR14,
 104         MISCREG_CR15,
 105
 106         // Debug registers
 107         MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
 108         MISCREG_DR0 = MISCREG_DR_BASE,
 109         MISCREG_DR1,
 110         MISCREG_DR2,
 111         MISCREG_DR3,
 112         MISCREG_DR4,
 113         MISCREG_DR5,
 114         MISCREG_DR6,
 115         MISCREG_DR7,
 116
 117         // Flags register
 118         MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
 119
 120         /*
 121          * Model Specific Registers
 122          */
 123         // Time stamp counter
 124         MISCREG_TSC,
 125
 126         MISCREG_MTRRCAP,
 127
 128         MISCREG_SYSENTER_CS,
 129         MISCREG_SYSENTER_ESP,
 130         MISCREG_SYSENTER_EIP,
 131
 132         MISCREG_MCG_CAP,
 133         MISCREG_MCG_STATUS,
 134         MISCREG_MCG_CTL,
 135
 136         MISCREG_DEBUG_CTL_MSR,
 137
 138         MISCREG_LAST_BRANCH_FROM_IP,
 139         MISCREG_LAST_BRANCH_TO_IP,
 140         MISCREG_LAST_EXCEPTION_FROM_IP,
 141         MISCREG_LAST_EXCEPTION_TO_IP,
 142
 143         MISCREG_MTRR_PHYS_BASE_BASE,
 144         MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
 145         MISCREG_MTRR_PHYS_BASE_1,
 146         MISCREG_MTRR_PHYS_BASE_2,
 147         MISCREG_MTRR_PHYS_BASE_3,
 148         MISCREG_MTRR_PHYS_BASE_4,
 149         MISCREG_MTRR_PHYS_BASE_5,
 150         MISCREG_MTRR_PHYS_BASE_6,
 151         MISCREG_MTRR_PHYS_BASE_7,
 152
 153         MISCREG_MTRR_PHYS_MASK_BASE,
 154         MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
 155         MISCREG_MTRR_PHYS_MASK_1,
 156         MISCREG_MTRR_PHYS_MASK_2,
 157         MISCREG_MTRR_PHYS_MASK_3,
 158         MISCREG_MTRR_PHYS_MASK_4,
 159         MISCREG_MTRR_PHYS_MASK_5,
 160         MISCREG_MTRR_PHYS_MASK_6,
 161         MISCREG_MTRR_PHYS_MASK_7,
 162
 163         MISCREG_MTRR_FIX_64K_00000,
 164         MISCREG_MTRR_FIX_16K_80000,
 165         MISCREG_MTRR_FIX_16K_A0000,
 166         MISCREG_MTRR_FIX_4K_C0000,
 167         MISCREG_MTRR_FIX_4K_C8000,
 168         MISCREG_MTRR_FIX_4K_D0000,
 169         MISCREG_MTRR_FIX_4K_D8000,
 170         MISCREG_MTRR_FIX_4K_E0000,
 171         MISCREG_MTRR_FIX_4K_E8000,
 172         MISCREG_MTRR_FIX_4K_F0000,
 173         MISCREG_MTRR_FIX_4K_F8000,
 174
 175         MISCREG_PAT,
 176
 177         MISCREG_DEF_TYPE,
 178
 179         MISCREG_MC_CTL_BASE,
 180         MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
 181         MISCREG_MC1_CTL,
 182         MISCREG_MC2_CTL,
 183         MISCREG_MC3_CTL,
 184         MISCREG_MC4_CTL,
 185
 186         MISCREG_MC_STATUS_BASE,
 187         MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
 188         MISCREG_MC1_STATUS,
 189         MISCREG_MC2_STATUS,
 190         MISCREG_MC3_STATUS,
 191         MISCREG_MC4_STATUS,
 192
 193         MISCREG_MC_ADDR_BASE,
 194         MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
 195         MISCREG_MC1_ADDR,
 196         MISCREG_MC2_ADDR,
 197         MISCREG_MC3_ADDR,
 198         MISCREG_MC4_ADDR,
 199
 200         MISCREG_MC_MISC_BASE,
 201         MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
 202         MISCREG_MC1_MISC,
 203         MISCREG_MC2_MISC,
 204         MISCREG_MC3_MISC,
 205         MISCREG_MC4_MISC,
 206
 207         // Extended feature enable register
 208         MISCREG_EFER,
 209
 210         MISCREG_STAR,
 211         MISCREG_LSTAR,
 212         MISCREG_CSTAR,
 213
 214         MISCREG_SF_MASK,
 215
 216         MISCREG_KERNEL_GS_BASE,
 217
 218         MISCREG_TSC_AUX,
 219
 220         MISCREG_PERF_EVT_SEL_BASE,
 221         MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
 222         MISCREG_PERF_EVT_SEL1,
 223         MISCREG_PERF_EVT_SEL2,
 224         MISCREG_PERF_EVT_SEL3,
 225
 226         MISCREG_PERF_EVT_CTR_BASE,
 227         MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
 228         MISCREG_PERF_EVT_CTR1,
 229         MISCREG_PERF_EVT_CTR2,
 230         MISCREG_PERF_EVT_CTR3,
 231
 232         MISCREG_SYSCFG,
 233
 234         MISCREG_IORR_BASE_BASE,
 235         MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
 236         MISCREG_IORR_BASE1,
 237
 238         MISCREG_IORR_MASK_BASE,
 239         MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
 240         MISCREG_IORR_MASK1,
 241
 242         MISCREG_TOP_MEM,
 243         MISCREG_TOP_MEM2,
 244
 245         MISCREG_VM_CR,
 246         MISCREG_IGNNE,
 247         MISCREG_SMM_CTL,
 248         MISCREG_VM_HSAVE_PA,
 249
 250         /*
 251          * Segment registers
 252          */
 253         // Segment selectors
 254         MISCREG_SEG_SEL_BASE,
 255         MISCREG_ES = MISCREG_SEG_SEL_BASE,
 256         MISCREG_CS,
 257         MISCREG_SS,
 258         MISCREG_DS,
 259         MISCREG_FS,
 260         MISCREG_GS,
 261
 262         // Hidden segment base field
 263         MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
 264         MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
 265         MISCREG_CS_BASE,
 266         MISCREG_SS_BASE,
 267         MISCREG_DS_BASE,
 268         MISCREG_FS_BASE,
 269         MISCREG_GS_BASE,
 270
 271         // Hidden segment limit field
 272         MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
 273         MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
 274         MISCREG_CS_LIMIT,
 275         MISCREG_SS_LIMIT,
 276         MISCREG_DS_LIMIT,
 277         MISCREG_FS_LIMIT,
 278         MISCREG_GS_LIMIT,
 279
 280         // Hidden segment limit attributes
 281         MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
 282         MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
 283         MISCREG_CS_ATTR,
 284         MISCREG_SS_ATTR,
 285         MISCREG_DS_ATTR,
 286         MISCREG_FS_ATTR,
 287         MISCREG_GS_ATTR,
 288
 289         // System segment selectors
 290         MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
 291         MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
 292         MISCREG_TR,
 293
 294         // Hidden system segment base field
 295         MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
 296         MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
 297         MISCREG_TR_BASE,
 298         MISCREG_GDTR_BASE,
 299         MISCREG_IDTR_BASE,
 300
 301         // Hidden system segment limit field
 302         MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
 303         MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
 304         MISCREG_TR_LIMIT,
 305         MISCREG_GDTR_LIMIT,
 306         MISCREG_IDTR_LIMIT,
 307
 308         // Hidden system segment attribute field
 309         MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
 310         MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
 311         MISCREG_TR_ATTR,
 312
 313         // Floating point control registers
 314         MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments,
 315
 316         //XXX Add "Model-Specific Registers"
 317
 318         NUM_MISCREGS
 319     };
 320
 321     static inline MiscRegIndex
 322     MISCREG_CR(int index)
 323     {
 324         return (MiscRegIndex)(MISCREG_CR_BASE + index);
 325     }
 326
 327     static inline MiscRegIndex
 328     MISCREG_DR(int index)
 329     {
 330         return (MiscRegIndex)(MISCREG_DR_BASE + index);
 331     }
 332
 333     static inline MiscRegIndex
 334     MISCREG_MTRR_PHYS_BASE(int index)
 335     {
 336         return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
 337     }
 338
 339     static inline MiscRegIndex
 340     MISCREG_MTRR_PHYS_MASK(int index)
 341     {
 342         return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
 343     }
 344
 345     static inline MiscRegIndex
 346     MISCREG_MC_CTL(int index)
 347     {
 348         return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
 349     }
 350
 351     static inline MiscRegIndex
 352     MISCREG_MC_STATUS(int index)
 353     {
 354         return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
 355     }
 356
 357     static inline MiscRegIndex
 358     MISCREG_MC_ADDR(int index)
 359     {
 360         return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
 361     }
 362
 363     static inline MiscRegIndex
 364     MISCREG_MC_MISC(int index)
 365     {
 366         return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
 367     }
 368
 369     static inline MiscRegIndex
 370     MISCREG_PERF_EVT_SEL(int index)
 371     {
 372         return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
 373     }
 374
 375     static inline MiscRegIndex
 376     MISCREG_PERF_EVT_CTR(int index)
 377     {
 378         return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
 379     }
 380
 381     static inline MiscRegIndex
 382     MISCREG_IORR_BASE(int index)
 383     {
 384         return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
 385     }
 386
 387     static inline MiscRegIndex
 388     MISCREG_IORR_MASK(int index)
 389     {
 390         return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
 391     }
 392
 393     static inline MiscRegIndex
 394     MISCREG_SEG_SEL(int index)
 395     {
 396         return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
 397     }
 398
 399     static inline MiscRegIndex
 400     MISCREG_SEG_BASE(int index)
 401     {
 402         return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
 403     }
 404
 405     static inline MiscRegIndex
 406     MISCREG_SEG_LIMIT(int index)
 407     {
 408         return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
 409     }
 410
 411     static inline MiscRegIndex
 412     MISCREG_SEG_ATTR(int index)
 413     {
 414         return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
 415     }
 416
 417     static inline MiscRegIndex
 418     MISCREG_SYSSEG_SEL(int index)
 419     {
 420         return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
 421     }
 422
 423     static inline MiscRegIndex
 424     MISCREG_SYSSEG_BASE(int index)
 425     {
 426         return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
 427     }
 428
 429     static inline MiscRegIndex
 430     MISCREG_SYSSEG_LIMIT(int index)
 431     {
 432         return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
 433     }
 434
 435     static inline MiscRegIndex
 436     MISCREG_SYSSEG_ATTR(int index)
 437     {
 438         return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
 439     }
 440
 441     /**
 442      * A type to describe the condition code bits of the RFLAGS register,
 443      * plus two flags, EZF and ECF, which are only visible to microcode.
 444      */
 445     BitUnion64(CCFlagBits)
 446         Bitfield<11> of;
 447         Bitfield<7> sf;
 448         Bitfield<6> zf;
 449         Bitfield<5> ezf;
 450         Bitfield<4> af;
 451         Bitfield<3> ecf;
 452         Bitfield<2> pf;
 453         Bitfield<0> cf;
 454     EndBitUnion(CCFlagBits)
 455
 456     /**
 457      * RFLAGS
 458      */
 459     BitUnion64(RFLAGS)
 460         Bitfield<21> id; // ID Flag
 461         Bitfield<20> vip; // Virtual Interrupt Pending
 462         Bitfield<19> vif; // Virtual Interrupt Flag
 463         Bitfield<18> ac; // Alignment Check
 464         Bitfield<17> vm; // Virtual-8086 Mode
 465         Bitfield<16> rf; // Resume Flag
 466         Bitfield<14> nt; // Nested Task
 467         Bitfield<13, 12> iopl; // I/O Privilege Level
 468         Bitfield<11> of; // Overflow Flag
 469         Bitfield<10> df; // Direction Flag
 470         Bitfield<9> intf; // Interrupt Flag
 471         Bitfield<8> tf; // Trap Flag
 472         Bitfield<7> sf; // Sign Flag
 473         Bitfield<6> zf; // Zero Flag
 474         Bitfield<4> af; // Auxiliary Flag
 475         Bitfield<2> pf; // Parity Flag
 476         Bitfield<0> cf; // Carry Flag
 477     EndBitUnion(RFLAGS)
 478
 479     /**
 480      * Control registers
 481      */
 482     BitUnion64(CR0)
 483         Bitfield<31> pg; // Paging
 484         Bitfield<30> cd; // Cache Disable
 485         Bitfield<29> nw; // Not Writethrough
 486         Bitfield<18> am; // Alignment Mask
 487         Bitfield<16> wp; // Write Protect
 488         Bitfield<5> ne; // Numeric Error
 489         Bitfield<4> et; // Extension Type
 490         Bitfield<3> ts; // Task Switched
 491         Bitfield<2> em; // Emulation
 492         Bitfield<1> mp; // Monitor Coprocessor
 493         Bitfield<0> pe; // Protection Enabled
 494     EndBitUnion(CR0)
 495
 496     // Page Fault Virtual Address
 497     BitUnion64(CR2)
 498         Bitfield<31, 0> legacy;
 499     EndBitUnion(CR2)
 500
 501     BitUnion64(CR3)
 502         Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
 503                                    // Base Address
 504         Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
 505                                // Base Address
 506         Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
 507                                  // Base Address
 508         Bitfield<4> pcd; // Page-Level Cache Disable
 509         Bitfield<3> pwt; // Page-Level Writethrough
 510     EndBitUnion(CR3)
 511
 512     BitUnion64(CR4)
 513         Bitfield<10> osxmmexcpt; // Operating System Unmasked
 514                                  // Exception Support
 515         Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
 516         Bitfield<8> pce; // Performance-Monitoring Counter Enable
 517         Bitfield<7> pge; // Page-Global Enable
 518         Bitfield<6> mce; // Machine Check Enable
 519         Bitfield<5> pae; // Physical-Address Extension
 520         Bitfield<4> pse; // Page Size Extensions
 521         Bitfield<3> de; // Debugging Extensions
 522         Bitfield<2> tsd; // Time Stamp Disable
 523         Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
 524         Bitfield<0> vme; // Virtual-8086 Mode Extensions
 525     EndBitUnion(CR4)
 526
 527     BitUnion64(CR8)
 528         Bitfield<3, 0> tpr; // Task Priority Register
 529     EndBitUnion(CR8)
 530
 531     // MTRR capabilities
 532     BitUnion64(MTRRcap)
 533         Bitfield<7, 0> vcnt; // Variable-Range Register Count
 534         Bitfield<8> fix; // Fixed-Range Registers
 535         Bitfield<10> wc; // Write-Combining
 536     EndBitUnion(MTRRcap)
 537
 538     /**
 539      * SYSENTER configuration registers
 540      */
 541     BitUnion64(SysenterCS)
 542         Bitfield<15, 0> targetCS;
 543     EndBitUnion(SysenterCS)
 544
 545     BitUnion64(SysenterESP)
 546         Bitfield<31, 0> targetESP;
 547     EndBitUnion(SysenterESP)
 548
 549     BitUnion64(SysenterEIP)
 550         Bitfield<31, 0> targetEIP;
 551     EndBitUnion(SysenterEIP)
 552
 553     /**
 554      * Global machine check registers
 555      */
 556     BitUnion64(McgCap)
 557         Bitfield<7, 0> count; // Number of error reporting register banks
 558         Bitfield<8> MCGCP; // MCG_CTL register present.
 559     EndBitUnion(McgCap)
 560
 561     BitUnion64(McgStatus)
 562         Bitfield<0> ripv; // Restart-IP valid
 563         Bitfield<1> eipv; // Error-IP valid
 564         Bitfield<2> mcip; // Machine check in-progress
 565     EndBitUnion(McgStatus)
 566
 567     BitUnion64(DebugCtlMsr)
 568         Bitfield<0> lbr; // Last-branch record
 569         Bitfield<1> btf; // Branch single step
 570         Bitfield<2> pb0; // Performance monitoring pin control 0
 571         Bitfield<3> pb1; // Performance monitoring pin control 1
 572         Bitfield<4> pb2; // Performance monitoring pin control 2
 573         Bitfield<5> pb3; // Performance monitoring pin control 3
 574         /*uint64_t pb(int index)
 575         {
 576             return bits(__data, index + 2);
 577         }*/
 578     EndBitUnion(DebugCtlMsr)
 579
 580     BitUnion64(MtrrPhysBase)
 581         Bitfield<7, 0> type; // Default memory type
 582         Bitfield<51, 12> physbase; // Range physical base address
 583     EndBitUnion(MtrrPhysBase)
 584
 585     BitUnion64(MtrrPhysMask)
 586         Bitfield<11> valid; // MTRR pair enable
 587         Bitfield<51, 12> physmask; // Range physical mask
 588     EndBitUnion(MtrrPhysMask)
 589
 590     BitUnion64(MtrrFixed)
 591         /*uint64_t type(int index)
 592         {
 593             return bits(__data, index * 8 + 7, index * 8);
 594         }*/
 595     EndBitUnion(MtrrFixed)
 596
 597     BitUnion64(Pat)
 598         /*uint64_t pa(int index)
 599         {
 600             return bits(__data, index * 8 + 2, index * 8);
 601         }*/
 602     EndBitUnion(Pat)
 603
 604     BitUnion64(MtrrDefType)
 605         Bitfield<7, 0> type; // Default type
 606         Bitfield<10> fe; // Fixed range enable
 607         Bitfield<11> e; // MTRR enable
 608     EndBitUnion(MtrrDefType)
 609
 610     /**
 611      * Machine check
 612      */
 613     BitUnion64(McStatus)
 614         Bitfield<15,0> mcaErrorCode;
 615         Bitfield<31,16> modelSpecificCode;
 616         Bitfield<56,32> otherInfo;
 617         Bitfield<57> pcc; // Processor-context corrupt
 618         Bitfield<58> addrv; // Error-address register valid
 619         Bitfield<59> miscv; // Miscellaneous-error register valid
 620         Bitfield<60> en; // Error condition enabled
 621         Bitfield<61> uc; // Uncorrected error
 622         Bitfield<62> over; // Status register overflow
 623         Bitfield<63> val; // Valid
 624     EndBitUnion(McStatus)
 625
 626     BitUnion64(McCtl)
 627         /*uint64_t en(int index)
 628         {
 629             return bits(__data, index);
 630         }*/
 631     EndBitUnion(McCtl)
 632
 633     // Extended feature enable register
 634     BitUnion64(Efer)
 635         Bitfield<0> sce; // System call extensions
 636         Bitfield<8> lme; // Long mode enable
 637         Bitfield<10> lma; // Long mode active
 638         Bitfield<11> nxe; // No-execute enable
 639         Bitfield<12> svme; // Secure virtual machine enable
 640         Bitfield<14> ffxsr; // Fast fxsave/fxrstor
 641     EndBitUnion(Efer)
 642
 643     BitUnion64(Star)
 644         Bitfield<31,0> targetEip;
 645         Bitfield<47,32> syscallCsAndSs;
 646         Bitfield<63,48> sysretCsAndSs;
 647     EndBitUnion(Star)
 648
 649     BitUnion64(SfMask)
 650         Bitfield<31,0> mask;
 651     EndBitUnion(SfMask)
 652
 653     BitUnion64(PerfEvtSel)
 654         Bitfield<7,0> eventMask;
 655         Bitfield<15,8> unitMask;
 656         Bitfield<16> usr; // User mode
 657         Bitfield<17> os; // Operating-system mode
 658         Bitfield<18> e; // Edge detect
 659         Bitfield<19> pc; // Pin control
 660         Bitfield<20> intEn; // Interrupt enable
 661         Bitfield<22> en; // Counter enable
 662         Bitfield<23> inv; // Invert mask
 663         Bitfield<31,24> counterMask;
 664     EndBitUnion(PerfEvtSel)
 665
 666     BitUnion32(Syscfg)
 667         Bitfield<18> mfde; // MtrrFixDramEn
 668         Bitfield<19> mfdm; // MtrrFixDramModEn
 669         Bitfield<20> mvdm; // MtrrVarDramEn
 670         Bitfield<21> tom2; // MtrrTom2En
 671     EndBitUnion(Syscfg)
 672
 673     BitUnion64(IorrBase)
 674         Bitfield<3> wr; // WrMem Enable
 675         Bitfield<4> rd; // RdMem Enable
 676         Bitfield<51,12> physbase; // Range physical base address
 677     EndBitUnion(IorrBase)
 678
 679     BitUnion64(IorrMask)
 680         Bitfield<11> v; // I/O register pair enable (valid)
 681         Bitfield<51,12> physmask; // Range physical mask
 682     EndBitUnion(IorrMask)
 683
 684     BitUnion64(Tom)
 685         Bitfield<51,23> physAddr; // Top of memory physical address
 686     EndBitUnion(Tom)
 687
 688     BitUnion64(VmCrMsr)
 689         Bitfield<0> dpd;
 690         Bitfield<1> rInit;
 691         Bitfield<2> disA20M;
 692     EndBitUnion(VmCrMsr)
 693
 694     BitUnion64(IgnneMsr)
 695         Bitfield<0> ignne;
 696     EndBitUnion(IgnneMsr)
 697
 698     BitUnion64(SmmCtlMsr)
 699         Bitfield<0> dismiss;
 700         Bitfield<1> enter;
 701         Bitfield<2> smiCycle;
 702         Bitfield<3> exit;
 703         Bitfield<4> rsmCycle;
 704     EndBitUnion(SmmCtlMsr)
 705
 706     /**
 707      * Segment Selector
 708      */
 709     BitUnion64(SegSelector)
 710         Bitfield<15, 3> si; // Selector Index
 711         Bitfield<2> ti; // Table Indicator
 712         Bitfield<1, 0> rpl; // Requestor Privilege Level
 713     EndBitUnion(SegSelector)
 714
 715     /**
 716      * Segment Descriptors
 717      */
 718
 719     BitUnion64(SegDescriptor)
 720         Bitfield<63, 56> baseHigh;
 721         Bitfield<39, 16> baseLow;
 722         Bitfield<55> g; // Granularity
 723         Bitfield<54> d; // Default Operand Size
 724         Bitfield<54> b; // Default Operand Size
 725         Bitfield<53> l; // Long Attribute Bit
 726         Bitfield<52> avl; // Available To Software
 727         Bitfield<51, 48> limitHigh;
 728         Bitfield<15, 0> limitLow;
 729         Bitfield<47> p; // Present
 730         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 731         Bitfield<44> s; // System
 732         SubBitUnion(type, 43, 40)
 733             // Specifies whether this descriptor is for code or data.
 734             Bitfield<43> codeOrData;
 735
 736             // These bit fields are for code segments
 737             Bitfield<42> c; // Conforming
 738             Bitfield<41> r; // Readable
 739
 740             // These bit fields are for data segments
 741             Bitfield<42> e; // Expand-Down
 742             Bitfield<41> w; // Writable
 743
 744             // This is used for both code and data segments.
 745             Bitfield<40> a; // Accessed
 746         EndSubBitUnion(type)
 747     EndBitUnion(SegDescriptor)
 748
 749     BitUnion64(SegAttr)
 750         Bitfield<0> writable;
 751         Bitfield<1> readable;
 752         Bitfield<2> expandDown;
 753         Bitfield<4, 3> dpl;
 754         Bitfield<5> defaultSize;
 755         Bitfield<6> longMode;
 756     EndBitUnion(SegAttr)
 757
 758     BitUnion64(GateDescriptor)
 759         Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
 760         Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
 761         Bitfield<31, 16> selector; // Target Code-Segment Selector
 762         Bitfield<47> p; // Present
 763         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 764         Bitfield<43, 40> type;
 765         Bitfield<36, 32> count; // Parameter Count
 766     EndBitUnion(GateDescriptor)
 767
 768     /**
 769      * Descriptor-Table Registers
 770      */
 771     BitUnion64(GDTR)
 772     EndBitUnion(GDTR)
 773
 774     BitUnion64(IDTR)
 775     EndBitUnion(IDTR)
 776
 777     BitUnion64(LDTR)
 778     EndBitUnion(LDTR)
 779
 780     /**
 781      * Task Register
 782      */
 783     BitUnion64(TR)
 784     EndBitUnion(TR)
 785 };
 786
 787 #endif // __ARCH_X86_INTREGS_HH__