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58 #ifndef __ARCH_X86_MISCREGS_HH__
59 #define __ARCH_X86_MISCREGS_HH__
61 #include "arch/x86/x86_traits.hh"
62 #include "base/bitunion.hh"
64 //These get defined in some system headers (at least termbits.h). That confuses
65 //things here significantly.
87 // Most of these are invalid.
89 MISCREG_CR0 = MISCREG_CR_BASE,
107 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
108 MISCREG_DR0 = MISCREG_DR_BASE,
118 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
121 * Model Specific Registers
123 // Time stamp counter
129 MISCREG_SYSENTER_ESP,
130 MISCREG_SYSENTER_EIP,
136 MISCREG_DEBUG_CTL_MSR,
138 MISCREG_LAST_BRANCH_FROM_IP,
139 MISCREG_LAST_BRANCH_TO_IP,
140 MISCREG_LAST_EXCEPTION_FROM_IP,
141 MISCREG_LAST_EXCEPTION_TO_IP,
143 MISCREG_MTRR_PHYS_BASE_BASE,
144 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
145 MISCREG_MTRR_PHYS_BASE_1,
146 MISCREG_MTRR_PHYS_BASE_2,
147 MISCREG_MTRR_PHYS_BASE_3,
148 MISCREG_MTRR_PHYS_BASE_4,
149 MISCREG_MTRR_PHYS_BASE_5,
150 MISCREG_MTRR_PHYS_BASE_6,
151 MISCREG_MTRR_PHYS_BASE_7,
153 MISCREG_MTRR_PHYS_MASK_BASE,
154 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
155 MISCREG_MTRR_PHYS_MASK_1,
156 MISCREG_MTRR_PHYS_MASK_2,
157 MISCREG_MTRR_PHYS_MASK_3,
158 MISCREG_MTRR_PHYS_MASK_4,
159 MISCREG_MTRR_PHYS_MASK_5,
160 MISCREG_MTRR_PHYS_MASK_6,
161 MISCREG_MTRR_PHYS_MASK_7,
163 MISCREG_MTRR_FIX_64K_00000,
164 MISCREG_MTRR_FIX_16K_80000,
165 MISCREG_MTRR_FIX_16K_A0000,
166 MISCREG_MTRR_FIX_4K_C0000,
167 MISCREG_MTRR_FIX_4K_C8000,
168 MISCREG_MTRR_FIX_4K_D0000,
169 MISCREG_MTRR_FIX_4K_D8000,
170 MISCREG_MTRR_FIX_4K_E0000,
171 MISCREG_MTRR_FIX_4K_E8000,
172 MISCREG_MTRR_FIX_4K_F0000,
173 MISCREG_MTRR_FIX_4K_F8000,
180 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
186 MISCREG_MC_STATUS_BASE,
187 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
193 MISCREG_MC_ADDR_BASE,
194 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
200 MISCREG_MC_MISC_BASE,
201 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
207 // Extended feature enable register
216 MISCREG_KERNEL_GS_BASE,
220 MISCREG_PERF_EVT_SEL_BASE,
221 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
222 MISCREG_PERF_EVT_SEL1,
223 MISCREG_PERF_EVT_SEL2,
224 MISCREG_PERF_EVT_SEL3,
226 MISCREG_PERF_EVT_CTR_BASE,
227 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
228 MISCREG_PERF_EVT_CTR1,
229 MISCREG_PERF_EVT_CTR2,
230 MISCREG_PERF_EVT_CTR3,
234 MISCREG_IORR_BASE_BASE,
235 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
238 MISCREG_IORR_MASK_BASE,
239 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
254 MISCREG_SEG_SEL_BASE,
255 MISCREG_ES = MISCREG_SEG_SEL_BASE,
261 MISCREG_INT, // This isn't actually used.
263 // Hidden segment base field
264 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
265 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
273 // Hidden segment limit field
274 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
275 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
281 MISCREG_INT_LIMIT, // This isn't actually used.
283 // Hidden segment limit attributes
284 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
285 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
291 MISCREG_INT_ATTR, // This isn't actually used.
293 // System segment selectors
294 MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
295 MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
298 // Hidden system segment base field
299 MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
300 MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
305 // Hidden system segment limit field
306 MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
307 MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
312 // Hidden system segment attribute field
313 MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
314 MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
317 // Floating point control registers
318 MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments,
320 //XXX Add "Model-Specific Registers"
325 static inline MiscRegIndex
326 MISCREG_CR(int index)
328 return (MiscRegIndex)(MISCREG_CR_BASE + index);
331 static inline MiscRegIndex
332 MISCREG_DR(int index)
334 return (MiscRegIndex)(MISCREG_DR_BASE + index);
337 static inline MiscRegIndex
338 MISCREG_MTRR_PHYS_BASE(int index)
340 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
343 static inline MiscRegIndex
344 MISCREG_MTRR_PHYS_MASK(int index)
346 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
349 static inline MiscRegIndex
350 MISCREG_MC_CTL(int index)
352 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
355 static inline MiscRegIndex
356 MISCREG_MC_STATUS(int index)
358 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
361 static inline MiscRegIndex
362 MISCREG_MC_ADDR(int index)
364 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
367 static inline MiscRegIndex
368 MISCREG_MC_MISC(int index)
370 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
373 static inline MiscRegIndex
374 MISCREG_PERF_EVT_SEL(int index)
376 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
379 static inline MiscRegIndex
380 MISCREG_PERF_EVT_CTR(int index)
382 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
385 static inline MiscRegIndex
386 MISCREG_IORR_BASE(int index)
388 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
391 static inline MiscRegIndex
392 MISCREG_IORR_MASK(int index)
394 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
397 static inline MiscRegIndex
398 MISCREG_SEG_SEL(int index)
400 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
403 static inline MiscRegIndex
404 MISCREG_SEG_BASE(int index)
406 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
409 static inline MiscRegIndex
410 MISCREG_SEG_LIMIT(int index)
412 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
415 static inline MiscRegIndex
416 MISCREG_SEG_ATTR(int index)
418 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
421 static inline MiscRegIndex
422 MISCREG_SYSSEG_SEL(int index)
424 return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
427 static inline MiscRegIndex
428 MISCREG_SYSSEG_BASE(int index)
430 return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
433 static inline MiscRegIndex
434 MISCREG_SYSSEG_LIMIT(int index)
436 return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
439 static inline MiscRegIndex
440 MISCREG_SYSSEG_ATTR(int index)
442 return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
446 * A type to describe the condition code bits of the RFLAGS register,
447 * plus two flags, EZF and ECF, which are only visible to microcode.
449 BitUnion64(CCFlagBits)
458 EndBitUnion(CCFlagBits)
464 Bitfield<21> id; // ID Flag
465 Bitfield<20> vip; // Virtual Interrupt Pending
466 Bitfield<19> vif; // Virtual Interrupt Flag
467 Bitfield<18> ac; // Alignment Check
468 Bitfield<17> vm; // Virtual-8086 Mode
469 Bitfield<16> rf; // Resume Flag
470 Bitfield<14> nt; // Nested Task
471 Bitfield<13, 12> iopl; // I/O Privilege Level
472 Bitfield<11> of; // Overflow Flag
473 Bitfield<10> df; // Direction Flag
474 Bitfield<9> intf; // Interrupt Flag
475 Bitfield<8> tf; // Trap Flag
476 Bitfield<7> sf; // Sign Flag
477 Bitfield<6> zf; // Zero Flag
478 Bitfield<4> af; // Auxiliary Flag
479 Bitfield<2> pf; // Parity Flag
480 Bitfield<0> cf; // Carry Flag
487 Bitfield<31> pg; // Paging
488 Bitfield<30> cd; // Cache Disable
489 Bitfield<29> nw; // Not Writethrough
490 Bitfield<18> am; // Alignment Mask
491 Bitfield<16> wp; // Write Protect
492 Bitfield<5> ne; // Numeric Error
493 Bitfield<4> et; // Extension Type
494 Bitfield<3> ts; // Task Switched
495 Bitfield<2> em; // Emulation
496 Bitfield<1> mp; // Monitor Coprocessor
497 Bitfield<0> pe; // Protection Enabled
500 // Page Fault Virtual Address
502 Bitfield<31, 0> legacy;
506 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
508 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
510 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
512 Bitfield<4> pcd; // Page-Level Cache Disable
513 Bitfield<3> pwt; // Page-Level Writethrough
517 Bitfield<10> osxmmexcpt; // Operating System Unmasked
519 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
520 Bitfield<8> pce; // Performance-Monitoring Counter Enable
521 Bitfield<7> pge; // Page-Global Enable
522 Bitfield<6> mce; // Machine Check Enable
523 Bitfield<5> pae; // Physical-Address Extension
524 Bitfield<4> pse; // Page Size Extensions
525 Bitfield<3> de; // Debugging Extensions
526 Bitfield<2> tsd; // Time Stamp Disable
527 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
528 Bitfield<0> vme; // Virtual-8086 Mode Extensions
532 Bitfield<3, 0> tpr; // Task Priority Register
537 Bitfield<7, 0> vcnt; // Variable-Range Register Count
538 Bitfield<8> fix; // Fixed-Range Registers
539 Bitfield<10> wc; // Write-Combining
543 * SYSENTER configuration registers
545 BitUnion64(SysenterCS)
546 Bitfield<15, 0> targetCS;
547 EndBitUnion(SysenterCS)
549 BitUnion64(SysenterESP)
550 Bitfield<31, 0> targetESP;
551 EndBitUnion(SysenterESP)
553 BitUnion64(SysenterEIP)
554 Bitfield<31, 0> targetEIP;
555 EndBitUnion(SysenterEIP)
558 * Global machine check registers
561 Bitfield<7, 0> count; // Number of error reporting register banks
562 Bitfield<8> MCGCP; // MCG_CTL register present.
565 BitUnion64(McgStatus)
566 Bitfield<0> ripv; // Restart-IP valid
567 Bitfield<1> eipv; // Error-IP valid
568 Bitfield<2> mcip; // Machine check in-progress
569 EndBitUnion(McgStatus)
571 BitUnion64(DebugCtlMsr)
572 Bitfield<0> lbr; // Last-branch record
573 Bitfield<1> btf; // Branch single step
574 Bitfield<2> pb0; // Performance monitoring pin control 0
575 Bitfield<3> pb1; // Performance monitoring pin control 1
576 Bitfield<4> pb2; // Performance monitoring pin control 2
577 Bitfield<5> pb3; // Performance monitoring pin control 3
578 /*uint64_t pb(int index)
580 return bits(__data, index + 2);
582 EndBitUnion(DebugCtlMsr)
584 BitUnion64(MtrrPhysBase)
585 Bitfield<7, 0> type; // Default memory type
586 Bitfield<51, 12> physbase; // Range physical base address
587 EndBitUnion(MtrrPhysBase)
589 BitUnion64(MtrrPhysMask)
590 Bitfield<11> valid; // MTRR pair enable
591 Bitfield<51, 12> physmask; // Range physical mask
592 EndBitUnion(MtrrPhysMask)
594 BitUnion64(MtrrFixed)
595 /*uint64_t type(int index)
597 return bits(__data, index * 8 + 7, index * 8);
599 EndBitUnion(MtrrFixed)
602 /*uint64_t pa(int index)
604 return bits(__data, index * 8 + 2, index * 8);
608 BitUnion64(MtrrDefType)
609 Bitfield<7, 0> type; // Default type
610 Bitfield<10> fe; // Fixed range enable
611 Bitfield<11> e; // MTRR enable
612 EndBitUnion(MtrrDefType)
618 Bitfield<15,0> mcaErrorCode;
619 Bitfield<31,16> modelSpecificCode;
620 Bitfield<56,32> otherInfo;
621 Bitfield<57> pcc; // Processor-context corrupt
622 Bitfield<58> addrv; // Error-address register valid
623 Bitfield<59> miscv; // Miscellaneous-error register valid
624 Bitfield<60> en; // Error condition enabled
625 Bitfield<61> uc; // Uncorrected error
626 Bitfield<62> over; // Status register overflow
627 Bitfield<63> val; // Valid
628 EndBitUnion(McStatus)
631 /*uint64_t en(int index)
633 return bits(__data, index);
637 // Extended feature enable register
639 Bitfield<0> sce; // System call extensions
640 Bitfield<8> lme; // Long mode enable
641 Bitfield<10> lma; // Long mode active
642 Bitfield<11> nxe; // No-execute enable
643 Bitfield<12> svme; // Secure virtual machine enable
644 Bitfield<14> ffxsr; // Fast fxsave/fxrstor
648 Bitfield<31,0> targetEip;
649 Bitfield<47,32> syscallCsAndSs;
650 Bitfield<63,48> sysretCsAndSs;
657 BitUnion64(PerfEvtSel)
658 Bitfield<7,0> eventMask;
659 Bitfield<15,8> unitMask;
660 Bitfield<16> usr; // User mode
661 Bitfield<17> os; // Operating-system mode
662 Bitfield<18> e; // Edge detect
663 Bitfield<19> pc; // Pin control
664 Bitfield<20> intEn; // Interrupt enable
665 Bitfield<22> en; // Counter enable
666 Bitfield<23> inv; // Invert mask
667 Bitfield<31,24> counterMask;
668 EndBitUnion(PerfEvtSel)
671 Bitfield<18> mfde; // MtrrFixDramEn
672 Bitfield<19> mfdm; // MtrrFixDramModEn
673 Bitfield<20> mvdm; // MtrrVarDramEn
674 Bitfield<21> tom2; // MtrrTom2En
678 Bitfield<3> wr; // WrMem Enable
679 Bitfield<4> rd; // RdMem Enable
680 Bitfield<51,12> physbase; // Range physical base address
681 EndBitUnion(IorrBase)
684 Bitfield<11> v; // I/O register pair enable (valid)
685 Bitfield<51,12> physmask; // Range physical mask
686 EndBitUnion(IorrMask)
689 Bitfield<51,23> physAddr; // Top of memory physical address
700 EndBitUnion(IgnneMsr)
702 BitUnion64(SmmCtlMsr)
705 Bitfield<2> smiCycle;
707 Bitfield<4> rsmCycle;
708 EndBitUnion(SmmCtlMsr)
713 BitUnion64(SegSelector)
714 Bitfield<15, 3> si; // Selector Index
715 Bitfield<2> ti; // Table Indicator
716 Bitfield<1, 0> rpl; // Requestor Privilege Level
717 EndBitUnion(SegSelector)
720 * Segment Descriptors
723 BitUnion64(SegDescriptor)
724 Bitfield<63, 56> baseHigh;
725 Bitfield<39, 16> baseLow;
726 Bitfield<55> g; // Granularity
727 Bitfield<54> d; // Default Operand Size
728 Bitfield<54> b; // Default Operand Size
729 Bitfield<53> l; // Long Attribute Bit
730 Bitfield<52> avl; // Available To Software
731 Bitfield<51, 48> limitHigh;
732 Bitfield<15, 0> limitLow;
733 Bitfield<47> p; // Present
734 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
735 Bitfield<44> s; // System
736 SubBitUnion(type, 43, 40)
737 // Specifies whether this descriptor is for code or data.
738 Bitfield<43> codeOrData;
740 // These bit fields are for code segments
741 Bitfield<42> c; // Conforming
742 Bitfield<41> r; // Readable
744 // These bit fields are for data segments
745 Bitfield<42> e; // Expand-Down
746 Bitfield<41> w; // Writable
748 // This is used for both code and data segments.
749 Bitfield<40> a; // Accessed
751 EndBitUnion(SegDescriptor)
754 Bitfield<0> writable;
755 Bitfield<1> readable;
756 Bitfield<2> expandDown;
758 Bitfield<5> defaultSize;
759 Bitfield<6> longMode;
762 BitUnion64(GateDescriptor)
763 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
764 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
765 Bitfield<31, 16> selector; // Target Code-Segment Selector
766 Bitfield<47> p; // Present
767 Bitfield<46, 45> dpl; // Descriptor Privilege-Level
768 Bitfield<43, 40> type;
769 Bitfield<36, 32> count; // Parameter Count
770 EndBitUnion(GateDescriptor)
773 * Descriptor-Table Registers
791 #endif // __ARCH_X86_INTREGS_HH__