src/arch/x86/miscregs.hh

   1 /*
   2  * Copyright (c) 2007 The Hewlett-Packard Development Company
   3  * All rights reserved.
   4  *
   5  * Redistribution and use of this software in source and binary forms,
   6  * with or without modification, are permitted provided that the
   7  * following conditions are met:
   8  *
   9  * The software must be used only for Non-Commercial Use which means any
  10  * use which is NOT directed to receiving any direct monetary
  11  * compensation for, or commercial advantage from such use.  Illustrative
  12  * examples of non-commercial use are academic research, personal study,
  13  * teaching, education and corporate research & development.
  14  * Illustrative examples of commercial use are distributing products for
  15  * commercial advantage and providing services using the software for
  16  * commercial advantage.
  17  *
  18  * If you wish to use this software or functionality therein that may be
  19  * covered by patents for commercial use, please contact:
  20  *     Director of Intellectual Property Licensing
  21  *     Office of Strategy and Technology
  22  *     Hewlett-Packard Company
  23  *     1501 Page Mill Road
  24  *     Palo Alto, California  94304
  25  *
  26  * Redistributions of source code must retain the above copyright notice,
  27  * this list of conditions and the following disclaimer.  Redistributions
  28  * in binary form must reproduce the above copyright notice, this list of
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  31  * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
  32  * contributors may be used to endorse or promote products derived from
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  35  * output created using the software may be prepared, but only for
  36  * Non-Commercial Uses.  Derivatives of the software may be shared with
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  38  * conditions herein which includes the Non-Commercial Use restrictions;
  39  * and (ii) such Derivatives of the software include the above copyright
  40  * notice to acknowledge the contribution from this software where
  41  * applicable, this list of conditions and the disclaimer below.
  42  *
  43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  54  *
  55  * Authors: Gabe Black
  56  */
  57
  58 #ifndef __ARCH_X86_MISCREGS_HH__
  59 #define __ARCH_X86_MISCREGS_HH__
  60
  61 #include "arch/x86/x86_traits.hh"
  62 #include "base/bitunion.hh"
  63
  64 //These get defined in some system headers (at least termbits.h). That confuses
  65 //things here significantly.
  66 #undef CR0
  67 #undef CR2
  68 #undef CR3
  69
  70 namespace X86ISA
  71 {
  72     enum CondFlagBit {
  73         CFBit = 1 << 0,
  74         PFBit = 1 << 2,
  75         ECFBit = 1 << 3,
  76         AFBit = 1 << 4,
  77         EZFBit = 1 << 5,
  78         ZFBit = 1 << 6,
  79         SFBit = 1 << 7,
  80         DFBit = 1 << 10,
  81         OFBit = 1 << 11
  82     };
  83
  84     enum MiscRegIndex
  85     {
  86         // Control registers
  87         // Most of these are invalid.
  88         MISCREG_CR_BASE,
  89         MISCREG_CR0 = MISCREG_CR_BASE,
  90         MISCREG_CR1,
  91         MISCREG_CR2,
  92         MISCREG_CR3,
  93         MISCREG_CR4,
  94         MISCREG_CR5,
  95         MISCREG_CR6,
  96         MISCREG_CR7,
  97         MISCREG_CR8,
  98         MISCREG_CR9,
  99         MISCREG_CR10,
 100         MISCREG_CR11,
 101         MISCREG_CR12,
 102         MISCREG_CR13,
 103         MISCREG_CR14,
 104         MISCREG_CR15,
 105
 106         // Debug registers
 107         MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
 108         MISCREG_DR0 = MISCREG_DR_BASE,
 109         MISCREG_DR1,
 110         MISCREG_DR2,
 111         MISCREG_DR3,
 112         MISCREG_DR4,
 113         MISCREG_DR5,
 114         MISCREG_DR6,
 115         MISCREG_DR7,
 116
 117         // Flags register
 118         MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
 119
 120         /*
 121          * Model Specific Registers
 122          */
 123         // Time stamp counter
 124         MISCREG_TSC,
 125
 126         MISCREG_MTRRCAP,
 127
 128         MISCREG_SYSENTER_CS,
 129         MISCREG_SYSENTER_ESP,
 130         MISCREG_SYSENTER_EIP,
 131
 132         MISCREG_MCG_CAP,
 133         MISCREG_MCG_STATUS,
 134         MISCREG_MCG_CTL,
 135
 136         MISCREG_DEBUG_CTL_MSR,
 137
 138         MISCREG_LAST_BRANCH_FROM_IP,
 139         MISCREG_LAST_BRANCH_TO_IP,
 140         MISCREG_LAST_EXCEPTION_FROM_IP,
 141         MISCREG_LAST_EXCEPTION_TO_IP,
 142
 143         MISCREG_MTRR_PHYS_BASE_BASE,
 144         MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
 145         MISCREG_MTRR_PHYS_BASE_1,
 146         MISCREG_MTRR_PHYS_BASE_2,
 147         MISCREG_MTRR_PHYS_BASE_3,
 148         MISCREG_MTRR_PHYS_BASE_4,
 149         MISCREG_MTRR_PHYS_BASE_5,
 150         MISCREG_MTRR_PHYS_BASE_6,
 151         MISCREG_MTRR_PHYS_BASE_7,
 152
 153         MISCREG_MTRR_PHYS_MASK_BASE,
 154         MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
 155         MISCREG_MTRR_PHYS_MASK_1,
 156         MISCREG_MTRR_PHYS_MASK_2,
 157         MISCREG_MTRR_PHYS_MASK_3,
 158         MISCREG_MTRR_PHYS_MASK_4,
 159         MISCREG_MTRR_PHYS_MASK_5,
 160         MISCREG_MTRR_PHYS_MASK_6,
 161         MISCREG_MTRR_PHYS_MASK_7,
 162
 163         MISCREG_MTRR_FIX_64K_00000,
 164         MISCREG_MTRR_FIX_16K_80000,
 165         MISCREG_MTRR_FIX_16K_A0000,
 166         MISCREG_MTRR_FIX_4K_C0000,
 167         MISCREG_MTRR_FIX_4K_C8000,
 168         MISCREG_MTRR_FIX_4K_D0000,
 169         MISCREG_MTRR_FIX_4K_D8000,
 170         MISCREG_MTRR_FIX_4K_E0000,
 171         MISCREG_MTRR_FIX_4K_E8000,
 172         MISCREG_MTRR_FIX_4K_F0000,
 173         MISCREG_MTRR_FIX_4K_F8000,
 174
 175         MISCREG_PAT,
 176
 177         MISCREG_DEF_TYPE,
 178
 179         MISCREG_MC_CTL_BASE,
 180         MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
 181         MISCREG_MC1_CTL,
 182         MISCREG_MC2_CTL,
 183         MISCREG_MC3_CTL,
 184         MISCREG_MC4_CTL,
 185
 186         MISCREG_MC_STATUS_BASE,
 187         MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
 188         MISCREG_MC1_STATUS,
 189         MISCREG_MC2_STATUS,
 190         MISCREG_MC3_STATUS,
 191         MISCREG_MC4_STATUS,
 192
 193         MISCREG_MC_ADDR_BASE,
 194         MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
 195         MISCREG_MC1_ADDR,
 196         MISCREG_MC2_ADDR,
 197         MISCREG_MC3_ADDR,
 198         MISCREG_MC4_ADDR,
 199
 200         MISCREG_MC_MISC_BASE,
 201         MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
 202         MISCREG_MC1_MISC,
 203         MISCREG_MC2_MISC,
 204         MISCREG_MC3_MISC,
 205         MISCREG_MC4_MISC,
 206
 207         // Extended feature enable register
 208         MISCREG_EFER,
 209
 210         MISCREG_STAR,
 211         MISCREG_LSTAR,
 212         MISCREG_CSTAR,
 213
 214         MISCREG_SF_MASK,
 215
 216         MISCREG_KERNEL_GS_BASE,
 217
 218         MISCREG_TSC_AUX,
 219
 220         MISCREG_PERF_EVT_SEL_BASE,
 221         MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
 222         MISCREG_PERF_EVT_SEL1,
 223         MISCREG_PERF_EVT_SEL2,
 224         MISCREG_PERF_EVT_SEL3,
 225
 226         MISCREG_PERF_EVT_CTR_BASE,
 227         MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
 228         MISCREG_PERF_EVT_CTR1,
 229         MISCREG_PERF_EVT_CTR2,
 230         MISCREG_PERF_EVT_CTR3,
 231
 232         MISCREG_SYSCFG,
 233
 234         MISCREG_IORR_BASE_BASE,
 235         MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
 236         MISCREG_IORR_BASE1,
 237
 238         MISCREG_IORR_MASK_BASE,
 239         MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
 240         MISCREG_IORR_MASK1,
 241
 242         MISCREG_TOP_MEM,
 243         MISCREG_TOP_MEM2,
 244
 245         MISCREG_VM_CR,
 246         MISCREG_IGNNE,
 247         MISCREG_SMM_CTL,
 248         MISCREG_VM_HSAVE_PA,
 249
 250         /*
 251          * Segment registers
 252          */
 253         // Segment selectors
 254         MISCREG_SEG_SEL_BASE,
 255         MISCREG_ES = MISCREG_SEG_SEL_BASE,
 256         MISCREG_CS,
 257         MISCREG_SS,
 258         MISCREG_DS,
 259         MISCREG_FS,
 260         MISCREG_GS,
 261         MISCREG_INT, // This isn't actually used.
 262
 263         // Hidden segment base field
 264         MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
 265         MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
 266         MISCREG_CS_BASE,
 267         MISCREG_SS_BASE,
 268         MISCREG_DS_BASE,
 269         MISCREG_FS_BASE,
 270         MISCREG_GS_BASE,
 271         MISCREG_INT_BASE,
 272
 273         // Hidden segment limit field
 274         MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
 275         MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
 276         MISCREG_CS_LIMIT,
 277         MISCREG_SS_LIMIT,
 278         MISCREG_DS_LIMIT,
 279         MISCREG_FS_LIMIT,
 280         MISCREG_GS_LIMIT,
 281         MISCREG_INT_LIMIT, // This isn't actually used.
 282
 283         // Hidden segment limit attributes
 284         MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
 285         MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
 286         MISCREG_CS_ATTR,
 287         MISCREG_SS_ATTR,
 288         MISCREG_DS_ATTR,
 289         MISCREG_FS_ATTR,
 290         MISCREG_GS_ATTR,
 291         MISCREG_INT_ATTR, // This isn't actually used.
 292
 293         // System segment selectors
 294         MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
 295         MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
 296         MISCREG_TR,
 297
 298         // Hidden system segment base field
 299         MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
 300         MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
 301         MISCREG_TR_BASE,
 302         MISCREG_GDTR_BASE,
 303         MISCREG_IDTR_BASE,
 304
 305         // Hidden system segment limit field
 306         MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
 307         MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
 308         MISCREG_TR_LIMIT,
 309         MISCREG_GDTR_LIMIT,
 310         MISCREG_IDTR_LIMIT,
 311
 312         // Hidden system segment attribute field
 313         MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
 314         MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
 315         MISCREG_TR_ATTR,
 316
 317         // Floating point control registers
 318         MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments,
 319
 320         //XXX Add "Model-Specific Registers"
 321
 322         NUM_MISCREGS
 323     };
 324
 325     static inline MiscRegIndex
 326     MISCREG_CR(int index)
 327     {
 328         return (MiscRegIndex)(MISCREG_CR_BASE + index);
 329     }
 330
 331     static inline MiscRegIndex
 332     MISCREG_DR(int index)
 333     {
 334         return (MiscRegIndex)(MISCREG_DR_BASE + index);
 335     }
 336
 337     static inline MiscRegIndex
 338     MISCREG_MTRR_PHYS_BASE(int index)
 339     {
 340         return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
 341     }
 342
 343     static inline MiscRegIndex
 344     MISCREG_MTRR_PHYS_MASK(int index)
 345     {
 346         return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
 347     }
 348
 349     static inline MiscRegIndex
 350     MISCREG_MC_CTL(int index)
 351     {
 352         return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
 353     }
 354
 355     static inline MiscRegIndex
 356     MISCREG_MC_STATUS(int index)
 357     {
 358         return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
 359     }
 360
 361     static inline MiscRegIndex
 362     MISCREG_MC_ADDR(int index)
 363     {
 364         return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
 365     }
 366
 367     static inline MiscRegIndex
 368     MISCREG_MC_MISC(int index)
 369     {
 370         return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
 371     }
 372
 373     static inline MiscRegIndex
 374     MISCREG_PERF_EVT_SEL(int index)
 375     {
 376         return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
 377     }
 378
 379     static inline MiscRegIndex
 380     MISCREG_PERF_EVT_CTR(int index)
 381     {
 382         return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
 383     }
 384
 385     static inline MiscRegIndex
 386     MISCREG_IORR_BASE(int index)
 387     {
 388         return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
 389     }
 390
 391     static inline MiscRegIndex
 392     MISCREG_IORR_MASK(int index)
 393     {
 394         return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
 395     }
 396
 397     static inline MiscRegIndex
 398     MISCREG_SEG_SEL(int index)
 399     {
 400         return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
 401     }
 402
 403     static inline MiscRegIndex
 404     MISCREG_SEG_BASE(int index)
 405     {
 406         return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
 407     }
 408
 409     static inline MiscRegIndex
 410     MISCREG_SEG_LIMIT(int index)
 411     {
 412         return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
 413     }
 414
 415     static inline MiscRegIndex
 416     MISCREG_SEG_ATTR(int index)
 417     {
 418         return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
 419     }
 420
 421     static inline MiscRegIndex
 422     MISCREG_SYSSEG_SEL(int index)
 423     {
 424         return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
 425     }
 426
 427     static inline MiscRegIndex
 428     MISCREG_SYSSEG_BASE(int index)
 429     {
 430         return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
 431     }
 432
 433     static inline MiscRegIndex
 434     MISCREG_SYSSEG_LIMIT(int index)
 435     {
 436         return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
 437     }
 438
 439     static inline MiscRegIndex
 440     MISCREG_SYSSEG_ATTR(int index)
 441     {
 442         return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
 443     }
 444
 445     /**
 446      * A type to describe the condition code bits of the RFLAGS register,
 447      * plus two flags, EZF and ECF, which are only visible to microcode.
 448      */
 449     BitUnion64(CCFlagBits)
 450         Bitfield<11> of;
 451         Bitfield<7> sf;
 452         Bitfield<6> zf;
 453         Bitfield<5> ezf;
 454         Bitfield<4> af;
 455         Bitfield<3> ecf;
 456         Bitfield<2> pf;
 457         Bitfield<0> cf;
 458     EndBitUnion(CCFlagBits)
 459
 460     /**
 461      * RFLAGS
 462      */
 463     BitUnion64(RFLAGS)
 464         Bitfield<21> id; // ID Flag
 465         Bitfield<20> vip; // Virtual Interrupt Pending
 466         Bitfield<19> vif; // Virtual Interrupt Flag
 467         Bitfield<18> ac; // Alignment Check
 468         Bitfield<17> vm; // Virtual-8086 Mode
 469         Bitfield<16> rf; // Resume Flag
 470         Bitfield<14> nt; // Nested Task
 471         Bitfield<13, 12> iopl; // I/O Privilege Level
 472         Bitfield<11> of; // Overflow Flag
 473         Bitfield<10> df; // Direction Flag
 474         Bitfield<9> intf; // Interrupt Flag
 475         Bitfield<8> tf; // Trap Flag
 476         Bitfield<7> sf; // Sign Flag
 477         Bitfield<6> zf; // Zero Flag
 478         Bitfield<4> af; // Auxiliary Flag
 479         Bitfield<2> pf; // Parity Flag
 480         Bitfield<0> cf; // Carry Flag
 481     EndBitUnion(RFLAGS)
 482
 483     /**
 484      * Control registers
 485      */
 486     BitUnion64(CR0)
 487         Bitfield<31> pg; // Paging
 488         Bitfield<30> cd; // Cache Disable
 489         Bitfield<29> nw; // Not Writethrough
 490         Bitfield<18> am; // Alignment Mask
 491         Bitfield<16> wp; // Write Protect
 492         Bitfield<5> ne; // Numeric Error
 493         Bitfield<4> et; // Extension Type
 494         Bitfield<3> ts; // Task Switched
 495         Bitfield<2> em; // Emulation
 496         Bitfield<1> mp; // Monitor Coprocessor
 497         Bitfield<0> pe; // Protection Enabled
 498     EndBitUnion(CR0)
 499
 500     // Page Fault Virtual Address
 501     BitUnion64(CR2)
 502         Bitfield<31, 0> legacy;
 503     EndBitUnion(CR2)
 504
 505     BitUnion64(CR3)
 506         Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
 507                                    // Base Address
 508         Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
 509                                // Base Address
 510         Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
 511                                  // Base Address
 512         Bitfield<4> pcd; // Page-Level Cache Disable
 513         Bitfield<3> pwt; // Page-Level Writethrough
 514     EndBitUnion(CR3)
 515
 516     BitUnion64(CR4)
 517         Bitfield<10> osxmmexcpt; // Operating System Unmasked
 518                                  // Exception Support
 519         Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
 520         Bitfield<8> pce; // Performance-Monitoring Counter Enable
 521         Bitfield<7> pge; // Page-Global Enable
 522         Bitfield<6> mce; // Machine Check Enable
 523         Bitfield<5> pae; // Physical-Address Extension
 524         Bitfield<4> pse; // Page Size Extensions
 525         Bitfield<3> de; // Debugging Extensions
 526         Bitfield<2> tsd; // Time Stamp Disable
 527         Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
 528         Bitfield<0> vme; // Virtual-8086 Mode Extensions
 529     EndBitUnion(CR4)
 530
 531     BitUnion64(CR8)
 532         Bitfield<3, 0> tpr; // Task Priority Register
 533     EndBitUnion(CR8)
 534
 535     // MTRR capabilities
 536     BitUnion64(MTRRcap)
 537         Bitfield<7, 0> vcnt; // Variable-Range Register Count
 538         Bitfield<8> fix; // Fixed-Range Registers
 539         Bitfield<10> wc; // Write-Combining
 540     EndBitUnion(MTRRcap)
 541
 542     /**
 543      * SYSENTER configuration registers
 544      */
 545     BitUnion64(SysenterCS)
 546         Bitfield<15, 0> targetCS;
 547     EndBitUnion(SysenterCS)
 548
 549     BitUnion64(SysenterESP)
 550         Bitfield<31, 0> targetESP;
 551     EndBitUnion(SysenterESP)
 552
 553     BitUnion64(SysenterEIP)
 554         Bitfield<31, 0> targetEIP;
 555     EndBitUnion(SysenterEIP)
 556
 557     /**
 558      * Global machine check registers
 559      */
 560     BitUnion64(McgCap)
 561         Bitfield<7, 0> count; // Number of error reporting register banks
 562         Bitfield<8> MCGCP; // MCG_CTL register present.
 563     EndBitUnion(McgCap)
 564
 565     BitUnion64(McgStatus)
 566         Bitfield<0> ripv; // Restart-IP valid
 567         Bitfield<1> eipv; // Error-IP valid
 568         Bitfield<2> mcip; // Machine check in-progress
 569     EndBitUnion(McgStatus)
 570
 571     BitUnion64(DebugCtlMsr)
 572         Bitfield<0> lbr; // Last-branch record
 573         Bitfield<1> btf; // Branch single step
 574         Bitfield<2> pb0; // Performance monitoring pin control 0
 575         Bitfield<3> pb1; // Performance monitoring pin control 1
 576         Bitfield<4> pb2; // Performance monitoring pin control 2
 577         Bitfield<5> pb3; // Performance monitoring pin control 3
 578         /*uint64_t pb(int index)
 579         {
 580             return bits(__data, index + 2);
 581         }*/
 582     EndBitUnion(DebugCtlMsr)
 583
 584     BitUnion64(MtrrPhysBase)
 585         Bitfield<7, 0> type; // Default memory type
 586         Bitfield<51, 12> physbase; // Range physical base address
 587     EndBitUnion(MtrrPhysBase)
 588
 589     BitUnion64(MtrrPhysMask)
 590         Bitfield<11> valid; // MTRR pair enable
 591         Bitfield<51, 12> physmask; // Range physical mask
 592     EndBitUnion(MtrrPhysMask)
 593
 594     BitUnion64(MtrrFixed)
 595         /*uint64_t type(int index)
 596         {
 597             return bits(__data, index * 8 + 7, index * 8);
 598         }*/
 599     EndBitUnion(MtrrFixed)
 600
 601     BitUnion64(Pat)
 602         /*uint64_t pa(int index)
 603         {
 604             return bits(__data, index * 8 + 2, index * 8);
 605         }*/
 606     EndBitUnion(Pat)
 607
 608     BitUnion64(MtrrDefType)
 609         Bitfield<7, 0> type; // Default type
 610         Bitfield<10> fe; // Fixed range enable
 611         Bitfield<11> e; // MTRR enable
 612     EndBitUnion(MtrrDefType)
 613
 614     /**
 615      * Machine check
 616      */
 617     BitUnion64(McStatus)
 618         Bitfield<15,0> mcaErrorCode;
 619         Bitfield<31,16> modelSpecificCode;
 620         Bitfield<56,32> otherInfo;
 621         Bitfield<57> pcc; // Processor-context corrupt
 622         Bitfield<58> addrv; // Error-address register valid
 623         Bitfield<59> miscv; // Miscellaneous-error register valid
 624         Bitfield<60> en; // Error condition enabled
 625         Bitfield<61> uc; // Uncorrected error
 626         Bitfield<62> over; // Status register overflow
 627         Bitfield<63> val; // Valid
 628     EndBitUnion(McStatus)
 629
 630     BitUnion64(McCtl)
 631         /*uint64_t en(int index)
 632         {
 633             return bits(__data, index);
 634         }*/
 635     EndBitUnion(McCtl)
 636
 637     // Extended feature enable register
 638     BitUnion64(Efer)
 639         Bitfield<0> sce; // System call extensions
 640         Bitfield<8> lme; // Long mode enable
 641         Bitfield<10> lma; // Long mode active
 642         Bitfield<11> nxe; // No-execute enable
 643         Bitfield<12> svme; // Secure virtual machine enable
 644         Bitfield<14> ffxsr; // Fast fxsave/fxrstor
 645     EndBitUnion(Efer)
 646
 647     BitUnion64(Star)
 648         Bitfield<31,0> targetEip;
 649         Bitfield<47,32> syscallCsAndSs;
 650         Bitfield<63,48> sysretCsAndSs;
 651     EndBitUnion(Star)
 652
 653     BitUnion64(SfMask)
 654         Bitfield<31,0> mask;
 655     EndBitUnion(SfMask)
 656
 657     BitUnion64(PerfEvtSel)
 658         Bitfield<7,0> eventMask;
 659         Bitfield<15,8> unitMask;
 660         Bitfield<16> usr; // User mode
 661         Bitfield<17> os; // Operating-system mode
 662         Bitfield<18> e; // Edge detect
 663         Bitfield<19> pc; // Pin control
 664         Bitfield<20> intEn; // Interrupt enable
 665         Bitfield<22> en; // Counter enable
 666         Bitfield<23> inv; // Invert mask
 667         Bitfield<31,24> counterMask;
 668     EndBitUnion(PerfEvtSel)
 669
 670     BitUnion32(Syscfg)
 671         Bitfield<18> mfde; // MtrrFixDramEn
 672         Bitfield<19> mfdm; // MtrrFixDramModEn
 673         Bitfield<20> mvdm; // MtrrVarDramEn
 674         Bitfield<21> tom2; // MtrrTom2En
 675     EndBitUnion(Syscfg)
 676
 677     BitUnion64(IorrBase)
 678         Bitfield<3> wr; // WrMem Enable
 679         Bitfield<4> rd; // RdMem Enable
 680         Bitfield<51,12> physbase; // Range physical base address
 681     EndBitUnion(IorrBase)
 682
 683     BitUnion64(IorrMask)
 684         Bitfield<11> v; // I/O register pair enable (valid)
 685         Bitfield<51,12> physmask; // Range physical mask
 686     EndBitUnion(IorrMask)
 687
 688     BitUnion64(Tom)
 689         Bitfield<51,23> physAddr; // Top of memory physical address
 690     EndBitUnion(Tom)
 691
 692     BitUnion64(VmCrMsr)
 693         Bitfield<0> dpd;
 694         Bitfield<1> rInit;
 695         Bitfield<2> disA20M;
 696     EndBitUnion(VmCrMsr)
 697
 698     BitUnion64(IgnneMsr)
 699         Bitfield<0> ignne;
 700     EndBitUnion(IgnneMsr)
 701
 702     BitUnion64(SmmCtlMsr)
 703         Bitfield<0> dismiss;
 704         Bitfield<1> enter;
 705         Bitfield<2> smiCycle;
 706         Bitfield<3> exit;
 707         Bitfield<4> rsmCycle;
 708     EndBitUnion(SmmCtlMsr)
 709
 710     /**
 711      * Segment Selector
 712      */
 713     BitUnion64(SegSelector)
 714         Bitfield<15, 3> si; // Selector Index
 715         Bitfield<2> ti; // Table Indicator
 716         Bitfield<1, 0> rpl; // Requestor Privilege Level
 717     EndBitUnion(SegSelector)
 718
 719     /**
 720      * Segment Descriptors
 721      */
 722
 723     BitUnion64(SegDescriptor)
 724         Bitfield<63, 56> baseHigh;
 725         Bitfield<39, 16> baseLow;
 726         Bitfield<55> g; // Granularity
 727         Bitfield<54> d; // Default Operand Size
 728         Bitfield<54> b; // Default Operand Size
 729         Bitfield<53> l; // Long Attribute Bit
 730         Bitfield<52> avl; // Available To Software
 731         Bitfield<51, 48> limitHigh;
 732         Bitfield<15, 0> limitLow;
 733         Bitfield<47> p; // Present
 734         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 735         Bitfield<44> s; // System
 736         SubBitUnion(type, 43, 40)
 737             // Specifies whether this descriptor is for code or data.
 738             Bitfield<43> codeOrData;
 739
 740             // These bit fields are for code segments
 741             Bitfield<42> c; // Conforming
 742             Bitfield<41> r; // Readable
 743
 744             // These bit fields are for data segments
 745             Bitfield<42> e; // Expand-Down
 746             Bitfield<41> w; // Writable
 747
 748             // This is used for both code and data segments.
 749             Bitfield<40> a; // Accessed
 750         EndSubBitUnion(type)
 751     EndBitUnion(SegDescriptor)
 752
 753     BitUnion64(SegAttr)
 754         Bitfield<0> writable;
 755         Bitfield<1> readable;
 756         Bitfield<2> expandDown;
 757         Bitfield<4, 3> dpl;
 758         Bitfield<5> defaultSize;
 759         Bitfield<6> longMode;
 760     EndBitUnion(SegAttr)
 761
 762     BitUnion64(GateDescriptor)
 763         Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
 764         Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
 765         Bitfield<31, 16> selector; // Target Code-Segment Selector
 766         Bitfield<47> p; // Present
 767         Bitfield<46, 45> dpl; // Descriptor Privilege-Level
 768         Bitfield<43, 40> type;
 769         Bitfield<36, 32> count; // Parameter Count
 770     EndBitUnion(GateDescriptor)
 771
 772     /**
 773      * Descriptor-Table Registers
 774      */
 775     BitUnion64(GDTR)
 776     EndBitUnion(GDTR)
 777
 778     BitUnion64(IDTR)
 779     EndBitUnion(IDTR)
 780
 781     BitUnion64(LDTR)
 782     EndBitUnion(LDTR)
 783
 784     /**
 785      * Task Register
 786      */
 787     BitUnion64(TR)
 788     EndBitUnion(TR)
 789 };
 790
 791 #endif // __ARCH_X86_INTREGS_HH__